Ultra low power clocking schemes using energy recovery and clock gating

PRESENTED BY: S.GOVINDA 3122603 VLSI DESIGN

OUTLINES
Motivation Power reduction methods Clock gating Energy recovery Four phase transmission gate ff Energy recovery flip-flops Clock gated ff Results Conclusions References

MOTIVATION
Demand for high performance is addressed by Increasing clock freq Increasing parallelism A significant portion of total power in highly synchronous systems is dissipated over clock networks

PROPOSED POWER REDUCTION METHODS

Energy recovery with clock gating
Use of sinusoidal clock instead of square wave clock Existing flip flop will work with this sinusoidal clock? Is there any need to design new flip flops ?

ENERGY RECOVERY
Developed for low power digital circuits
Achieve low power dissipation by Restricting current to flow across the device with low voltage drop Recycling the energy stored on the capacitors

needs ac type supply voltage

Uses a sinusoidal clock signal

The key questions

Which capacitance to recover from? Clock network? Gates? Bit lines? I/O? Other? Balancing? Other issues? How to store/reuse recovered energy? Capacitors? Inductors? How many power-clock phases? What circuits do the recovery? Power-clock generator design

CLOCK GENERATOR

Continued..

IMPACT OF PVT ON ER CLOCK

Amplitude of waveform is changes with changes in temperature Leads to malfunctioning of flip flops
Remedy: Introducing a pull-up transistor

CLOCK GATING
Technique for reducing power consumption during idle states Implementation: replace inverters with NAND gates

Continued

Waveform

COMPARISION

Four phase transmission gate ERCFF

Disadvantages
Longer delay from D to Q
Requirement of 4 phase clock

Requirement of 4 transmission gates results large chip area

PROPOSED FLIP FLOPS

Sense amplifier energy recovery flip flop(SAER) Static differential energy recovery flip flop(SDER) Differential conditional capturing energy recovery flip flop(DCCER) Single ended conditional capturing energy recovery flip flop(SCCER)

Sense amplifier energy recovery flip flop(SAER)

It is a dynamic flip flop It is used to operate with low voltage swing clock Uses single phase clock Operation: Difference between data inputs results in a initial voltage difference between SET and RESET Energy recovered from input capacitances No energy recovery from internal nodes

Simulated wave form:

Advantages:

SAER flip flop is fast Uses fairly low power at high switching activities Disadvantages
Either SET or RESET node is always charged or discharged every cycle regardless of data activity

leads to power consumption at low data switching activities

Static differential energy recovery flip flop(SDER)

It is a static flip flop Energy recovery clock is applied to minimum sized inverter skewed for fast high to low transition For sharper pulse we can use cascaded inverters No internal redundant switching on SET and RESET nodes if the input data remains idle

Differential conditional capturing energy recovery flip flop(DCCER)

Uses conditional capturing to eliminate redundant internal transitions Conditional capturing is implemented by using from output to control transistors

Effect of charge sharing is reduced

Largest transistor MN1 is placed at the bottom of the stack

Single ended conditional capturing energy recovery flip flop(SCCER)

ERFF with clock gating

RESULTS

CONCLUSION
Clock gating in energy recovery clocked flip-flops result in significant power savings during the idle state of the flip-flops without any considerable overhead compared to the original flip-flops for applications with very high sleep mode probability (above 72%) oscillator clock gating is the most power optimal clock gating solution for applications with lower idle state probabilities, flip-flop clock gating is the most power optimal clock gating approach. we can achieve 25% of power saving by using energy recovery and clock gating

REFERENCES
[1]Hamid mahmoodi, member, IEEE, vishy tirumalashetty, matthew cooke, and kaushik roy, fellow, IEEE Ultra Low-power Clocking Scheme Using Energy Recovery And Clock Gating, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, no. 1, january 2009 [2]Matthew cooke, hamid mahmoodi-meimand, kaushik roy Energy recovery clocking scheme and flip-flops For ultra low-energy applications [3]B. Voss and M. Glesner, A low power sinusoidal clock, IEEE International symposium on circuits and systems, pp. 108-1 11, may 2001. [4]B. Nikolic, V. G. Oklobdzija, V. Stojanovic, J. Wenyan, J. Kar-shing Chiu, and M. Ming-tak leung, improved sense-amplifier-based flipflop: Design and measurements, IEEE J. Solid-state circuits, vol. 35, Pp. 876884, jun. 2000