Low Power Cache Design

Swathi Roll no:22

Contents
Introduction Cache Memory DRAM 6T SRAM 7T SRAM Read and write delays Bit line Power Consumption

Introduction

Cache memory is the mainly used temporary storage of data in order to improve the performance of the processor. In general all the temporary storage devices are designed with RAM(Random Access Memory), like SRAM and DRAM. SRAM represents large portion of the chip. In order to get higher performance and longer battery life the SRAM shold have low power consumption. The power consumption means sum of the power consumption in decoders, BL(bit line), DL(Data line), sense amplifier and periphery circuits. Out of all these the BL has more power dissipation about 60% of the dynamic power .

Introduction
Power dissipation is given by P= BL CBL V2 Fwrite is the activity factor. Activity Factor: It is defined as the number of changes per clock cycle. In 6T SRAM the activity factor is equal to 1 and in the 7T SRAM the activity factor is less than 0.5 7T SRAM cell depends only on one of the BL to perform a write operation and thus reduces power consumption.

Cache Memory
A copy of data or program from main memory is stored in another location, which is nearer to the processor. The main intention in using this is we can reduce the average time to access the memory. Cache hit and miss Cache inbuilt L1,Cache on separate chip-L2. As the cache size increases power dissipation is going to increase. We have to design a cache in such a way that it has low power consumption.

Cache size Vs miss rate

DRAM

Dynamic Random Access Memory, is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. This set up is used to store one bit

Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically.

SRAM
Static Random Access Memory Each bit in SRAM is stored in four transistors, which form two cross coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access storage cell during the read and write operation. An SRAM cell has three different states : Standby mode: the circuit is idle,Read and write mode Access to the cell is enabled by the word line (WL).

6T SRAM Operation

Standby: The word line is not asserted, so the access transistors M5 and M6 disconnect the cell from the bit lines. Read mode: Both the bit lines are charged to one. One of the bit line is discharged based on the read value.

6T SRAM Operation

Write mode: The start of a write cycle begins by applying the value to be written to the bit lines. At a write operation the probability of one of the bit line pair equals to 1, which means that the activity factor of switching the bit line pair is equal to 1. Which gives more power consumption from the relation, P= CBL V2 Fwrite .

7T SRAM

An additional MOSFET is added to the 6T SRAM cell, as a feedback connection between those two inverters as shown in Fig.

Write Operation

Write operation starts by turning N5 off to cut off the feedback connection by making W=0. N3 is turned on by making WL:1 and N4 is kept off , since we are doing the write operation R:0.The resultant circuit is shown in the fig

Write operation
N3 transistor transfers the data from BL_bar to Q2, which drives the inv2, P2 and N2 to develop Q, the cell data. Similarly Q drives inv1,P1 and N1 to develop Q_bar which equals to Q2 if data is 0 ,slightly higher than Q2 if the data is 1. Both BL and BL_bar are precharged high. Using the write scheme, BL_bar is kept high to write 0 with negligible power consumption. To store 1 in the cell, BL_bar is discharged to 0 with comparable power consumption to the conventional 6T cell.

Read Operation

Both WL and R signals are turned on, while N5 is kept on. When Q=0, the read path consists of N2 and N4 and behaves like a 6T SRAM cell. When Q=1, the reads path consists of N1,N5 and N3

Read path when Q=0

Read path when Q=1

Read and Write delay

Read delay: It is defined as the time delay between 50% of the WL activation to when the sense amplifier has reached 90% of its full swing . Write delay: It is defined as the time between the activation 50% of WL to when Q_bar is 90% of its full swing. The write delay is approximately equals the propagation delay of inverter2 and inverter1. Because inv1 is only driving the diffusion capacitor of N5, it is better if its input capacitance reduces as much as possible to reduce the load on inv2.

Bit Line power consumption

In real applications most of the bits in cache are 0s, no need to discharge the BL (bit line) during writing 0, it leads in reducing the activity factor and then the power consumption reduces. In contradiction with above statement if an application more number of ones complement of data can be stored. In worst case, we are having saving power of 49% in which probability of writing 0 is equal to probability of writing 1.

Conclusion

The 7TSRAM cell reduces the activity factor by using only one of the BL to perform a write operation thereby reducing power consumption by at least half.

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