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BUS STRUCTURE

BUS
Bus is the mechanism by which the CPU communicates with memory and I/O devices Bus is not just a collection of wires Bus defines the protocol for communication

Bus (2)
Shared communication link single set of wires used to connect multiple subsystems A Bus is also a fundamental tool for composing large, complex systems
Processor Control Datapath Input

Memory
Output

What defines a bus?


Transaction Protocol
Timing and Signaling Specification

Bunch of Wires
Electrical Specification

Physical / Mechanical Characteristics the connectors

Address:
Data: Control:

Generic bus structure m


n

Generic Organization of a Bus


Control lines: Signal requests and acknowledgments Indicate what type of information is on the data lines Data lines carry information between the source and the destination: Data and Addresses
Address: special form of data

Complex commands

Bus Characteristics
Bus signals are usually tri-stated. Address and data lines may be multiplexed. Every device on the bus must be able to drive the maximum bus load:
Bus wires. Other bus devices.

Bus may include clock signal.


Timing is relative to clock.

Time Multiplexing
Share a single set of wires for multiple pieces of data Saves wires at expense of time
Master
data(15:0)

req

Servant
data(15:0)

Master
addr data

req

Servant
addr data

mux

demux

mux

demux

data(8)

addr/data

req data
15:8 7:0

req addr/data
addr data

data serializing

address/data muxing

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

Increasing the Bus Bandwidth


Non-multiplexed address and data lines:
Address and data can be transmitted in one bus cycle if separate address and data lines are available Cost: (a) more bus lines, (b) increased complexity

Data bus width:


By increasing the width of the data bus, transfers of multiple words require fewer bus cycles Cost: more bus lines

Block transfers:
Allow the bus to transfer multiple words in back-to-back bus cycles Only one address needs to be sent at the beginning The bus is not released until the last word is transferred Cost: (a) increased complexity (b) decreased response time for request

Advantages of Bus
Versatility:
New devices can be added easily

Low Cost:
A single set of wires is shared in multiple ways

Disadvantages of Bus
It creates a communication bottleneck
The bandwidth of the bus can limit the maximum I/O throughput

The maximum bus speed is largely limited by:


The length of the bus The number of devices on the bus The need to support a range of devices with:
Widely varying latencies Widely varying data transfer rates

Parallel communication
Multiple data, control, and possibly power wires One bit per wire High data throughput with short distances Typically used when connecting devices on same IC or same circuit board Bus must be kept short long parallel wires result in high capacitance values which requires more time to charge/discharge Data misalignment between wires increases as length increases Higher cost, bulky

Serial communication
Single data wire, possibly also control and power wires Words transmitted one bit at a time Higher data throughput with long distances Less average capacitance, so more bits per unit of time Cheaper, less bulky More complex interfacing logic and communication protocol Sender needs to decompose word into bits Receiver needs to recompose bits into word Control signals often sent on same wire as data increasing protocol complexity

Synchronous Bus
Includes a clock in the control lines A fixed protocol for communication that is relative to the clock Advantage: involves very little logic and can run very fast Disadvantages:
Every device on the bus must run at the same clock rate To avoid clock skew, they cannot be long if they are fast

Most processor-memory buses

Asynchronous Bus
Asynchronous Bus:
It is not clocked It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol

Basic Protocol Concepts


A bus transaction includes two parts:
Issuing the command (and address) request Transferring the data action

Master is the one who starts the bus transaction by:


issuing the command (and address)

Slave is the one who responds to the address by:


Sending data to the master if the master ask for data Receiving data from the master if the master wants to send data

Bus Arbitration
One of the most important issues in bus design:
How is the bus reserved by a device that wishes to use it?

Master-slave arrangement:
Only the bus master can control access to the bus:
It initiates and controls all bus requests

A slave responds to read and write requests

The simplest system:


Processor is the only bus master All bus requests must be controlled by the processor Major drawback: the processor is involved in every transaction

Basic Transaction Protocols


Master req Servant Master req ack data data Servant

req data

1 2

3 4

req ack data

1 2

3 4

taccess
1. Master asserts req to receive data 1. Master asserts req to receive data

2. Servant puts data on bus within time taccess


3. Master receives data and deasserts req 4. Servant ready for next request

2. Servant puts data on bus and asserts ack


3. Master receives data and deasserts req 4. Servant ready for next request

Strobe protocol

Handshake protocol

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

A strobe/handshake combination
Master req wait data Servant

req wait
data

req wait

1 2 3

2 taccess

data taccess 1. Master asserts req to receive data

1. Master asserts req to receive data 2. Servant puts data on bus within time taccess (wait line is unused) 3. Master receives data and deasserts req 4. Servant ready for next request

2. Servant can't put data within taccess, asserts wait ack 3. Servant puts data on bus and deasserts wait 4. Master receives data and deasserts req 5. Servant ready for next request

Fast-response case

Slow-response case

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

When to use handshake?


When response time cannot be guaranteed in advance:
Data-dependent delay. Component variations.

ISA bus protocol memory access


ISA: Industry Standard Architecture Features
20-bit address Compromise strobe/handshake control
4 cycles default Unless CHRDY deasserted resulting in additional wait cycles (up to 6)
Microprocessor
ISA bus memory-read bus cycle
CYCLE CLOCK D[7-0]

Memory

I/O Device

C1 C4

C2

WAIT

C3
DATA

A[19-0]
ALE /MEMR CHRDY

ADDRESS

memory-write bus cycle


CYCLE CLOCK D[7-0] A[19-0] ALE /MEMW CHRDY

C1 C4

C2

WAIT
DATA
ADDRESS

C3

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

Arbitration for Multiple Potential Bus Masters


Bus arbitration schemes usually try to balance two factors:
Bus priority: the highest priority device should be serviced first Fairness: Even the lowest priority device should never be completely locked out from the bus

Bus arbitration schemes can be divided into four broad classes:


Daisy chain arbitration Centralized, parallel arbitration Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. Distributed arbitration by collision detection: Each device just goes for it. Problems found after the fact.

The Daisy Chain


Device 1 Highest Priority Grant Bus Arbiter Grant

Advantage: simple
Device 2 Device N Lowest Priority Grant Release Request

wired-OR Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed

Centralized Parallel Arbitration


Device 1 Device 2 Device N

Grant
Bus Arbiter

Req

Used in essentially all processor-memory busses and in high-speed I/O busses

Arbitration: Priority arbiter


Types of priority
Fixed priority
each peripheral has unique rank highest rank chosen first with simultaneous requests preferred when clear difference in rank between peripherals

Rotating priority (round-robin)


priority changed based on history of servicing better distribution of servicing especially among peripherals with similar priority demands

Arbitration using a priority arbiter


Microprocessor System bus Inta Int 3 Ireq1 Iack1 Ireq2 Iack2 6 5 Priority arbiter Peripheral1 Peripheral2 7

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

Arbitration using a priority arbiter (2)



Microprocessor is executing its program. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq2. Priority arbiter sees at least one Ireq input asserted, so asserts Int. Microprocessor stops executing its program and stores its state. Microprocessor asserts Inta. Priority arbiter asserts Iack1 to acknowledge Peripheral1.

Arbitration using a priority arbiter(3)


Peripheral1 puts its interrupt address vector on the system bus Microprocessor jumps to the address of ISR read from data bus, ISR executes and returns (and completes handshake with arbiter). Microprocessor resumes executing its program

Increasing Transaction Rate on Multi-master Bus


Overlapped arbitration
perform arbitration for next transaction during current transaction

Bus parking
master holds onto bus and performs multiple transactions as long as no other master makes request

Overlapped address / data phases


requires one of the above techniques

Increasing Bus transaction rate (2)


Split-phase (or packet switched) bus
completely separate address and data phases arbitrate separately for each address phase yield a tag which is matched with data phase

All of the above in most modern memory buses

Direct memory access


Direct transfer of data by-passing CPU Using DMA controller
Separate single-purpose processor Microprocessor relinquishes control of system bus to DMA controller Microprocessor can meanwhile execute its regular program
No inefficient storing and restoring state due to ISR call Regular program need not wait unless it requires the system bus Harvard architecture processor can fetch and execute instructions as long as they dont access data memory if they do, processor stalls

Peripheral to memory transfer with DMA


1(a): P is executing its main program. It has already configured 3: DMA ctrl asserts Dreq to the DMA ctrl registers. request control of system bus. 4: After executing an instruction, P sees Dreq 5: (a) DMA ctrl asserted, releases the system asserts ack (b) bus, asserts Dack, and reads data from resumes execution. P stalls 0x8000 and (b) only if it needs the system bus writes that data to to continue executing. 0x0001. 7(a): P de-asserts Dack and resumes control of the bus. 6:. DMA deasserts Dreq and ack completing handshake with P1. 1(b): P1 receives input data in a register with address 0x8000.

2: P1 asserts req to request servicing by DMA ctrl.

7(b):

P1 de-asserts req.

ISA bus DMA cycles


Processor ISA-Bus R A DMA Memory

R
A I/O Device

DMA Memory-Write Bus Cycle

DMA Memory-Read Bus Cycle

CYCLE

CLOCK
D[7-0] A[19-0] ALE /IOR /MEMW CHRDY

C1 C7

C2

C3

C4

C5

C6

CYCLE CLOCK

C1 C7

C2

C3

C4

C5

C6

DATA ADDRESS

D[7-0] A[19-0] ALE /MEMR /IOW CHRDY

DATA
ADDRESS

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

Multilevel bus architectures


One bus for all communication
Peripherals would need high-speed, processorspecific bus interface
excess gates, power consumption, and cost; less portable
Microprocessor Cache Memory controller DMA controller

Processor-local bus

Peripheral

Peripheral

Peripheral

Bridge

Too many peripherals slows down bus


Peripheral bus

Multi-level Buses
Processor-local bus
High speed, wide, most frequent communication Connects microprocessor, cache, memory controllers, etc.

Peripheral bus
Lower speed, narrower, less frequent communication Typically industry standard bus (ISA, PCI) for portability

Bridge
Single-purpose processor converts communication between busses

Parallel protocol: PCI Bus


PCI Bus (Peripheral Component Interconnect)
High performance bus originated at Intel in the early 1990s Standard adopted by industry and administered by PCISIG (PCI Special Interest Group) Interconnects chips, expansion boards, processor memory subsystems Data transfer rates of 127.2 to 508.6 Mbits/s and 32-bit addressing Synchronous bus architecture Multiplexed data/address lines

PCI Bus Architecture

Ref: IEEE Computer, 1999 Weiss & Finkelstein

PCI Read/Write Transactions


All signals sampled on rising edge Centralized Parallel Arbitration
overlapped with previous transaction

All transfers are (unlimited) bursts Address phase starts by asserting FRAME# Next cycle initiator asserts cmd and address

PCI Read/Write Transactions


Data transfers happen on when
IRDY# asserted by master when ready to transfer data TRDY# asserted by target when ready to transfer data transfer when both asserted on rising edge

FRAME# de-asserted when master intends to complete only one more data transfer

PCI Variants for Embedded Systems


PC/104: Embedded system version of the ISA bus
Incorporate 16 and x86 processors running at 16 to 33 Mhz Bandwidth: 5 Mbytes/s

PC/104: Standard that specifies PC/104 size cards with both ISA and PCI
Enabling use of Pentium CPU in Embedded system A new form factor and a pass through connector

PC/104
Small Size: 3.6 x 3.8 P1 Bus has 64 pins like PC-XT P2 Bus has 40 pins
(note: 64+40=104 as in PC/104)

Provides full AT compatibility Replaces card edge connector with more reliable pin-and-socket Up to 4 modules can be stacked

Single Board Computers


Intel pioneered the concept of a single board computer (SBC) with the first industry standard mezzanine board called iSBX that provided additional I/O PC architecture redefined and vitalized the popularity of the SBC SBCs allowed companies to:
Make their design portable from one version to the next Shorten product development time Focus manpower on product instead of the platform

SBC
SBCs follow the technology developed by the PC Industry Basic Architecture ISA/PCI Bus protocol Serial & Parallel Port The latest SBCs provide all the flexibility and power of a PC with very small space requirements PC/104 and PC/104 plus meet the need of SBCs

Summary
We have studied about Bus connecting CPU to memory and I/O devices There may be more than one bus master
We need arbitration

We shall look at the nature of buses used in SOCs We shall also study serial buses

BUS STRUCTURE-2
SOC BUS SERIAL BUS

Recap: SBC
SBCs follow the technology developed by the PC Industry
Basic Architecture ISA/PCI Bus protocol Serial & Parallel Port

The latest SBCs provide all the flexibility and power of a PC with very small space requirements
Software Compatibility

PC/104 and PC/104 plus meet the need of SBCs


Small foot-print to suit the requirement of embedded appliances

PCI Bus Architecture

Ref: IEEE Computer, 1999 Weiss & Finkelstein

Bridge
A bridge is a slave on the fast bus and master of the slow bus Takes command from the fast bus on which it is slave Issues commands on the slow bus Returns results from slow bus to fast bus Also functions as protocol translator

The System-on-a-Chip
System Bus
DMA CPU DSP

Mem Ctrl. Bridge

MPEG

I C

Custom Interfaces Control Wires Peripheral Bus

System-on-a-chip (SoCs) requires busing systems to connect various components, including one or more microprocessors, memory, peripherals, and special logic

ARM Processor Bus Interface


ARM provides Advanced Micro controller Bus Architecture (AMBA)
ARM processor uses AMBA to interface to the System Bus

AMBA standardizes the bus interface Allows increased re-use of IP in designs Enable the creation of upgrades and families of devices

Arbiter

AMBA
ARM
Bus Interface On-chip RAM

Reset

TIC Bridge External ROM External RAM Timer

External Bus Interface

Remap/ Pause

Decoder

Interrupt Controller

AHB or ASB System Bus

APB Peripheral Bus

AMBA: ARMs on chip bus specification

AMBA
AMBA is a multi-level Bus ASB/AHB: Advanced System Bus: To connect High Performance modules APB: Advanced Peripheral Bus: Simpler interface for low performance peripherals Support 32-, 64-, and 128-bit data-bus implementations with a 32-bit address bus
as well as smaller byte and half-word designs.

Synchronous, non-multiplexed buses that support bursting and pipelining

AMBA based System


System bus interconnects a processor in a SOC with memory controllers, on-chip memory, and DMA controllers Slower peripherals are connected to the slower, simpler APB peripheral bus. System and peripheral buses can run at different clock rates. They link via a bridge that buffers data and operations between the two buses.

AHB & ASB


Busses are multi-master Use a central arbiter Each transfer has an address and control cycle Pipelined
able to start the next transfer's arbitration and address phase while finishing the current transfer

AHB
The AHB puts the address on the bus, followed by the data. It supports wait-state insertion and has a data-valid signal (HREADY). It has separate read (HRDATA) and write (HWDATA) buses.

AHB operation
AHB supports bursts, with 4-, 8-, and 16-beat bursts, as well as undefinedlength bursts and single transfers.
Bursts can be address wrapped, i.e., staying within a fixed address range. Slaves can insert wait states to adjust its response (up to 16).

Bus operation
All bus operations are initiated by bus masters, which also can serve as a slave. The master-generated address is decoded by a central address decoder that provides a select signal to the addressed bus slave unit. The bus master can "lock" the bus, reserving it with the central arbiter for a series of locked transfers.

Arbitration
Master x requests for the AHB by issuing req[x] When bus is available the arbiter issues a hgrant[x] to master x Upon receiving grant signal master issues address and control information to indicate the type of transfer

Simple Arbiter Scheme


arbiter

master 1

address write data

slave 1

master 2

slave 2

master 3

read data decoder

slave 3

Bus transaction
The slave unit has the option to terminate a transaction
as an error, signal the master to retry, or split the transaction for later completion.

Split transactions enable the slave to defer the operation until it's able to accomplish it,
thereby releasing the bus for other accesses.

Split Transaction
The slave signals a split transaction and saves the master number (HMASTER[]). When ready to complete the transaction, the slave signals the arbiter with the master number. When the arbiter grants bus access to the master, it restarts the transaction.
No master can have more then 1 pending split transaction.

AHB Signals

AHB Protection Control Signals


HPROT[1:0] : Protection control signals provide additional information about a bus access
Primarily intended for use by a bus decoder when acting as a basic protection unit. The signals indicate
if the transfer is an op-code fetch or data access, if the transfer is a supervisor mode access or user mode access.

The signals are driven by the active bus master and have the same timing as the address bus.

Some more AHB Signals


HSIZE[1:0]
The transfer size signals indicate the size of the transfer, which may be byte, half-word word. The signals are driven by the active bus master and have the same timing as the address bus.

HTRANS[1:0]
Transfer signals indicate the type of the next transaction, which may be address-only, nonsequential or sequential. These signals are driven by a bus master when the appropriate GRANTx signal asserted.

Timing Diagram

ARM Core AMBA Interface


ARM core cannot understand AMBA signaling standards directly.
It needs an interface unit for decoding and translation to ASB/AHB signals Some signals are just renamed

ARM Core ASB Interface Wrapper

APB
Designed to support low-speed peripherals such as UARTs, keypads, and PIO All bus devices are slaves to the master, the bridge to the AHB, or ASB system bus. Provides a simple address, with latched address and control signals for easy interfacing. APB can be implemented with a single tristated data bus.

APB Bridge

APB Transaction
As a simple bus, the APB doesn't support bursting. Each transaction consists of 2 cycles: an address cycle (Setup state) and a data cycle (Enable state). The bus uses a single clock, PCLK.
In Setup, the bus brings PSEL and PWRITE up, putting the address on the PADDR address bus. In the Enable state, it brings PENABLE up and places data on the PWDATA/PRDATA bus. The enable signal, PENABLE, is de-asserted on the next clock.

System Architecture

ARM SYSTEM Architecture

Open Core Protocol


Open core defines a comprehensive
bus independent,
high performance, configurable interface

Connecting IP cores and on-chip communication interface Synthesis/Timing Analysis Friendly Encompass entire core/system interface needs (data, control, and test flows)

Master vs. Slave


IP Core
Master

IP Core
Master Slave

IP Core
Slave Request Response

Open Core Protocol Initiator Slave

Slave

Master

Target

Master

On-Chip Bus

Protocol Phases
Request Phase (begins Transfer)
Master presents request (command, address, etc.) to Slave

Response Phase (ends Transfer)


Slave presents response (success/fail, read data) to Master Only available for read transfers (posted write model)

Protocol Phases
Datahandshake Phase (Optional)
Allows pipelining request ahead of write data Only available for write transfers

Phase ordering
Request -> Datahandshake -> Response

Use of Protocol
A designer selects only those signals and features from the palette of OCP configurations needed to fulfill all of an IP cores unique data, control and test signaling requirements

Serial Buses

Serial Protocol
Used for moving data quickly from one device to another Serial protocols like I2C & SPI are meant for short distances inside the box
Low complexity Low cost

I2C
Meant for inter-Integrated Circuit Communication Developed by Philips Semiconductor for TV sets in the 1980s I2C devices include EEPROMs, thermal sensors, and real-time clocks Used as a control interface to signal processing devices that have separate data interfaces, e.g. RF tuners, video decoders and encoders, and audio processors.

I2C: Features
Bi-directional
Data can flow in both directions

Synchronous
Data is clocked along with a clock signal Clock signal controls when data is changed and when it should be read Clock rate can vary unlike asynchronous (RS-232 style) communication I2C bus has three speeds: Slow (under 100 Kbps) Fast (400 Kbps) High-speed (3.4 Mbps) I2C v.2.0

I2C: Connections
Two wired bus
Serial data line(SDA) Serial Clock line (SCL)

Voltage Levels
High - 1 Low - 0

Bit transfer
SCL=1 implies SDA = valid data Stable data during high clock Data change during low clocks

Basic Protocol
I2C is a master slave protocol
Master device controls the clock (SCL) Slave devices may hold the clock low to prevent data transfer No data is transferred unless a clock signal is present All slaves are controlled by the master clock

Summary
We have studied bus specifications used in a SOC Looked at a serial bus for connecting devices to a micro-controller We shall learn more about serial buses in the next class

Bus Structure-3
Serial Interfaces

I2C: Basics
Two wired bus
Serial data line(SDA) Serial Clock line (SCL)

Voltage Levels
High - 1 Low - 0

Bit transfer
SCL=1 implies SDA = valid data Stable data during high clock Data change during low clocks

I2C Signals
I2C lines can have two possible states
Float high Drive low

Pull-up resistor on the line and only devices pull the line low
If no device is pulling on the line it will float high

Wired-and Connection
Bus is free implying SDA and SCL are high
By pull-up resistors

Device output is AND-ed with signal on bus

Frame
Start Condition(S)
SDA 1->0 transition when SCL=1

Stop Condition(P)
SDA 0->1 transition when SCL=1

Repeated start (Sr)


Start is generated instead of stop

Bus state
Busy - after S and before next P Free after P and before next S

Data transfer
Data bits are transferred after start condition Transmission is byte oriented
8 bits + 1 acknowledge bit

Most significant bit first Address of the slave is also data


First byte is address During first byte transfer
Master is the transmitter Addressed slave is receiver

Next bytes: depend on the last bit in the address byte

Addressing Scheme
First byte transmitted by master
7 bits: address 1 bit: direction(R/W)
0 master writes data 1 master receives data

Master may generate repeated start and address another device Each device listens to address
If address matches device switches state according to R/W bit

Data Transfer SCL


Master sets SCL=0 and generates pulse for each data bit
8 pulses for data followed by one for ack

After ack
Master tries to generate next bytes first pulse Slave can hold SCL low forcing master to switch to wait state

Data transfer SCL

Data transfer -SDL


Data bits are generated by transmitter as SCL pulses 9th pulse
Transmitter releases SDA Receiver must hold SDA low in order to ack received data Slave must release SDA after acknowledge bit

Data transfer SDL

Frame Format

Bus Arbitration
I2C designed as a multi-master bus
Any one of several different devices may act as the master at various times No global master to generate clock
A master drives both SCL and SDL

When two devices try to drive SDL to different values


Listen to the bus to be sure that is not interfering with another message
If the device is trying to send a logic 1 but hears logic 0 , it immediately stops transmission and gives the other sender priority

Bus Arbitration (2)


Synchronization needed on SCL Arbitration needed on SDA

I2C in PIC
In PIC micro-controller MSSP module provides the support for I2C

MSSP

SSPBUF: a register that stores data sent or received on I2C bus

I2C in PIC

Controls actions of the device based I2C instructions

I2C Engine implements I2C protocol in hardware

I2C Tradeoffs
Advantages:
Good for communication with on-board devices that are accessed occasionally. Easy to link multiple devices because of addressing scheme Cost and complexity do not scale up with the number of devices

Disadvantages:
The complexity of supporting software components can be higher than that of competing schemes ( for example, SPI ).

SPI
Shorthand for Serial Peripheral Interface Defined by Motorola on the MC68HCxx line of microcontrollers
Generally faster than I2C, capable of several Mbps

Applications:
Like I2C, used in EEPROM, Flash, and real time clocks Better suited for data streams, i.e. ADC converters Full duplex capability, i.e. communication between a codec and digital signal processor

SPI Bus Configuration


SCLK MOSI MISO /SS

Master

Slave

Bus Signals
Synchronous serial data link operating at full duplex Master/slave relationship 2 data signals:
MOSI master data output, slave data input
Also called SDO : serial data output

MISO master data input, slave data output


Also called SDI: serial data input

2 control signals:
SCLK clock /SS slave select (no addressing)

SPI vs. I2C


For point-to-point, SPI is simple and efficient
Less overhead than I2C due to lack of addressing, plus SPI is full duplex.

For multiple slaves, each slave needs separate slave select signal
More effort and more hardware than I2C

Single master, multiple slave SPI implementation

SPI Protocol

2 Parameters, Clock Polarity (CPOL) and Clock Phase (CPHA), determine the active edge and idle state of the clock
CPOL 0 0 1 1 CPHA 0 1 0 1 Active edge Rising Falling Falling Rising

Master and slave must agree on parameter pair values in order to communicate

SPI Protocol (2)


SPI interface defines only the communication lines and the clock edge There is no specified flow control
No acknowledgement mechanism to confirm receipt of data

Hardware realization can be done with a simple shift register

SPI in PIC
The SSP and MSSP module in PIC can implement SPI protocol
I2C by MSSP only

SSPCON register used for managing SPI


Some bits used:
SSPOV : serial port overflow SSPEN: synchronous serial port enable CKP : clock polarity

SSPSTAT register is also used


Some bits used:
CKE: Clock edge select BF: Buffer full

Data transfer Mechanism


Shift register loaded by SPI data or from SSPBUF

Serial buffer: Data is put after SPI transfer or before SPI transfer

Communicating with Embedded System

USB
USB is a serial protocol and physical link
transmits all data differentially on a single pair of wires. Another pair provides power to downstream peripherals

PC centric protocol Every USB device is an embedded system.

Bit serial bus


USB uses bit-serial, differential drive technology

USB signaling
Speeds:
High-speed is 480 Mb/s. Full-speed is 12 Mb/s. Low-speed is 1.5 Mb/s.

Signals:
Vbus, Gnd. D+, D-.

USB power
USB devices can pull a limited amount of power from the bus.
May also supply their own power.

System may provide a powermanagement protocol.


Independent of USB.

USB architecture
USB Peripherals are slaves responding to commands from the host. When a peripheral is attached to the USB network, the host communicates with the device
To learn its identity and To discover which device driver is required (a process called enumeration ).

USB devices
The specification recognizes two kinds of peripherals:
Stand-alone (single function units, like a mouse) Compound devices (those that have more than one peripheral sharing a USB port).
An example of a compound device is a video camera with separate audio processor.

USB bus protocol


Polled bus, all transfers initiated by host. Basic transaction:
Host sends token packet:
Type and direction. USB device number. Endpoint number (subdevice).

Data transfer packet. Acknowledge packet.

Summary
We have studied serial interfaces for connecting peripherals We have also looked at serial bus protocol for connecting embedded systems to hosts

Serial Intefaces
USB, IEEE 1394, IrDA

Recap: USB bus protocol


Polled bus, all transfers initiated by host. Basic transaction:
Host sends token packet:
Type and direction. USB device number. Endpoint number (subdevice).

Data transfer packet. Acknowledge packet.

Bus Protocol
data transfer

token

Type of transaction Direction of trans. handshake USBdevice address

Host controller initiates data transfer by generating token packet Data transferred Handshake packet for completion

Attach and Remove of USB Devices


Host
Enable port allocate Remove USB address upstream port indicato indicato disable r r

port

Hub
port

port

device

USB Organization

USB Hubs
Hubs are bridges
Increase the logical and physical fan-out of the network.
A hub has a single upstream connection Many downstream connections.

Hubs are themselves USB devices Hubs detect topology changes due insertion/deletion of devices. They also source power to the USB network

USB Communication
Communications between the host and endpoints located in the peripherals.
An endpoint is a uniquely addressable portion of the peripheral that is the source or receiver of data. Four bits define the device's endpoint address; Codes also indicate transfer direction and the transaction

PIPE
Pipe: all transfers occur through virtual pipes that connect the peripheral's endpoints with the host. When establishing communications with the peripheral, each endpoint returns a descriptor
Descriptor is a data structure that tells the host about the endpoint's configuration and expectations.
Include transfer type, max size of data packets, perhaps the interval for data transfers, and in some cases, the bandwidth needed.

Types of data transfer


Four data transfer types:
control, Isochronous Bulk interrupt.

Control transfers exchange configuration, setup, and command information between the device and the host.

Bulk data transfer


Bulk transfers move large amounts of data when timely delivery isn't critical.
Typical applications include printers and scanners. Bulk transfers are fillers, claiming unused USB bandwidth when nothing more important is going on.

Interrupt transfer
Interrupt transfers, though not interrupts in the CPU-diverting sense, poll devices to see if they need service.
Peripherals exchanging small amounts of data that need immediate attention (such as mice and keyboards) use interrupt transfers. Error checking validates the data.

Isochronous transfer
Isochronous data transfer ensures that data flows at a pre-set rate so that an application can handle it in a timed way. Isochronous transfers handle streaming data like that from an audio or video device. It is time sensitive information so, within limitations, it has guaranteed access to the USB bus. No error checking occurs so the system must tolerate occasional scrambled bytes.

IEEE 1394

IEEE 1394 (Firewire)


400 Mbps and more( 3200Mbps for 1394b ) Plug & play Provides power Comparison to USB
USB is host-based(must be connected to computer)

IEEE 1394 is peer connected directly)

to peer (two devices can be

Firewire:features
Packet-based layered design structure Applications using FireWire include:
disk drives, printers, scanners, cameras

Capable of supporting a LAN similar to Ethernet


64-bit address:
10 bits for network ids, 1023 subnetworks 6 bits for node ids, each subnetwork can have 63 nodes 48 bits for memory address, each node can have 281 terabytes of distinct locations

IEEE 1394 Applications

Source: Texas Instruments

Connecting Devices
In work area #1 a video camera, PC, and video recorder, all interconnected PC is also connected to a physically distant printer via a 1394 repeater
Repeater extends the interdevice distance by redriving the 1394 signals.

A 1394 splitter is used to provide another port to attach a 1394 bus bridge.
Source: http://www.pctechguide.com/26interfaces_IEEE_1394.htm

Connecting Devices
The 1394 bus bridge isolates data traffic within each work area. Bus bridges allow selected data to be passed from one bus segment to another.
PC #2 can request image data from the video recorder in work area #1. Since the 1394 cable is powered, the signalling interface is always powered Video data is transported even if PC #1 is powered off.
Source: http://www.pctechguide.com/26interfaces_IEEE_1394.htm

Protocol Stack

Soure: Xilinx

Physical Layer
Physical layer provides the initialization and arbitration services
It assures that only one node at a time is sending data

Includes
Electrical signaling Mechanical connectors and cabling Arbitration mechanism Serial coding and decoding of data being transferred or received Transfer speed detection

Link Layer
Extracts and put data packets on and off the wire Does error detection and correction Does retransmission Handles provision for cycle control for isochronous channel Link layer supplies an acknowledged datagram to the transaction layer
A datagram is a one-way data transfer with request confirmation

Transaction Layer
Implements Request-response protocol Minimizes amount of circuitry required to interconnect with standard buses such as the PCI bus

Host Controller

Soure: Xilinx

Wireless Protocol
IRDA

Wireless communication
Infrared (IR)
Electronic wave frequencies just below visible light spectrum Diode emits infrared light to generate signal Infrared transistor detects signal, conducts when exposed to infrared light Cheap to build Need line of sight, limited range

IrDA
IrDA is a standard defined by the IrDA consortium (Infrared Data Association). Specifies a way to wirelessly transfer data via infrared radiation. Specifications include standards for both the physical devices and the protocols they use to communicate with each other. Can connect various mobile/embedded systems
Primary use has been to link notebooks or various personal communicators

Features
Most IrDA work over distances up to 1.0m with BER 10-9 and maximum level of surrounding illumination 10klux (daylight).
Bit Error Ratio - number of incorrectly transferred bits over number of correctly transferred bits

Pulse modulation with 3/16 of the length of the original duration of a bit is used. Data format is the same as for a serial port asynchronously transmitted word, with a start bit at the beginning.

Pulse width
Transmitter can use either 3/16 mark-tospace ratio for one bit, or a fixed length 1.63 us of each optical pulse, which would correspond to 115kbps (ver1.0).

IR Frame

Why pulse modulation?


The receiver needs to distinguish between the surrounding illumination, noise, and received signal. Useful to use the highest possible output power:
higher power -> higher current in the receiver -> better signal-to-noise ratio.

IR-LED's can not transmit at full power continuously over 100% of time. So, a pulse width of only 3/16 of the total time for one bit is used.

Advantages of Pulse modulation


Power can be up to 4 or 5 times the possible maximum power for LED's shining continuously. The transmission path does not carry the dc component
Receiver continuously adapts itself to the surrounding illumination, and detects changes only.

Integrated IrDA transceivers do have filters that eliminate noise other than the IrDA frequency range 2400-115200 bps

Packet Structure
A packet consists of two start words followed by target address
IrDA devices are assigned numbers by the means of IrDA protocol, so they are able to unambiguously identify themselves

Followed by data, CRC-16 and a stop word. The whole packet (frame) including CRC-16 is generated by IrDA compatible chipset. Start and stop words last 1.5times the bit duration (6 times longer flash than usual).

Protocols
IrDA Infrared Link Access Protocol (IrLAP)
Encapsulates the frames Provides arbitration
Only one primary device, others are secondary The communication is always half-duplex

Describes how the devices establish connection, close it, and how are they going to be internally numbered.

IrDA Protocols
IrDA Infrared Link Management Protocol (IrLMP)
Every device lets the others know about itself via the IrLMP protocol, which runs above IrLAP IrLMP's goal is to detect presence of devices offering a service, to check data flow, and to act as a multiplexer for configurations with more devices with different capabilities involved Applications use the IrLMP layer to ask if a required device is within range, etc.

Protocols
IrDA Transport Protocols (Tiny TP)
This layer manages virtual channels between devices, performs error corrections (lost packets, etc.), divides data into packets, and reassembles original data from packets.

IrDA Object Exchange Protocol (IrOBEX)


Defines PUT and GET commands, thus allowing binary data transfer between devices. The standard defines what a packet must contain in order for the devices to recognize each other and communicate.

Application Protocols
Extensions to IrOBEX for Ir Mobile Communications
Extension for mobile devices - handhelds, PDA, cellular phones - defines how to transfer informations pertaining to GSM network
address books, SMS, calendar, dialing control, digital voice transfer over IR, etc.

IrTran-P (Infrared Transfer Picture) Specification


Specifies how to transfer pictures over the infrared interface.

Application of IrDA

Wireless Communication
Radio frequency (RF)
Electromagnetic wave frequencies in radio spectrum Analog circuitry and antenna needed on both sides of transmission Line of sight not needed, transmitter power determines range

Generic Issues

Error detection and correction


Often part of bus protocol Error detection: ability of receiver to detect errors during transmission Error correction: ability of receiver and transmitter to cooperate to correct problem
Typically done by acknowledgement/retransmission protocol

Bit error: single bit is inverted


Always detects single bit errors, but not all burst bit errors

Error detection and Correction


Burst of bit error: consecutive bits received incorrectly Parity: extra bit sent with word used for error detection
Odd parity: data word plus parity bit contains odd number of 1s Even parity: data word plus parity bit contains even number of 1s Checksum: extra word sent with data packet of multiple words
e.g., extra word contains XOR sum of all data words in packet

Trends in Bus structure


Switched Serial Inter-Connect
Packet switching

Serial high speed buses for connecting processor to memory and peripherals Use of packet switching for improving transfer efficiency
Split transaction

Example: PCI-express

Summary
We have studied about bus structures used for connecting CPU and peripherals We have also looked at the interface specifications for connecting two or more systems

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