Broad family of TIs 16-bit microcontrollers

from 1Kbytes ROM, 128 bytes RAM (approx. $1 ) to 60Kbytes ROM, 10Kbytes RAM ( $10)

Three subfamilies
MSP430x1xx: basic unit MSP430x3xx: more features MSP430x4xx: built-in LCD driver

Device Production Sampling Development Future

5xx-Next Gen
25 MIPS 32-256 KB USB-RF
F23x-F24x F23x0 F22xx F261x F241x F563x USB F543x F5xx F5xx RF

Performance

2xx-Catalog

F20xx

F21x1

1xx-Catalog
8 MIPS 1-60KB

F15x-F16x F13x-F14x F12xx F/C11xx

F21x2

16 MIPS 1-120KB 500nA Stand By

F471x7 Fx43x F44x F47x4 CG461x FG461x

4xx-LCD

Fx42x
Fx42x0 F/C41x

8/16 MIPS 4-120KB LCD Driver

F = Flash C = Custom ROM

Integration

Handheld Measurement Air Flow measurement Alcohol meter Barometer Data loggers Emission/Gas analyser Humidity measurement Temperature measurement Weight scales Medical Instruments Blood pressure meter Blood sugar meter Breath measurement EKG system

Utility Metering Home environment Gas Meter Air conditioning Water Meter Control unit Heat Volume Counter Thermostat Heat Cost Allocation Boiler control Electricity Meter Shutter control Meter reading system (RF) Irrigation system White goods Sports equipment (Washing machine,..) Altimeter Bike computer Misc Diving watches Smart card reader Taxi meter Security Smart Batteries Glass break sensors Door control Smoke/fire/gas detectors

RISC architecture with 27 instructions and 7 addressing modes. Full register access including program counter, status registers, and stack pointer. Single-cycle register operations. Large 16-bit register file reduces fetches to memory. 16-bit address bus allows direct access and branching throughout entire memory range. 16-bit data bus allows direct manipulation of word-wide arguments. Constant generator provides six most used immediate values and reduces code size. Direct memory-to-memory transfers without intermediate register holding. Word and byte addressing and instruction formats.

 Large 16-bit register file eliminates single accumulator bottleneck High-bandwidth 16-bit data and address bus with no paging RISC architecture with 27 instructions and 7 addressing modes Single-cycle register operations with full-access Direct memory-memory transfer designed for modern programming Compact silicon 30% smaller than an 8051 saves power and cost

Complex Instruction Set Computer (CISC)

Memory in those days was expensive
bigger program->more storage->more money

Hence needed to reduce the number of instructions per program Number of instructions are reduced by having multiple operations within a single instruction

Reduced Instruction Set Computer (RISC)

Provide minimal set of instructions that could carry out all essential operations

The difference between CISC and RISC becomes evident through the basic computer performance equation: RISC systems shorten execution time by reducing the clock cycles per instruction (i.e. simple instructions take less time to interpret) CISC systems shorten execution time by reducing the number of instructions per program

RISC Simple instructions, few in number Fixed length instructions Complexity in compiler Only LOAD/STORE instructions access memory Few addressing modes

CISC Many complex instructions Variable length instructions Complexity in microcode Many instructions can access memory Many addressing modes

Each instruction uses an even number of bytes (2, 4, or 6) PC is word aligned (the LSB is 0)

MOV #LABEL,PC ; Branch to address LABEL MOV LABEL,PC ; Branch to address contained in LABEL MOV @R14,PC ; Branch indirect, indirect R14

 Stack pointer for return addresses of subroutines and interrupts SP is word aligned (the LSB is 0) Pre-decrement/post-increment scheme
PUSH #0123h ; Put 0123h onto TOS POP R8 ; R8 = 0123h

C: SR(0) Z: SR(1) N: SR(2) GIE (Global interrupt enable): SR(3) CPUOff: SR(4) OSCOff: SR(5) SCG1, SCG0: SR(7), SR(6) V: SR(8)

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As source register addressing mode in the instruction word

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For example, consider an "increment" instruction "INC R2"; many architectures have a special instruction to implement this. Others will implement it as "add #1, R2", where you'll have to have "1" in a memory location somewhere. On the MSP430, the constant "1" comes from the constant generator, so it doesn't take any extra memory, nor a special instruction.

CPE/EE 42/521 Microcomputers

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Register Mode

Indexed Mode

Symbolic Mode

Absolute Mode

This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address. These are addressed with absolute mode to ensure software transportability (for example, positionindependent code).

Indirect Register Mode

Indirect Autoincrement Mode

Immediate Mode

One address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory.

Flash ROM:

The start address of Flash/ROM depends on the amount of Flash/ROM present and varies by device. The end address for Flash/ROM is 0FFFFh. Flash can be used for both code and data. The interrupt vector table is mapped into the the upper 16 words of Flash/ROM address space, with the highest priority interrupt vector at the highest Flash/ROM word address (0FFFEh).

RAM:
RAM starts at 0200h. The end address of RAM depends on the amount of RAM present and varies by device. RAM can be used for both code and data.

Peripheral Modules 16 bits:

The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0.

Peripheral Modules 8 bits:

The address space from 010h to 0FFh is reserved for 8-bit peripheral modules. These modules should be accessed with byte nstructions. Read access of byte modules using word instructions results in unpredictable data in the high byte. If word data is written to a byte module only the low byte is written into the peripheral register, ignoring the high byte.

Special Function Registers (SFRs):

Some peripheral functions are configured in the SFRs. The SFRs are located in the lower 16 bytes of the address space, and are organized by byte. SFRs must be accessed using byte instructions only. See the devicespecific data sheets for applicable SFR bits.

Bytes are located at even or odd addresses. Words are only located at even addresses as shown. When using word instructions, only even addresses may be used. The low byte of a word is always an even address. The high byte is at the next odd address.

For example, if a data word is located at address xxx4h, then the low byte of that data word is located at address xxx4h, and the high byte of that word is located at address xxx5h.

If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

Features:

Four software-selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Selectable clock source Can be stopped to conserve power Clock fail-safe feature in WDT+