(Metal Oxide Semiconductor Field Effect

Transistor)

Presented By- Mohammad Rameez
Transistors
These are three terminal
devices, where the current or
voltage at one terminal, the
input terminal, controls the
flow of current between the
two remaining terminals.
Current Controlled vs Voltage Controlled Devices





Current Controlled vs Voltage Controlled Devices





Transistors
Can be classified as:
FET Field Effect Transistor;
Majority carrier device;
Unipolar device;
BJT Bipolar Junction Transistor;
Minority carrier device;
Bipolar device.
FETs
Two primary types:
MOSFET, Metal-Oxide-Semiconductor FET. Also
known as IGFET Insulated Gate FET;
JFET, Junction FET.
MOS transistors can be:
n-Channel;
Enhancement mode;
Depletion mode;
p-Channel;
Enhancement mode;
Depletion mode;
Overview


Types of FET
p-channel
JFET
n-channel
MOSFET
p-channel
n-channel
enhancement
depletion
enhancement
depletion
The MOS Transistor
Polysilicon
Aluminum
Metal Oxide Semiconductor FET: MOSFET
MOSFET also known as insulated-gate field-effect
transistors (IGFET) is preferred in power electronics due to
its ability of fast switching especially in timing circuits.
MOSFET has a "Metal Oxide" gate (silicon dioxide- usually
a glass, with insulating properties), which is electrically
insulated from the semiconductors N-channel or P-channel.
This isolation of the controlling gate makes the input
resistance of the MOSFET extremely high in the Mega-
ohms region (infinite), thus switching loss at input side can
controlled and stabilized.
As the gate terminal is isolated from the main current
carrying channel "NO current flows into the gate, so
MOSFET acts as a voltage controlled resistor (like JFET).
MOSFET is specially used in digital complementary metal
oxide semiconductor (CMOS) logics.

Metal Oxide Semiconductor FET: MOSFET
MOS gate Structure
First electrode - Gate :
Consists of low-resistivity
material such as highly-doped
polycrystalline silicon,
aluminum or tungsten

Second electrode - Substrate
or Body: n- or p-type
semiconductor

Dielectric - Silicon dioxide:
stable high-quality electrical
insulator between gate and
substrate.
MOS Capacitor Picture
MOS Electrostatics
Condition is called flatband --- the voltage when this occurs
is called flatband
This state is the baseline operating case --- a capacitive
divider has one free parameter
V
fb

MOS Electrostatics
Depletion Condition --- gate charge is terminated by charged
ions in the depletion region
Part of this region is often referred to as weak-inversion
MOS Electrostatics
Inversion --- further gate charge is terminated by carriers
at the silicon--silicon-dioxide interface
MOSFET FAMILY-TREE
MOSFET Circuit Symbols
(g) and (i) are the most
commonly used
symbols in VLSI logic
design.
MOS devices are
symmetric.
In NMOS, n
+
region at
higher voltage is the
drain.
In PMOS p
+
region at
lower voltage is the
drain
Output current (Drain current-ID) in a MOSFET is controlled by the gate-
source voltage V
GS
.
V
GS
controls the thickness of the channel

MOSFET Operation
n-Channel MOSFET With VGS < VT
n-Channel MOSFET With VGS > VT , small VDS
n-Channel MOSFET With VGS > VT , large VDS
MOSFET Regions of Operation
MOSFET Regions of Operation
I-V Characteristics of MOSFET
The drain current versus the drain-to-source voltag
for an enhancement-type NMOS transistor
operated.
MOSFET ID-VG, ID-VDS
OFF
ON
ID
VGS =VDD
VGS1
VGS2
VGS3
ID
VGS
VDS = Kostant
I
D
D
S
G
VDS
VGS
Analog
Digital Logic
D or S D or S
Gate
V
TN

V
DD
= 1
MOSFET Modes of Operations
Two basic types of MOSFETs:
1. Depletion MOSFETs (D-MOSFETs) : can be operated in either
the depletion mode or the enhancement mode (Negative VGS).
2. Enhancement MOSFETs (E-MOSFETs) : can be operated only
in the enhancement mode (Positive VGS) .
E-MOSFET: Zero bias D-MOSFET: Zero bias
DEPLETION TYPE MOSFET
A CONDUCTING CHANNEL
ALREADY EXISTS
DEVICE IS NORMALLY ON WITH
NO BIAS APPLIED TO GATE.
THE DEVICE CAN OPERATED
EITHER IN THE ENHANCEMENT
MODE BY APPLYING A POSITIVE
GATE VOLTAGE OR IN A
DEPLETION MODE WITH A
NEGATIVE BIAS ON THE GATE





Depletion Mode MOSFET Construction
The Drain (D) and Source (S) leads connect to the to n-doped regions
These N-doped regions are connected via an n-channel
This n-channel is connected to the Gate (G) via a thin insulating layer of SiO
2
The n-doped material lies on a p-doped substrate that may have an additional
terminal connection called SS





Basic Operation
A D-MOSFET may be biased to operate in two modes:
the Depletion mode or the Enhancement mode
D-MOSFET Depletion Mode Operation





The transfer characteristics are similar to the JFET
In Depletion Mode operation:
When VGS = 0V, ID = IDSS
When VGS

< 0V, ID < IDSS
When VGS > 0V, ID > IDSS
The formula used to plot the Transfer Curve, is:
| |
|
\ .
2
GS
D DSS
P
V
I = I 1 -
V
D-MOSFET Enhancement Mode Operation





Enhancement Mode operation
In this mode, the transistor operates with V
GS
> 0V, and I
D
increases above I
DSS

Shockleys equation, the formula used to plot the Transfer Curve, still applies but
VGS is positive:

| |
|
\ .
2
GS
D DSS
P
V
I = I 1 -
V





p-Channel Depletion Mode MOSFET
The p-channel Depletion mode MOSFET is similar to the n-channel except that
the voltage polarities and current directions are reversed
ENHANCEMENT TYPE MOSFET
THE ENHANCEMENT TYPE
MOSFET IS NORMALLY OFF
NO CURRENT FLOWS
BETWEEN THE SOURCE AND
THE DRAIN FOR VG=0
THE CHANNEL IS INDUCED BY
APPLYING A VOLTAGE OF
APPROPRIATE POLARITY TO
THE GATE.





Enhancement Mode MOSFET Construction
The Drain (D) and Source (S) connect to the to n-doped regions
These n-doped regions are not connected via an n-channel without an external
voltage
The Gate (G) connects to the p-doped substrate via a thin insulating layer of SiO
2
The n-doped material lies on a p-doped substrate that may have an additional
terminal connection called SS





E-MOSFET Symbols





Basic Operation
The Enhancement mode MOSFET only operates in the enhancement mode.













VGS is always positive
IDSS = 0 when VGS < VT
As VGS increases above VT, ID increases
If VGS is kept constant and VDS is increased, then ID saturates (IDSS)
The saturation level, VDSsat is reached.





Transfer Curve
To determine ID given VGS:
where VT = threshold voltage or voltage at which the MOSFET turns on.
k = constant found in the specification sheet
The PSpice determination of k is based on the geometry of the device:

2
D GS T I = k (V - V )
D(on)
2
GS(ON) T
I
k =
(V - V )
| || |
| |
\ .\ .
N OX
W KP
k = where KP = C
L 2





p-Channel Enhancement Mode MOSFETs
The p-channel Enhancement mode MOSFET is similar to the n-channel except
that the voltage polarities and current directions are reversed.
TYPES OF MOSFET





Summary Table
JFET D-MOSFET E-MOSFET
Non-ideal MOS
So far, we have discussed MOS characteristics
making some assumptions - calling it ideal.
Assumed that the u
M
= u
S
, i.e. the bands are flat when
no voltage is applied.
Assumed that the oxide and oxide-semiconductor
interface are free of charges.
These assumptions do not hold good in an actual
MOS device, and we have to consider the
deviations from the ideal case. For the purpose of
discussions, we call these as real.
Metal-semiconductor work function difference - ideal
When u
M
= u
S
, the Fermi level is aligned before we make the device. So, when the
MOS structure is made, the band remains flat when the applied gate voltage is zero.
Assumption u
MS
= u
M
u
S
= 0
E
FS

E
FM

O M S
u
M
u
S
_
Flat band condition
Metal-semiconductor work function difference - real
u
M
depends on the metal.
Example: u
M
(Al) ~ 4 eV, u
M
(Au) ~ 5.1 eV
u
S
depends on the semiconductor doping.
u
S
= _ + (E
C
E
F
)
FB

So, u
MS
= u
M
u
S
= 0
in a real device.
So, actual band alignment before
making the MOS-C structure looks as
shown for Al-Si (p)
E
FS

E
FM

O M S
u
M
u
S
_
M = Al
Interface and oxide charges
For the ideal device, we have assumed that the oxide and the
interface is devoid of any excess charges. This is not true in practice.
Si
+ + + + + + + + + + + + + + + + ++
+ +
+
Na
+

Na
+

Q
it

Q
of

Q
of

Q
metal
Assume that all these charges
are situated close to the interface
on the oxide side (even though
they arent) and their concentration
is ~ Q
i
Coulombs/cm
2
.

Q
i
= net interface charges in C/cm
2
Effect of interface charges, Q
i

(C/cm
2
)
The interface charge Q
i
in the oxide (assumed positive) will induce
some negative charges (Q
i
/cm
2
) in the semiconductor. The effect
is as though we have applied a positive gate voltage to the gate, and
the negative charges in the semiconductor causes band bending. To
get flat-band condition, we have to apply a negative voltage to the gate.
Voltage to be applied to the
gate to get flat-band condition
ox
ox
ox
ox
i
where
x
C
C
Q c
= =
Q
i
is usually positive (but can be both positive or negative in general).
Effects of work function difference and interface charges
If we consider the effects of work function difference and the
interface charges, the silicon band diagram may not be flat
even when no voltage is applied to the gate. Hence, a correction
has to be applied to the threshold voltage calculations carried out
earlier assuming ideal MOS conditions.
|
|
.
|

\
|
+ u =
ox
i
ms FB
1
C
Q
q
V
voltage to be applied to the gate to
get flat band condition.
=
'
T FB T
V V V + =
where V
T

is the threshold voltage assuming

ideal conditions
Channel length modulation
The reverse biased p-n junction
between the drain and the body
forms a depletion region with
length L that increases with V
db
.
The depletion region effectively
shorten the channel length to:
L
eff
= L L

Assuming the source voltage is
close to the body votage V
db
~
V
sb
. Hence, increasing V
ds

decrease the effective channel
length.

Shorter channel length results in
higher current


Nonideal Effects..channel length modulation
D
I
D D
I
L L
L
I |
.
|

\
|
A
=
'
'
D
I
Where is the actual drain current and is
the ideal drain current. Since is a function of
, is now also a function of even though
the transistor is biased in the saturation region.
D D
I
L L
L
I
|
.
|

\
|
A
=
'
L A
'
D
I
DS
V
DS
V
Body Effect
The potential difference between source and body V
sb
affects (increases) the
threshold voltage
Threshold voltage depends on:
V
sb
Process
Doping
Temperature

Sub-Threshold Conduction
Ideally at V
GS
< V
T
, I
D
= 0.
The MOS device is partially conducting for
gate voltages below the threshold voltage.
This is termed sub-threshold or weak inversion
conduction.
In most digital applications the presence of
sub-threshold current is undesirable.

A Sub-threshold digital circuit manages to
satisfy the ultra-low power requirement.
Subthreshold Conduction
Below cut off current does not abruptly become zero


Falls off exponentially

Useful in low power CMOS VLSI design
) 1 (
0
T
ds
T
t gs
v
V
nv
V V
ds ds
e e I I

=
8 . 1 2
0
e v I
T ds
| =
Nonideal Effects..subthreshold
( )
(

|
.
|

\
|

|
.
|

\
|

kT
eV
kT
eV
sub I
DS GS
D
exp 1 exp
Junction Leakage
Conduction even when
transistor is in cut-off
Substrate to diffusion
junctions are reverse
biased
However reverse
biased diodes do
conduct leakage
current
) 1 ( =
T
D
v
V
S D
e I I
Junction Leakage

The p-n junctions between diffusion and the substrate or
well for diodes.
The well-to-substrate is another diode
Substrate and well are tied to GND and VDD to ensure
these diodes remain reverse biased
But, reverse biased diodes still conduct a small amount of
current that depends on:
Doping levels
Area and perimeter of the diffusion region
The diode voltage
Leakge Current
When the junction bias voltage is significantly more than the
thermal voltage (~26mV @room temperature) the leakage
current is Is
Junction leakage limits storage time in on-chip memory
elements
Requires refreshing dynamic nodes
Tunneling current
Current technology nodes
Tunneling current as significant as junction leakage and sub-threshold
conduction
Technique to reduce tunneling current
Use high-K materials in the gate oxide layer
High dielectric constant makes high gate capacitance
Reduces the need to reduce the oxide thickness
Silicon Nitride is a good candidate for such materials
Tunneling effects
Ideal MOS model
High input impedence
No static current flow through the gate terminal
Quantum mechanical effect
Carriers tunnel through insulating barriers with finite probability
Insulating barrier has to be very thin for appreciable current
Current gate oxide thickness ~10-15
Single atomic layer of silicon ~3
Temperature Effects
Effect on Mobility
Carrier mobility
decreases with
temperature
k is a parameter usually
in the range 1.2-2.0

k
r
r
T
T
T T

|
|
.
|

\
|
= ) ( ) (
Temperature effects
Threshold voltage
Vt decreases linearly with increase in temperature


Junction leakage also increases with increase in temperature
All combined results in decrease of On current and increase of
Off current

The Threshold Voltage
Any gate-to-source voltage less than V
T0
is not
sufficient to establish an inversion layer.
The MOSFET conducts no current between its
source and drain terminals unless V
GS
is
greater than V
T0
.
Increasing the gate-to-source voltage above
and beyond V
T0
will not affect the surface
potential and the depletion region depth.
There are 4 physical properties that affect the
threshold voltage namely (i) the work function
difference between the gate and the channel,
(ii) the gate voltage component to change the
surface potential, (iii) the gate voltage
component to offset the depletion region
charge and (iv) the voltage component to
offset the fixed charges in the gate oxide and
in the silicon oxide interface.
qV
T0
E
c
E
i
E
Fp
E
v
2u
F
u
F
u
F
Metal (Al)

Oxide (SiO
2
)

P-type Semiconductor (Si)

Velocity saturation and mobility degradation
At strong lateral fields
resulting from high V
ds
,
drift velocity rolls off due
to carrier scattering and
eventually saturates

Strong vertical fields
resulting from large V
gs

cause the carriers to
scatter against the
surface and also reduce
the carrier mobility. This
effect is called mobility
degradation
Nonideal Effects..velocity saturation
2 / 1
2
1
(
(

|
|
.
|

\
|
+
=
sat
eff
eff
v
E

Nonideal Effects..mobility variation

3 / 1
0
0

|
|
.
|

\
|
=
E
E
eff
eff

0

Where and are constants determined from

experimental results.
0
E
Short Channel Effect

In small transistors, source/drain depletion regions extend into the channel
Impacts the amount of charge required to invert the channel
And thus makes V
t
a function of channel length

Short channel effect: V
t
increases with L
Some processes exhibit a reverse short channel effect in which V
t
decreases with L
Hot-Carrier Effects
Channel electron
traveling through
high electric field
near the drain end
can:
become highly energetic, i.e. hot
cause impact ionization and generate e
-
and holes
+holes go into the substrate creating substrate current, I
sub
.
Some channel e
-
have enough energy to overcome the
SiO
2
-Si energy barrier generating gate current, I
g
.
The maximum e-field, E
m
near the drain has the greatest
control of hot carrier effects.
Gate
I
g

n+ Drain n+ Source
I
sub

m
hole
hot e

l
l l l l l l
Hot electrons
The channel Hot Electrons effect is caused by electrons
flowing in the channel for large V
DS

e- arriving at the Si-SiO
2
interface with enough kinetic
energy to surmount the surface potential barrier are
injected into the oxide

This may degrade permanently the C-V characteristics of a
MOSFETs
Hot Electron Effects
Effect:
hot electron injection.
Outcome:
substrate current.
Trends:
power supplies are decreasing
electric fields are increasing.
Non-Ideal I-V Effects (Summary)
Miniaturization has led to modern devices
having nonideal characteristics
The saturation current increases less than
quadratically with increasing V
GS
.
Velocity saturation and mobility
degradation are two of the effects that
cause the non quadratic current increase
with V
GS
.
When carrier velocity ceases to increase
linearly with field strength we have
velocity saturation.
The current I
DS
is lower than expected at
high V
DS
.
There are several sources of leakage that
result in current flow when the transistor is
expected to be OFF.
The source and drain diffusion regions are
form reverse biased diodes which
experience junction leakage into the
substrate or well.
The current into the gate I
G
is ideal zero,
however as gate oxide thickness is
reduced electrons tunnel through the gate,
causing some current.
APPLICATIONS OF MOSFET
CAN BE USED AS A SWITCH
AS AN AMPILFIER
DeepGATE power MOSFETs with increased voltage ratings, delivering
enhanced on-state and switching performance for DC-DC applications
For automotive applications
For space applications