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Execution Control
Execution control refers to the rules or mechanisms used in a processor for determining the next instruction to execute. several features of execution control hardware looping, interrupt handling, stacks, and relative branch support.
Hardware Looping
DSP algorithms frequently involve the repetitive execution of a small number of instructions- socalled inner loops or kernels. problems associated with traditional approaches to repeated instruction execution:
a natural approach to looping uses a branch instruction to jump back to the start of the loop. most loops execute a fixed number of times, the processor must usually use a register to maintain the loop index, that is, the count of the number of times the processor has been through the loop.
DSP processors have evolved to avoid these problems via hardware looping, also known as zero-overhead looping. Hardware loops are special hardware control constructs that repeat either a single instruction or a group of instructions some number of times. The key difference between hardware loops and software loops is that hardware loops lose no time incrementing or decrementing counters, checking to see if the loop is finished, or branching back to the top of the loop. This can result in considerable savings.
The software loop takes roughly three times as long to execute, assuming that all instructions execute in one instruction cycle. In fact, branch instructions usually take several cycles to execute, so the hardware looping advantage is usually even larger.
Nesting Depth
A nested loop is one loop placed within another. The most common approaches to hardware loop nesting are:
Directly nestable Partially nestable Software nestable Nonnestable
Interrupts
An external event that causes the processor to stop executing its current program and branch to a special block of code called an interrupt service routine. All DSP processors support interrupts and most use interrupts as their primary means of communicating with peripherals.
Interrupt Sources
On-chip peripherals : generate interrupts when certain conditions are met External interrupt lines : asserted by external circuitry to interrupt the processor Software interrupts : generated either under software control or due to a software-initiated operation
Interrupt Vectors
All processors associate a different memory address with each interrupt. These locations are called interrupt vectors. Processors that provide different locations for each interrupt are said to support vectored interrupts. Typical interrupt vectors are one or two words long and are located in low memory. The interrupt vector usually contains a branch or subroutine call instruction that causes the processor to begin execution of the interrupt service routine located elsewhere in memory. On some processors, interrupt vector locations are spaced apart by several words.
Interrupt Enables
All processors provide mechanisms to globally disable interrupts. On some processors, this may be via special interrupt enable and interrupt disable instructions, while on others it may involve writing to a special control register. Most processors also provide individual interrupt enables for each interrupt source. This allows the processor to selectively decide which interrupts are allowed at any given time.
When a processor allows a higher-priority interrupt to interrupt a lower priority interrupt that is already executing, we call this automatically nestable interrupts.
Interrupt Latency
The amount of time between an interrupt occurring and the processor doing something in response to it. Formal definition: The minimum time from the assertion of an external interrupt line to the execution of the first word of the interrupt vector that can be guaranteed under certain assumptions.
Interrupt Latency
The details of and assumptions used in this definition are as follows:
Most processors sample the status of external interrupt lines every instruction cycle. For an interrupt to be recognized as occurring in a given instruction cycle, the interrupt line must be asserted some amount of time prior to the start of the instruction cycle; this time is referred to as the set-up time. we assume that these setup time requirements are missed. This lengthens interrupt latency by one instruction cycle.
Interrupt Latency
Depending on the processor synchronization can add from one to three instruction cycles to the processor's interrupt latency. we assume the processor is in an interruptible state, which typically means that it is executing the shortest interruptible instruction possible. we assume the processor is in an interruptible state, which typically means that it is executing the shortest interruptible instruction possible.
Stacks
Processor stack support is closely tied to execution control. For example, subroutine calls typically place their return address on the stack, while interrupts typically use the stack to save both return address and status information. DSP processors typically provide one of three kinds of stack support:
Shadow registers: Shadow registers are dedicated backup registers that hold the contents of key processor registers during interrupt processing. Hardware stack: A hardware stack holds selected registers during interrupt processing or subroutine calls. Software stack: A software stack is a conventional stack using the processor's main memory to store values during interrupt processing or subroutine calls.
Pipelining
Pipelining
A technique for increasing the performance of a processor by breaking a sequence of operations into smaller pieces and executing these pieces in parallel when possible, thereby decreasing the overall time required to complete the set of operations. Unfortunately, in the process of improving performance, pipelining frequently complicates programming.
Assuming that each of the four stages above takes 20 ns to execute, and that they must be done sequentially
A pipelined implementation of this processor starts a new instruction fetch immediately after the previous instruction has been fetched . Similarly, it begins decoding each instruction as soon as the previous instruction is finished decoding. In essence, it overlaps the various stages of execution. As a result, the execution stages now work in parallel.
Pipeline Depth
Although most DSP processors are pipelined, the depth (number of stages) of the pipeline may vary from one processor to another. In general, a deeper pipeline allows the processor to execute faster but makes the processor harder to program. Most processors use three stages (instruction fetch, decode, and execute) or four stages (instruction fetch, decode, operand fetch, and execute). In three-stage pipelines the operand fetch is typically done in the latter part of the decode stage.
Interlocking
The execution sequence shown in Figure 9-2 is referred to as a perfect overlap, because the pipeline phases mesh together perfectly and provide 100 percent utilization of the processor's execution stages. In reality, processors may not perform as well as we have shown in our hypothetical example. The most common reason for this is resource contention.
Interlocking
Interlocking
One solution to this problem is interlocking. An interlocking pipeline delays the progression of the latter of the conflicting instructions through the pipeline
Interlocking
Branching Effects
Branching effects occur whenever there is a change in program flow, and not just for branch instructions. For example, subroutine call instructions, subroutine return instructions, and return from interrupt instructions are all candidates for the pipeline effects described above. Processors offering delayed branches frequently also offer delayed returns.
Branching Effects
Branching Effects
Interrupt Effects
Interrupts typically involve a change in a program's flow of control to branch to the interrupt service routine. The pipeline often increases the processor's interrupt response time, much as it slows down branch execution. When an interrupt occurs, almost all processors allow instructions at the decode stage or further in the pipeline to finish executing, because these instructions may be partially executed. What occurs past this point varies from processor to processor. We discuss several examples below:
Interrupt Effects
Interrupt Effects
Interrupt Effects