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Dr.K.Krishnaveni Professor and Head Dept. of EEE ,CBIT
3/5/2013 EEE Dept. CBIT, Hyderabad
OUTLINE
Introduction Various types of multi level Inverters
--Diode clamped --Capacitor clamped --Cascaded
Switching logic in multilevel inverters Comparison Single phase H-bridge(special case) Applications Conclusion
3/5/2013 EEE Dept. CBIT, Hyderabad
Introduction
Wave forms of practical inverters are non-sinusoidal & contain certain number of harmonics.
For low and medium power applications square wave or quasi square wave voltage may be acceptable.
But for high power applications, sinusoidal wave forms with low distortion are required. Harmonic contents present in the output of a dc-ac inverter can be eliminated by employing a filtering circuit or by employing PWM technique.
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Use of filters has the disadvantage of large size and cost, PWM technique reduces the filter requirement to minimum or zero depending on the type of application. Traditional two-level PWM Inverter have some drawbacks ,namely 1.More switching losses. 2.Intro.. of large amount of higher order harmonics. 3.large dv/dt rating. 4.Common mode voltages. 5.Problem of voltage sharing series connected devices. 6.Requirement of switches with very low turn-on and turn-off times.
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To overcome the mentioned problems Multi-level Inverters can be employed. In addition to the above they offer the advantage of less switching stress on the device for high voltage, high power applications with reduced harmonic content at low switching frequencies. This seminar presents the basic description of 2-level,3-level and 5-level inverters (and also presents the methodology for switching loss calculations). Modulation technique for 2,3,5 level Inverters & finally comparison will be shown for the topologies on the basis of switching losses &THD at different switching frequencies.
3/5/2013 EEE Dept. CBIT, Hyderabad
One phase leg of an inverter with (a) two levels, (b) three levels, and (c) n levels .
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Output voltage profile of (a) 2-level, (b) 3-level, and (c) 5-level inverter.
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The switching logic to obtain the output voltage for a 120 degrees mode of operation is shown in below table
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This topology can be used at very high switching frequencies to obtain low THD by using PWM technique.
Disadvantages in two-Level:
Power devices are to be connected in series-parallel to achieve a large power capability, but they suffer from static and dynamic voltage sharing problems in series & parallel connection of power devices. High rate of change of voltage due to synchronous commutation of series devices. In addition to above, high switching frequencies and harmonic contents in inverter output voltage.
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11
To produce an m-level output phase voltage, (m-1) switches are required for each half phase leg, a total of (m-1) dc link capacitors for energy storage and(m-1)*(m-2) clamping diodes for each phase leg
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Three-phase
diode clamped three-level inverter (neutral point clamped) topology is shown in below figure
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Three-phase
diode clamped three-level inverter (neutral point clamped) topology is shown in below figure
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The circuit consists of two dc link capacitors, 12 power switches and six clamping diodes. The middle point of the dc bus capacitor is known as neutral point n. The main feature of this topology is clamping diodes that clamp the switch voltage to half of the dc bus voltage, reducing the voltage stress of the switching device. The output voltage has three different states: +, 0 and and the corresponding output phase voltages are +Vdc/2, 0 and -Vdc/2.
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Switching states to synthesize the output voltages for phase A are defined in below table
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Five-Level DCMLI
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Five-Level DCMLI
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Five-Level DCMLI
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It consists of 24 power switches and 36 clamping diodes. The DC bus has four capacitors for a DC bus voltage Vdc. The voltage across each capacitor is Vdc/4.
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Switching losses can be calculated from the turn-on and turn-off characteristics of the devices. Instantaneous voltage and current during turn on time tc(on) are V(t)=Vdc-(Vdc-Von)*(t/tc(on)); 0<ttc(on) (1) i(t)=Idc*(t/tc(on)); 0<ttc(on) (2)
(3)
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Ec,on=(Vdc*Idc*tc(on))/2-(Vdc-Von)*Idc*tc(on)/3 =(Vdc*Idcton)/6-(Von*Idc*tc(on))/3
(4)
and during turn-off transition, of t c(off), the current falls from Idc to zero and the Von rises linearly to Vdc. The instantaneous voltage and current during this period are V(t)=Von+(Vdc-Von)/tc(off) i(t)=Idc-Idc/tc(off)
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(5) (6)
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(8)
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With a switching frequency of Fs, the average switching loss in the switch during each transition of turn on and turn off can be found as Pc,on=(Vdc*Idc*tc(on)/Ts)/6+(Von*Idc*tc(on)/Ts)/3 (9) Pc,off=(Vdc*Idc*tc(off)/Ts)/6-(Von*Idc*tc(off)/Ts)/3 (10)
(11)
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Eqn. (11) shows that the switching power loss in a semiconductor switch varies linearly with the switching frequency and switching times.
Therefore, with the devices having short switching times, it is possible to operate them at a higher switching frequency thus avoiding excessive switching power losses in the device
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Modulation technique
The modulation or controlled techniques are classified below
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SPWM technique is considered for the study in this project. In SPWM technique a triangular carrier wave is compared with the sinusoidal reference wave at fundamental output frequency. The below figure shows the generation of switching pulses for power device S1 of the two level inverter
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The below figure shows the switching pulses for power devices Sa1 and Sa2 of three level inverter
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The below figure shows the switching pulses for power devices Sa1,Sa2,Sa3 and Sa4 of five level inverter
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Scope Subsystem
A B
Vabc Iabc a b c
Display
s ignal THD
Total Harmonic Distorsion Vin voltages ] From Total Harmonic Distorsion 1 Iin Von From 8
s ignal THD s ignal THD
From 3 Product
-K Gain Display 1
InMean
Mean Value
Scope 3
[s211 ] From 7
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-KGain Display 1
InMean
Von From 8
Mean Value
Scope 3
s211 From 7
voltages ] From
signal THD
[voltages ] Goto
signal THD
Scope
A Vabc Iabc B a b C c
Three -Phase V-I Measurement 3
Subsystem
c
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Scope [voltages ]
C
Subsystem
b
A Vabc Iabc B a b C c
Three -Phase V-I Measurement 3
Display
A signal THD
voltages ] From
signal THD
. Vin
-K Gain Display 1
InMean
Add
Mean Value
Scope 3
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Frequency spectrum
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Frequency spectrum
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Harmonic order
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Variation of switching losses and THD with carrier frequency for the three-level inverter.
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Variation of switching losses and THD with carrier frequency for a five-level inverter.
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Variation of switching losses for two-level, threelevel and five-level inverters with carrier frequency.
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Variation of percentage THD for two-level, threelevel and five-level inverter with carrier frequency.
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References
1.F. Z. Peng & J. S. 1. Lai, Multilevel Converters - A new breed of power converters, IEEE Transaction on Industry Applications, Vol. 32, No. 3, May/June, 1996, pp. 509-517. 2. Jose Rodriguez, J. S. Lai & F. Z. Peng, Multilevel Inverters: A Survey of Topologies, Controls, and Applications, IEEE Transaction on Industrial Electronics, Vol. 49, No. 4, Aug 2002, pp. 724-738. 3. Mohan Ned, Undeland T.M. & Robbins W.P., Power Electronics: Converters, Applications and Design, John Wiley and Sons, Second Edition, 2001. 4. G. Bhuvaneswari & Nagaraju, Multilevel Inverters A Comparative Study, IETE Journal of Research, Vol. 51, No.2, Mar-Apr 2005, pp.
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