Study & Verilog Implementation of PN Sequence generator using Fibonacci and Galois method

Harshita Kumar

PN Sequences

PN generator produces periodic sequence that appears to be random Generated by an algorithm using initial seed Sequence isnt statistically random but will pass many test of randomness Sequences referred to as pseudorandom numbers or pseudo-noise sequences Unless algorithm and seed are known, the sequence is impractical to predict

PN Sequences

A deterministically generated sequence that nearly satisfies these properties is referred to as a Pseudorandom Sequence (PN)

Random White Gaussian Noise

Same Power Spectral Density for all the frequencies The autocorrelation function of WGN is given by the inverse Fourier transform of the noise power spectral density

The autocorrelation function is zero for t 0

Random White Gaussian Noise

The amplitude of integrated (bandlimited) WGN has a Gaussian probability density distribution as given below

Random White Gaussian Noise in Time Domain

Random White Gaussian Noise Probability Density Distribution

Random White Gaussian Noise Autocorrelation Function

Random White Gaussian Noise Power Spectral Density

Pseudo Random Noise

Acts as a noise-like (but deterministic) carrier used for bandwidth spreading of the signal energy. The PN code sequence is a pseudo noise or pseudo-random sequence of 1s and 0s but not a real random sequence. Random signals cannot be predicted. Autocorrelation properties of a PN sequence are similar to that of white noise.

Pseudo Random

Not random, but looks randomly for the user who doesnt know the code. Deterministic, periodic signal that is known to both the transmitter and the receiver. Statistical properties of sampled white noise.

Length of PN Sequence

Short code: The same PN sequence for each data symbol Long code: The PN sequence period is much longer than the data symbol, so that a different chip pattern is associated with each symbol

Properties of PN Sequences

Balance Property
In each period of the sequence the number of binary ones differs from the number of binary zeros by at most one digit
pn = 1 1 1 0 1 0 0

Properties of PN Sequences

Run length distribution

A run is a sequence of a single type of binary digits. Among the runs of 1s and 0s in each period it is desirable that about one-half the runs of each type are of length 1, about one-fourth are of length 2, one-eighth are of length 3, and so on.

Properties of PN Sequences

Autocorrelation
The origin of the name pseudo-noise is that the digital signal has an autocorrelation function which is very similar to that of a white noise signal: impulse like The autocorrelation function for the periodic sequence pn is defined as the number of agreements less the number of disagreements in a term by term comparison of one full period of the sequence with a cyclic shift (position t) of the sequence itself:

Properties of PN Sequences

Frequency Spectrum
Due to the periodic nature of the PN sequence the frequency spectrum has spectral lines which become closer to each other with increasing sequence length NC. Each line is further smeared by data scrambling, which spreads each spectral line and further fills in between the lines to make the spectrum more nearly continuous. The DC component is determined by the zero-one balance of the PN-sequence.

Properties of PN Sequences

Cross-correlation
It describes the interference between codes pni and pnj:

It is a measure of agreement between two different codes. When the cross-correlation is zero for all t, the codes are called orthogonal.

Common classes of PN generators

Linear congruential generators Lagged Fibonacci generators Linear feedback shift registers Generalized feedback shift registers Recent instances of pseudorandom algorithms include Blum Blum Shub, Fortuna, and the Mersenne twister

PN Generators Implemented

Fibonacci Galois
These are based on defining polynomial P(x). The circuit will be traced through all possible states. The output of the circuit implementation is the exact replica of the states observed from mathematical implementation. It can also be observed that the output from one implementation is a delayed version of that from the other in Fibonacci and Galois pair.

PN Generators Implemented

Fibonacci Galois
These are based on defining polynomial P(x). The circuit will be traced through all possible states. The output of the circuit implementation is the exact replica of the states observed from mathematical implementation. It can also be observed that the output from one implementation is a delayed version of that from the other in Fibonacci and Galois pair.

Transforming binary messages to polynomials

Manipulation of long binary values requires some special techniques. Binary messages of the form 1s and 0s can be transformed into polynomials using binary-poly mathematics. The polynomials notation lends itself to computation in hardware using only shift registers and exclusive-OR (XOR) gates.

Transforming binary messages to polynomials

Binary-Poly Mathematics
Binary values can be represented as polynomials with coefficients {0,1}. For example, 110011 can be written as 1 x5 + 1 x4 + 0 x3 + 0 x2 + 1 x1 + 1 x0 and simplified as: x5 + x4 + x + 1
Polynomials can be manipulated using the usual arithmetic rules, and these properties (closure, associative, commutative, etc) define a field. For example, 110011 x 10 = 1100110 can be written as: (x5 + x4 + x + 1) (x) = x6 + x5 + x2 + x

Transforming binary messages to polynomials

Binary-Poly Mathematics
Polynomials always use modulus 2 arithmetic. This is equivalent to the exclusive-OR operation. For example, 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0
The rules for subtraction follow from addition (if 1+1=0, then 0-1=1 !!), and are also equivalent to the exclusive-OR operation, as shown below. 0-0=0 0-1=1 1-0=1 1-1=0 If a polynomial has no factors other than 1 and itself, it is a prime polynomial.
In practice, we proceed by testing for only ODD factors and finally stop when the square root of the number is reached.

Polynomials and Linear Recursive Sequences

One of the practical applications of polynomials is in the definition and description of linear recursive sequence generators. These sequential circuits, based on shift registers and exclusive-OR (XOR) gates, find use in the generation of random numbers, with many applications in modern cryptography and digital communications. The sequential circuit is defined by the divisor, a polynomial P(x) which is reflected in the XOR gates in the circuit. Each coefficient in the polynomial describes a 'tap' connection to the shift registers.

Polynomials and Linear Recursive Sequences

In the above circuit, the taps are 101111 and the polynomial describing this circuit is: P(x) = x5 + x3 + x2 + x + 1

Conditions for Maximal Length Sequences

The polynomial P(x) must be prime.

If a polynomial P(x) of order N gives a maximum length sequence, the length will be L = 2N-1. On the other hand, there are some prime polynomials which do not work here. A second distinction is necessary.

The polynomial P(x) must be a primitive prime.

For a prime P(x) to give a maximum length sequence of length L, P(x) must be a factor of xL+1 (and of no other smaller L). Such a prime is called primitive.

Rules for circuit implementation

The order of the polynomial determines the number of the shift registers used in the circuit. In the previous slide P(x) is of the order of 5. So, 5 shift registers are required. This rule is same for Fibonacci as well as Galois implementation. The position of 1s in the binary equivalent value of the polynomial determines the XOR-tap positions. This rule differentiates between Galois and Fibonacci implementation.

Fibonacci Implementation

In this method, XOR-taps are always present in the feedback path. Consider the binary value [1011] of a polynomial, P(x). The Fibonacci implementation of this polynomial is

Sequence #1(Starting with 0):

States: 0, 0, forever....

Sequence#2 (Starting with 1):

States: 1, 4, 2, 5, 6, 7, 3, 1

Period = 7 (Maximum Length Sequence) Output = 1001011...

Galois Implementation

In this method, XOR-taps are always present in the feedforward path. Consider the binary value [1011] of a polynomial, P(x). The Fibonacci implementation of this polynomial is

Sequence #1(Starting with 0):

States: 0, 0, forever....

Sequence#2 (Starting with 1):

States: 1, 6, 3, 7, 5, 4, 2, 1

Period = 7 (Maximum Length Sequence) Output = 1011100...

State table

This circuit may be analyzed by considering what would happen when the shift register is clocked for each possible state of the circuit. In the state table below, the shift register is filled with each possible value and the contents after the next clock are computed. Results are shown in binary and in decimal. A sequence of states may be traced by following the states from any starting value. The LSB is shifted out to create a bitstream output sequence.

This State

000 001 010 011 100 101 110 111

0 1 2 3 4 5 6 7

Next State

000 110 001 111 010 100 011 101

0 6 1 7 2 4 3 5

Result

A maximum length sequence was found. For this polynomial of order 3, the maximum length sequence has a period of 23-1 states. This only happens when the characteristic polynomial is prime, as in this case. Use of a prime polynomial is a necessary but not sufficient condition for a maximum length sequence.

Clock Generator

Verilog code

`timescale 1ns / 1ps module clkgen(fetch, clk2, clk); output fetch, clk2, clk; reg fetch, clk2, clk; `define period 20.000

initial fork clk=0; clk2=1; fetch=1; forever #(`period/2) clk = ~clk; forever #(`period) clk2 = ~clk2; forever #(`period*2) fetch = ~fetch; join endmodule

Clock Generator

Waveform

D Flip Flop

Verilog code

Verilog code (contd..)

module dff ( din, clk, qout, qbarout, resetin, setin ); input din, clk, resetin, setin; output qout, qbarout; reg qout, qbarout; wire din, clk, resetin, setin; initial begin qout = 1'b0; qbarout = 1'b1; end always @(resetin, setin) begin if (resetin == 1'b1) begin qout = 1'b0; qbarout = 1'b1; end

else if (setin == 1'b1) begin qout = 1'b1; qbarout = 1'b0; end end always @(posedge clk) begin if ((resetin == 1'b0) && (setin == 1'b0)) begin qout = din; qbarout = ~din; end end endmodule

D Flip Flop Testbench

Verilog code
`timescale 1ns / 1ps
module dff_test ( din, clk, qout, qbarout, resetin, setin ); output din, clk, qout, qbarout, resetin, setin; reg din, resetin, setin; initial begin resetin = 0; setin = 0; din =1; #500 resetin = 1; #500 setin = 1; resetin = 0; din = 0; #500 setin = 0; #500 resetin = 0; setin = 1; $finish; end clkgen clkgen_inst (clk2, clk, clk1); dff dff_inst (din, clk, qout, qbarout, resetin, setin ); endmodule

PN Sequence

Verilog code

`timescale 1ns / 1ps module dff ( din, clk, qout, qbarout, resetin, setin ); input din, clk, resetin, setin; output qout, qbarout; reg qout, qbarout; wire din, clk, resetin, setin; initial begin qout = 1'b0; qbarout = 1'b1; end always @(resetin, setin) begin if (resetin == 1'b1) begin qout = 1'b0; qbarout = 1'b1; end

PN Sequence

Verilog code (contd..)

else if (setin == 1'b1) begin qout = 1'b1; qbarout = 1'b0; end end always @(posedge clk) begin if ((resetin == 1'b0) && (setin == 1'b0)) begin qout = din; qbarout = ~din; end end endmodule

PN Sequence

Verilog code (contd..)

`timescale 1ns / 1ps module xorgate (A, B, Z); input A, B; output Z; wire A, B; reg Z; always @(A, B) begin if (((A == 1'b1) && (B == 1'b0)) || ((A == 1'b0) && (B == 1'b1))) begin Z = 1'b1; end else if (((A == 1'b0) && (B == 1'b0)) || ((A == 1'b1) && (B == 1'b1))) begin Z = 1'b0; end end endmodule

PN Sequence

Verilog code (contd..)

`timescale 1ns / 1ps

module pns (resetin, clk, pnsout_FIB, pnsout_GAL); input resetin, clk; output pnsout_FIB, pnsout_GAL; reg pnsout_FIB, pnsout_GAL; wire resetin, clk; wire d1, d2, d2n, d3, d3n, d5, d5n, d6, d7, d7n; wire pnsoutn_FIB, pnsoutn_GAL; reg setin; wire pnsout_FIB_int, pnsout_GAL_int; initial begin setin = 1'b0; end

PN Sequence

Verilog code (contd..)

//Fibonacci implementation dff dff_inst1 (d1, clk, d2, d2n, resetin, setin ); dff dff_inst2 (d2, clk, d3, d3n, resetin, setin ); dff dff_inst3 (d3, clk, pnsout_FIB_int, pnsoutn_FIB, setin, resetin ); xorgate xorgate_inst4 (pnsout_FIB, d3, d1); always @(pnsout_FIB_int) begin pnsout_FIB = pnsout_FIB_int; end

PN Sequence

Verilog code (contd..)

//Galois implementation dff dff_inst4 (pnsout_GAL_int, clk, d5, d5n, resetin, setin ); dff dff_inst5 (d6, clk, d7, d7n, resetin, setin ); dff dff_inst6 (d7, clk, pnsout_GAL_int, pnsoutn_GAL, setin, resetin ); xorgate xorgate_inst7 (pnsout_GAL, d5, d6); always @(pnsout_GAL_int) begin pnsout_GAL = pnsout_GAL_int; end endmodule

DFF Inst1

Waveform

DFF Inst2

Waveform

DFF Inst3

Waveform

DFF Inst4

Waveform

DFF Inst5

Waveform

DFF Inst6

Waveform

XORGATE Inst4

Waveform

XORGATE Inst7

Waveform

PNS Inst

Waveform

PNS TEST

Waveform

PORT GRAPH

Waveform

Tools & Language

Tools
Cadence NCVERILOG Mentor Modelsim

Language
Verilog

Bibliography

Andrew J. Viterbi: Principles of Spread Spectrum Communication, Addison Wesley, 1995 Simon Haykin: Communication Systems, John Wiley,
2000

Don Torrieri: Principles of Spread Communication Systems, Springer, 2005

Spectrum

Thank You