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Introduction to VHDL
VHDL stands for Very High Speed Integrated Circuit Hardware Description Language. It is used in electronic design automation to describe digital and mixed signal systems such as field programmable gate arrays and integrated circuits.
Introduction to VHDL
A circuit or subcircuit described with code is called a design entity or just entity. It has two main part:
Entity
Entity declaration
Architecture
Architecture
End architecture_name;
time functions (change with delay) --signal assignment statement use to keep intermediate results --variable assigment statement use to maintain a constant value
Variable
:=
Constant
Operators
BOOLEAN ARITHMETIC AND LOGIC (+, -, x, AND, OR, XOR,..) RELATIONAL (=, /=, <=, >=)
Standard Logic
Give information to the port what value and signal should it carry (0 or1) Two types of standard logic : a) STD_LOGIC (normally used to model a logic bit) b) STD_LOGIC_VECTOR (contains a onedimensional array of std_logic) Requires the inclusion of special standard logic libraries
LIBRARY ieee; USE ieee.std_logic_1164.all;
Dataflow Modelling
Example 1
Library ieee; Use ieee.std_logic_1164.all; entity logfunc is port (y1, y2, y3: in std_logic; f : out std_logic); end logfunc; architecture LogicFunc of logfunc is begin f <=(not y1 and not y2 and y3) or (y1 and not y2 and not y3) or (y1 and not y2 and y3) or (y1 and y2 and not y3); end LogicFunc;
logfunc
y1 y2 y3 Logic Function f
Example 2
Library ieee; Use ieee.std_logic_1164.all; entity fulladdr is port (Cin, x, y : in std_logic; S, Cout : out std_logic); end fulladdr; architecture LogicFunc of fulladdr is begin s <= x xor y xor Cin; Cout <= (x and y) or (Cin and x) or (Cin and y); end LogicFunc;
fulladdr
x y Cin Logic Function Cout f
Exercise
Complete the VHDL coding below to model the circuit on the right entity Ha is port (a, b : in std_logic; s, c : out std_logic); Ha end Ha;
a
s= a + b c =a . b
s c
end Dataflow;
Structural Modelling
Example 1
entity Fa is port (a, b, Cin : in std_logic; Sum, Cout : out std_logic); end Fa; architecture Structural_Fa of Fa is signal s1, s2, s3: std_logic; component Ha port (a, b : in std_logic; s, c : out std_logic); end component; begin u1: Ha port map (a, b, s1, s2); u2: Ha port map (s1, Cin, Sum, s3); Cout <= s3 or s2;
Cout
Fa
a b Cin Cout Sum
Cin Ha a b a b s c Ha a b s c Sum
end Structural_Fa;
Behavioural Modelling
Example 1
entity compare is port (a, b : in std_logic; z : out std_logic); end compare; architecture Behav of compare is begin process (a, b) begin z <= 0; if a = b then z <= 1; end if; end process; end Behav;
Exercise
Complete the VHDL coding below to obtain the VHDL Behavioural Model of gate OR
entity OR is port ( ); end OR; architecture Behav_OR of OR is begin process ( ) begin
x y
Combinational Logic
Sequential statement order may effect the semantics of the code. There are three variants of sequential statements: IF statement, CASE statement and LOOP statement. The sequential statement must be placed inside another type of statement, called a PROCESS statement.
process (a, b) begin z <= 0; if a = b then z <= 1; end if; end process;
sel
Example 2 Obtain the logic circuit modelled by the VHDL code below:
entity LogicCircuit is port (a, b : in std_logic_vector(3 downto 0); s : in std_logic; z : out std_logic_vector(3 downto 0); end LogicCircuit; architecture behav of LogicCircuit is begin process (a, b, s) begin if s = 0 then z <= a; else z <= b; end if; end process; end behav;
architecture archmux of mux is begin with s select x <= a when 00; b when 01; c when 10; d when others; end archmux;
architecture archmux of mux is begin x <= a when (s = 00) else b when (s = 01) else c when (s = 10) else d; end archmux;
Problems
Problem 1
Derive the Boolean equation generated by the synthesis of the VHDL code fragment below.
architecture muxdesign of mux is begin process (a, b, c, d, s) begin if s = 00 then x <= a; elseif s = 01 then x <= b; elseif s = 10 then x <= c; else x <= a; end if; end process; end archmux;
Problem 2
CAD Lab Assignment a) Design and simulate a dataflow model of the half-adder module (HA). b) Design and simulate a structural model of a full-adder (FA), using the half-adder already designed in (a).
LAB 2
Revision of Memory
Memory (data storage) is a device for storing binary data for some interval of time. Basic type of memory: semiconductor, magnetic and optical. Memory can be divided into 2 categories: primary (main) memory and secondary memory. Main memory: Use in executing storing program (fast operation). A program and data used by the program reside in the main memory. Consist of semiconductor memories: RAM and ROM. Component of RAM that will be discussed (VHDL program) flip flop.
Revision of Memory
RAM Random accessed memory. Volatile, cannot retain stored data when power is off. Data can be readily written into and read from any selected address in any sequence. When data are written into a given address in RAM, the previous stored data will be destroyed and replaced by the new data. For short term data storage. Type of RAM Static RAM: use storage element (eg: FF) to store data for the time as long as the power is on. Dynamic RAM: store data on capacitors, which required periodic recharging to retain the data.
Revision of Memory
ROM Read only memory. Non-volatile , can retain stored data when power is off. Store data permanently/semi permanently. Data can be read from memory but cannot be written. ROM stored data is used for system application . Type of ROM BIOS ROM: programmed by manufacturer. PROM: programmable ROM. EPROM: erasable PROM. EEPROM: electrical EPROM.
The memory remembers the effect of previous input and feedback the data to the combinational logic circuit, to be used together with the present input. Component of RAM that will be discussed (VHDL program) counter and register.
Flip-flops (FFs)
FF is an edge-triggered memory device. Edge-triggered FF ignores the pulse while it is at a constant level. It triggers only during a transition of the clock signal. Some FFs trigger on the positive edge (0-to-1 transition), whereas others trigger on the negative edge (1-to-0 transition).
Flip-flops (FFs)
Clock edge detection in VHDL In positive-edge triggered FF, the Q output changes only as a result of a 0-to-1 transition of the clock signal. Syntax CLK event is applied to recognize signal transition. This syntax uses an attribute that refers to a property of an object, which is event attribute that refers to any change in CLK signal. VHDL code: if (CLK event and CLK=1) then means a condition if the value of CLK signal has changed and the value now is 1. This condition models a positive clock edge in VHDL.
d CLK
D ff Q q
Example 2
Negative-edge triggered D Flip-flop with asynchronous reset input
entity Dff is port (CLK, RST : in std_logic; Data_in : in std_logic d Data_out : buffer std_logic); CLK end Dff; architecture arc_Dff of Dff is begin process (CLK, RST) begin if (RST=1) then Data_out <= 0; else if (CLK event and CLK=0) then Data_out <= Data_in; else Data_out <= Data_out; end if; end if; end process; end arch_Dff;
D ff clr Q q
RST
pst
rst
Example 3
8-Bit Register
entity reg8 is port (clock, load : in std_logic; rst, pst : in std_logic; data : in std_logic_vector(7 downto 0); Q : buffer std_logic_vector(7 downto 0)); end reg8; architecture arc_reg8 of reg8 is begin process (clock) begin if rst=1 then Q <= (others => 0); elsif pst=1 then Q <= (others => 1); elsif (clock event and clock=0) then if load=1 then Q <= data; else Q <= Q; end if; end if; end process; end arc_reg8;
Example 4
Shift Register
entity shiftLreg is port (d : in std_logic_vector(7 downto 0); ldsh, en, w : in std_logic; clk, rst : in std_logic; q : buffer std_logic_vector(7 downto 0)); end shiftLreg; architecture arc_shift of shiftLreg is begin process (clk, rst) begin if rst=0 then q <= (others => 0); elsif (clk event and clk=1) then if en=1 then if ldsh=1 then q <= d; else q(0) <= w; for i in 1 to 7 loop q(i) <= q(i-1); end loop; end if; end if; end if; end process; end arc_shift;
Exercise
a) Based on Example 3, what type of the shift register? (state the direction) b) From your opinion, which part of the program should be modified for shift register of the other direction? c) Create VHDL codes to perform (b).
Answer
a) Shift Left Register b) Modified for-loop in the program for Shift Right Register c) q(7) <= w; for i in 0 to 6 loop q(i) <= q(i+1); end loop;
Example 5
Synchronous Counters
entity prog_counter is port (data : in std_logic_vector(4 downto 0); ld, inc : in std_logic; clk, clrreg : in std_logic; Q : out std_logic_vector(4 downto 0)); end prog_counter; architecture arc_counter of prog_counter is signal temp : in std_logic_vector(4 downto 0); begin process (clk, clrreg, ld, inc) begin if clrreg=1 then temp <= (others => 0); else if (clk event and clk=1) then if ld=1 then temp <= data; else if inc= 1 then temp <= temp+1; else temp <= temp; end if; end if; end if; end if; end process; Q <= temp; end arc_counter;
Synchronous Counter
Example 5 describes a 5-bit up-counter with enable and asynchronous reset. The signal temp is defined to represent the flip-flop in counters. This signal is not needed if Q have buffer mode as shown in Example 6. pst
data4:0 load clock 5 pre D 8 en reg8 clr Q q
clrreg
Example 6
Synchronous Counters
entity upcount is port (data : in integer range 0 to 31; ld, inc : in std_logic; clk, clrreg : in std_logic; Q : buffer integer range 0 to 31); end upcount; architecture behaviour of upcount is begin process (clk, clrreg) begin if clrreg=0 then Q <= 0; elsif (clk event and clk=1) then if ld=1 then Q <= data; else if inc= 1 then Q <= Q+1; else Q <= Q; end if; end if; end if; end process; end behaviour;