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An MOS Transistor
|VGS|
n+
n+
n-channel p-substrate B
Depletion Region
Transistor in Linear
VGS S G n+ VDS D n+ L x ID
V(x)
p-substrate B
Transistor in Saturation
VGS VDS > VGS - VT D
G S n+
-
VGS - VT
n+
Pinch-off
Current-Voltage Relations
6 x 10
-4
VGS= 2.5 V
Resistive
Saturation
VGS= 2.0 V
VDS = VGS - VT
VGS= 1.5 V
Quadratic Relationship
ID (A)
VGS= 1.0 V
0.5
1 V DS (V)
1.5
2.5
Velocity Saturation
( Deep sub micron Era)
u n ( m /s)
usat = 105
Constant velocity
xc = 1.5
x (V/m)
Perspective
ID
Long-channel device VGS = VDD Short-channel device
V DSAT
VGS - V T
VDS
ID versus VGS
6
5 4
I D (A)
x 10
-4
x 10 2.5
-4
quadratic
linear
1.5
ID (A)
3 2 1
0.5
quadratic
0.5 1
VGS(V)
0 0
1.5
2.5
0 0
0.5
1
VGS(V)
1.5
2.5
Long Channel
Short Channel
A PMOS Transistor
0 x 10
-4
VGS = -1.0V
-0.2 VGS = -1.5V -0.4
ID (A)
-0.6
VGS = -2.0V
-0.8
VGS = -2.5V
-1 -2.5
-2
-1.5
VDS (V)
-1
-0.5
MOS Capacitances
G
CGS S
CGD D
CSB
CGB
CDB
n+
L Cross section
n+
Gate Capacitance
G CGC S D S G CGC D S G CGC D
Cut-off
Resistive
Saturation
Diffusion Capacitance
Channel-stop implant N A1 Side wall W
Source ND
Bottom
xj
Side wall LS
Channel Substrate N A
Linear
10
-4
10
ID (A)
-6
Quadratic
CD I D ~ I 0e , n 1 Cox
qVGS nkT
10
-8
10
-10
Exponential VT
0.5 1
VGS (V)
10
-12
1.5
2.5
Fabrication
For a great tour through the IC manufacturing process and its different steps, check
http://www.fullman.com/semiconductors/semico nductors.html
Create contact and via windows Deposit and pattern metal layers
Inverter Layout
VDD
Fabrication Steps
Start with blank wafer (typically p-type where NMOS is created) First step will be to form the n-well (where PMOS would reside)
Cover wafer with protective layer of SiO2 (oxide) Remove oxide layer where n-well should be built Implant or diffuse n dopants into exposed wafer to form nwell Strip off SiO2
p substrate
Oxidation
SiO 2
p substrate
Photoresist
Photo resist Photoresist is a light-sensitive organic polymer Property changes where exposed to light Two types of photo resists (positive or negative) Positive resists can be removed if exposed to UV light Negative resists cannot be removed if exposed to UV light
Photoresist
SiO 2
p substrate
Lithography
Expose photoresist to Ultra-violate (UV) light through the n-well mask Strip off exposed photo resist with chemicals
Photoresist SiO 2
p substrate
Etch
Etch oxide with hydrofluoric acid (HF) Only attacks oxide where resist has been exposed N-well pattern is transferred from the mask to silicon-di-oxide surface; creates an opening to the silicon surface
Photoresist SiO 2
p substrate
Strip Photoresist
SiO 2
p substrate
N-well
N-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic-rich gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si SiO SiO2 shields (or masks) areas which remain pn well type
2
Strip Oxide
Strip off the remaining oxide using HF Subsequent steps involve similar series of steps
n well p substrate
Deposit very thin layer of gate oxide < 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
Self-Aligned Process
Use gate-oxide/poly silicon and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact
n well p substrate
N-diffusion/implantation
Pattern oxide and form n+ regions Self-aligned process where gate blocks n-dopants Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing
n+ Diffusion
n well p substrate
N-diffusion/implantation cont.
Historically dopants were diffused Usually high energy ion-implantation used today But n+ regions are still called diffusion
n+
n+ n well p substrate
n+
P-Diffusion/implantation
Similar set of steps form p+ diffusion regions for PMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+ p substrate
p+ n well
p+
n+
Contacts
Now we need to wire together the devices Cover chip with thick field oxide (FO) Etch oxide where contact cuts are needed
Contact
Metalization
Sputter on aluminum over whole wafer Gold is used in newer technology Pattern to remove excess metal, leaving wires
Metal
CMOS INVERTER
VDD
V DD V DD Rp
V in 5 V DD
V in 5 0
VDD
2.5
0.5
1.5
0.5
1.5
ln(0.5)
VDD
0.5 0.36
Vin = V DD RonCL
t
Transient Response
3 2.5 2 1.5 1 0.5 0 -0.5 0
?
tp = 0.69 CL (Reqn+Reqp)/2
tpLH tpHL
Vout(V)
0.5
1 t (sec)
1.5
2 x 10
2.5
-10
tp(normalized)
1.2
1.4
1.6
1.8
2.2
2.4
DD
(V)
tp(sec)
Leakage
Leaking diodes and transistors
Vin
Vout
CL
2 dd L 2 dd
*f
Vin CL
Vout
0.15
IVDD (mA)
0.10
0.05
0.0
1.0
4.0
5.0
Leakage
Vd d
Vout
Sub-threshold current one of most compelling issues Sub-Threshold Current Dominant Factor in low-energy circuit design!
Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 0.9 V by 2010!)
Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
PUN
NMOS only
Threshold Drops
PUN VDD
S
VDD
D
VDD
D
0 VDD CL
VGS
PDN
D
VDD 0
VGS
VDD
S
CL
CL
CMOS Properties
Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors
Delay (psec)
67 64
61 45
Voltage [V]
1.5 1
0.5 0
A=1, B=10
0 100 200 300 400
80
81
-0.5
A= 10, B=1
time [ps]
Transistor sizing
Progressive sizing
InN
MN
CL
Distributed RC line M1 > M2 > M3 > > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks
M3 M2 M1
C3 C2 C1
Transistor ordering
critical path critical path 01 In1 M3 In2 1 M2 In3 1 M1
In3 1 M3
In2 1 M2 In1 M1 01
charged CL
C2 charged C1 charged
charged CL
C2 discharged C1 discharged
Summary