Interrupts

Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device An interrupt is considered to be an emergency signal. The Microprocessor should respond to it as soon as possible. When the Microprocessor receives an interrupt signal it complete the currently executing instruction & store the content of program counter (address of next instruction to be fetched) onto stack and jumps to an Interrupt Service Routine(ISR) to respond to the incoming interrupt. After interrupt request accepted processor generate INTA (interrupt Acknowledge) Each interrupt have its own ISR. Interrupts can be classified into two types: 1. Hardware Interrupt: MPU pin used to receive interrupt request 2. Software Interrupt: The cause of interrupt is an execution of instruction. When interrupt is active 8085 execute a CALL instruction to predefined location.

Hardware Interrupt
8085 have 5 hardware interrupt TRAP RST 7.5 RST 6.5 RST 5.5 & INTR Location from where subroutine is referred as Vector Location.--- Called Vectored Interrupt TRAP, RST7.5, RST 6.5 & RST5.5 are vectored interrupt. These interrupt transfer program control to predetermined location INTR is a non-vectored interrupt, it requires external hardware for subroutine address. Responding to Interrupts: Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable TRAP has highest priority, Non maskable interrupt INTR has lowest priority TRAP is Level sensitive and edge sensitive RST 7.5 +edge sensitive RST 6.5, RST 5.5 & INTR are level sensitive

Software Interrupt
8085 have 8 software interrupt. RST0 RST 7 Vector address calculated as All interrupts are mapped onto a memory area called the Interrupt Vector Table(IVT). The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives. The IVT is divided into several blocks. Each block is used by one of the interrupts to hold its address. The 8085 recognizes 8 RESTART instructions: RST0 -RST7. Each of these RST would send the execution to a memory location

Sequence for INTR

1) 2) 3) 4) 8085 checks the status of INTR during execution of each instruction 8085 complete current instruction and send INTA (interrupt acknowledge) In response to INTA external logic place OPCODE on the data bus 8085 save the address of next instruction on the stack and execute received instruction

Restart Instruction
The restart sequence is made up of three machine cycles In the 1st machine cycle: The microprocessor sends the INTA signal. Program counter holds the address of next instruction to be store in stack, data lines opcode of RST instruction receive from the interrupting device 6 T state In the 2nd machine cycles: High order address of program counter placed on (SP-1) address. 3- T state In the 3rd machine cycles: Low order address of program counter placed on (SP-2) address. 3- T state Then the microprocessor jumps to the address associated with the specified RST instruction

Set Interrupt Mask(SIM)

This instruction used to set/mask interrupt or send serial data. It transfer content of accumulator to interrupt control logic It is necessary to appropriate content before execution of SIM instruction

Bit 0 is the mas kfor RST 5.5 bit 1 is the mask for RST 6.5 and bit 2 is the mask for RST 7.5. If the mask bit is 0 the interrupt is available. If the mask bit is 1, the interrupt is masked. Bit 3 (Mask Set Enable -MSE) is an enable for setting the mask. If it is set to 0 the mask is ignored and the old settings remain. If it is set to 1 the new setting are applied. Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the microprocessor did not respond to it. Bit 5 is not used by the SIM instruction Bit 6 is used to tell the microprocessor whether or not to perform serial data transmission If 0 then do not perform serial data transmission If 1 then not perform serial data transmission The value to be sent out on SOD has to be placed in bit 7 of the accumulator

Example
Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked and RST7.5 is enabled. First determine the contents of the accumulator

Read Interrupt Mask(RIM)

Since the 8085 has five interrupt lines interrupts may occur during an ISR and remain pending. Using the RIM instruction the programmer can read the status of the interrupt lines and find if there are any pending interrupts -- RIM instruction allow the serial input data

Example
Set the mask to enable RST6.5 without modifying the masks for RST5.5 and RST7.5.

 The 8259A is a programmable interrupt controller designed to work with Intel microprocessors 8085, 8086, and 8088. The 8259A interrupt controller can 1. manage eight interrupt according to the instructions written into its control registers. This is equivalent to providing eight interrupt pins on the processor in place of one INTR (8085) pin. 2. vector an interrupt request anywhere in the memory map. However, all eight interrupts are spaced at the interval of either four or eight locations. This eliminates the major drawback of the 8085 interrupts in which all interrupts are vectored to memory locations on page 00H. 3. Resolve eight levels of interrupt priorities in a variety of modes, such as fully nested mode, automatic rotation mode, and specific rotation mode 4. Mask each interrupt request individually. 5. Read the status of pending interrupts, in-service interrupts, and masked interrupts. 6. Be set up to accept either the level-triggered or the edge-triggered interrupt request. 7. Be expanded to 64 priority levels by cascading additional 8259As. 8. Be set up to work with either the 8085 microprocessor mode or the

The 8259A programmable Interrupt Controller

Block Diagram of 8259A

It includes eight blocks: control logic, read/write logic, data bus buffer, three registers (IRR, ISR, and IMR), priority resolver, cascade buffer.

Block Diagram of 8259

 Read/Write Logic This is typical Read/Write control logic. When the address line A0 is at logic 0, the controller is selected to write a command or read a status . The chip select logic and A0 determine the port address of the controller. Control Logic This block has two pins: INT (Interrupt) as an output, and INTA (Interrupt Acknowledge) as an input. The INT is connected to the interrupt pin of the MPU. Whenever a valid interrupt is asserted, this signal goes high. The INTA is the Interrupt Acknowledge signal from the MPU. Interrupt Registers and Priority Resolver The interrupt Request Register (IRR) has eight input lines (IR0-IR7) for interrupts. When these lines go high, the requests are stored in the register. The In-service Register (ISR) stores all the levels that are currently being serviced, and the Interrupt masked Register (IMR) stores the masking bits of the interrupt lines to be masked. The Priority resolver (PR) examines these registers and determines whether INT should be sent to the MPU. Cascade Buffer/Comparator This block is used to expand the number of interrupt levels by cascading two or more 8259As.

 To implement interrupts, the Interrupt Enable flipflop in the microprocessor should be enabled by writing the EI instruction, and the 8259A should be initialized by writing control words in the control register. The 8259A requires two types of control words. Initialization Command Words (ICWs) and Operational Command Words (OCWs). The ICWs are used to set up the proper conditions and specify RST vector addresses. The OCWs are used to perform functions such as masking interrupts, setting up status-read operations, etc.

Interrupt Operation

1. 2.

3. 4.

5. 6.

7.

8.

After the 8259A is initialized, the following sequence of events occurs when one or more interrupt request lines go high: The IRR stores the requests. The priority resolver checks three registers: the IRR for interrupt requests, the IMR for masking bits, and the ISR for the interrupt request being served. It resolves the priority and sets the INT high when appropriate. The MPU acknowledge the interrupt by sending INTA. After the INTA is received, the appropriate priority bit in the ISR is set to indicate which interrupt level is being served, and the corresponding bit in the IRR is reset to indicate that the request is accepted. Then, the opcode for the CALL instruction is placed on the data bus. When the MPU decodes the CALL instruction, it places two more INTA signals on the data bus. When the 8259 receives the second INTA, it places the low order byte of the CALL address on the data bus. At the third INTA, it places the high order byte on the data bus. The CALL address is the vector memory location for the interrupt; this address is placed in the control register during the initialization. During the third INTA pulse, the ISR bit is reset either automatically (Automatically-End-of-Interrupt-AEOI) or by a command word that must be issued at the end of the service routine (End-of-Interrupt-EOI). This option is determined by the initialization command word. The program sequence is transferred to the memory location specified by the CALL instruction.

Priority Modes and Other Features

Many types of priority modes are available under software control in the 8259A, and they can be changed dynamically during the program by writing appropriate command words. Commonly used priority modes: 1. Fully nested mode 2. Automatic Rotation mode 3. Specific Rotation mode

 End of Interrupt After the completion of an interrupt service, the corresponding ISR bit needs to be reset to update the information in the ISR. This is called the END-of-Interrupt (EOI) command. It can be issued in three formats: 1. Non specific EOI command 2. Specific EOI command 3. Automatic EOI

Additional Features of 8259A

The 8259A is a complex device with various modes of operation. Interrupt Triggering: The 8259A can accept an interrupt request with either the edge-triggered mode or the leveltriggered mode. The mode is determined by the initialization instructions. Interrupt Status: The status of three interrupt registers (IRR, ISR, and IMR) can be read, and this status information can be used to make the interrupt process versatile. Poll Method: The 8259A can be set up to function in a polled environment. The MPU polls the 8259A rather than each peripheral.

8259-Programmable Interrupt Controller

It is programmed to work with either 8085 or 8086 processor. It manage 8-interrupts according to the instructions written into its control registers. If we save NMI for a power failure interrupt, this leaves only one interrupt for all the other applications. For applications where we have interrupts from multiple source, we use an external device called a priority interrupt controller ( PIC ) to the interrupt signals into a single interrupt input on the processor. The interrupts can be masked or unmasked individually. The 8259s can be cascaded to accept a maximum of 64 interrupts. All the interrupt can be prioritize Each interrupt request individually Set up to either edge trigger or level triggered interrupt Vector address of Interrupt assigned by user

Block Diagram

It has eight functional blocks. They are 1) Control logic-- This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. 2) Read Write logic--- This circuit accepts and decodes commands from the CPU. This block also allows the status of the 8259A to be transferred on to the data bus. 3) Data bus buffer 4) Interrupt Request Register (IRR)keeps information of incoming interrupt 5) In-Service Register (ISR)keeps information of interrupt currently executed 6) Interrupt Mask Register (IMR)keeps information of interrupt can be masked 7) Priority Resolver (PR)checks the priority of incoming interrupt 8) Cascade buffer:---The data bus and its buffer are used for the following activities. The processor sends control word to data bus buffer through D0-D7. The processor read status word from data bus buffer through D0-D7 From the data bus buffer the 8259 send type number (in case of 8086) or the call opcode and address (in case of 8085) through D0-D7 to the processor.

Signal Description
CS: This is an active-low chip select signal for enabling RD and WR operations of 8259A. RD : This is an active-low read enable input to 8259A. A low on this line enables 8259A to release status onto the data bus of CPU. The processor uses the RD (low), WR (low) and A0 to read or write 8259. D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to control word or from status word registers. This also carries interrupt vector information. CAS0 CAS2 Cascade Lines : A single 8259A provides eight vectored interrupts. If more interrupts are required, the 8259A is used in cascade mode. In cascade mode, a master 8259A along with eight slaves 8259A can provide up to 64 vectored interrupt lines. These three lines act as select lines for addressing the slave 8259A. SP/EN : (Slave program/ Enable Buffer)This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as buffered enable to control buffer transreceivers. If this is not used in buffered mode then the pin is used as input to designate whether the chip is used as a master (SP =1) or slave (EN = 0). INT : This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt the CPU and is connected to the interrupt input of CPU. IR0 IR7 (Interrupt requests) :These pins act as inputs to accept interrupt request to the CPU A0- Command Select Address

8279 Keyboard & Display

Intels 8279 is a general purpose keyboard display controller. It is a hardware approach to interface matrix keyboard and multiplexed display. It simultaneously drives the display of a system and interfaces a keyboard with the CPU. 8279 has two major segment (1) Keyboard (2) Display Keyboard segment connected to 64-contact key matrix. Display segment provide 16 character scanned display interface (LED). Keyboard entries are denounce and stored in FIFO; an interrupt signal generated with each entry. Display segment has 16*8 R/W RAM. Which can be used to read /write for display. It provides 3 input for keyboard (1) Scanned keyboard (2) Scanned sensor Keyboard (3) Strobed Input mode 8279 are divided into 4 functional group CPU Interface Keyboard

Scan

Display

Block Diagram

CPU interface section:

The CPU interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU. It requires two internal address A0 =0 for selecting data buffer and A0 = 1 for selecting control register of 8279. The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279. It has an interrupt request line IRQ, for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler. The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.

 I/O Control and Data Buffers :

The I/O control section controls the flow of data to/from the 8279. The data buffers interface the external bus of the system with internal bus of 8279. The I/O section is enabled only if CS is low. The pins A0, RD and WR select the command, status or data read/write operations carried out by the CPU with 8279

Control and Timing Register and Timing Control :

These registers store the keyboard and display modes and other operating conditions programmed by CPU. The Timing and control unit controls the basic timings for the operation of the circuit. Scan counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies.

Scan Counter :
The scan counter has 4 scan counter and 4 scan line (SL0-SL3) These 4 scan line can be decoded using 4 to 16 decoder to generate 16 lines for scanning. These line connected to row of a matrix keyboard and digit drivers of display.
The scan counter has two modes to scan the key matrix and refresh the display. In the encoded mode, the counter provides binary count 0000 to 1111 that is to be externally decoded to provide the scan lines SL0-SL3 for keyboard and display. Binary count must be externally decoded. In the decode scan mode, the counter internally decodes the least significant 2 bits and provides 4 possible combination 1110,1101,1011,0111 on scan on SL0-SL3. The output of these line are active low

Keyboard Section
Keyboard section consist of eight line (RL0-RL7) connected to eight column of keyboard and two additional lines SHIFT and CNTL/STB. Status of the SHIFT and Control key can be stored along with key closure. The keys are automatically denounced. The keyboard can operate in two mode (1) Two-key lock out (2) N-Key Roll over In Two-key lock out mode if two keys are pressed almost simultaneously only the first key are recognized. In N-Key roll over mode simultaneous keys are recognized and their code are stored in the internal buffer. (No key recognized until only one key remains pressed) The keyboard section also includes 8*8 FIFO RAM. FIFO RAM consist of 8 register that can store keyboard entries. Each entries read in order Status logic keeps track of number of entries and provides the IRQ(Interrupt Request) signal when the FIFO is not empty.

 Keyboard denounce control looking for key closures in that row. In scanned keyboard only if denounce circuit detect a close switch it wait for 10 msec. After the denounce period, if the key continues to be detected. The code of key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status. FIFO RAM status keeps track the number of character in the FIFO and whether it is full or empty. In scan sensor matrix mode pressed key is arranged in the form of matrix In strobed input mode pressed key information will be stored in FIFO RAM.

(SCAN)

(RETURN)

Display Section
The display section has eight output lines divided into two groups A0-A3 and B0-B3. These line used either 8 line or two group of 4 lines. This section consist of 16*8 display RAM. MPU read from or write into any of these register. The display address register holds the address of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU. The 8279 provides two basic output mode left Entry (Typewriter)Display character left to right Right Entry (Calculator)Display character right to left If auto increment flag is set to1 after each write operation Display RAM address is incremented by one.

Pin Diagram

Interfacing Scheme

Signal Description
DB0-DB7 : These are bidirectional data bus lines. The data and command words to and from the CPU are transferred on these lines. CLK : This is a clock input used to generate internal timing required by 8279. RESET : This pin is used to reset 8279. A high on this line reset 8279. After resetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler is set to 31. CS : Chip Select A low on this line enables 8279 for normal read or write operations. Other wise, this pin should remain high. A0 : A high on this line indicates the transfer of a command or status information. A low on this line indicates the transfer of data. This is used to select one of the internal registers of 8279. RD, WR (Input/output ) READ/WRITE These input pins enable the data buffers to receive or send data over the data bus. IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor RAM. The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM further contains any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU. Vss, Vcc : These are the ground and power supply lines for the circuit.

8086-Processor

8086 is a 16 bit microprocessor. It has 16-bit ALU, internal register and instruction are designed to work with 16 bit binary word. 8086 has 16 bit data bus. It can read or write data to memory and port either 16 bit or 8 bit at a time.

8086 has a 20 bit address bus can access up to 2^20 memory locations or 10,48,576 (1MB).
8086 can generate 16-bit I/O address, hence it cam access 2^16 = 65576 I/O ports 8086 provides fourteen 16 bit register. It has multiplexed address and data bus AD0- AD15 and A16 A19. it reduces the number of pins

8086 is designed to operate in two modes Minimum and Maximum. When only one 8086 CPU is used in a microcomputer 8086 in minimum mode. When 8086 used in multiprocessing system 8086 used in maximum mode. In maximum mode external bus controller(8288) required. It can prefetches upto 6 instruction bytes from memory and queues the min order to speed up instruction execution.

 Register organization/ programming model

8086 has eight 8-bit register(AH,AL,BH,L,CH,CL,DH,DL) which can be used as for 16 bit (AX,BX,CX,DX) by clubbing. 8086 have 4 segment register (code segment, data segment, extended segment, source segment.) 8086 have 16 bit flag register 8086 have 4 index register and one Instruction pointer register.

Segment Register
8086 divides 1MB memory into 4. segment. Each segment is 64 KB Any location in segment access by 16 bit Segment used to hold upper 16-bit of starting address of the memory segment on which 8086 works in a particular time. Starting address of segment also known as base address. BIU insert zero for a lower 4-bit(nibble) in the content of segment register to generate 20-bit address.

CS(code segment) register holds upper 16-bit of the starting address of the segment from which BIU currently fetching the instruction code. SS(stack segment) register is used for upper 16-bit of the starting address for stack register. ES(extended segment) and DS(data segment) register are used to hold the upper 16-bit of the starting address of the segment which are used for data transfer. Segment are 16 bit register. To generate 20-bit physical address pointer or index register used with each segment. IP associated with Code Segment BP associated with Data Segment SP associated with Stack Segment Index register holds the offset within code, data and stack segment.

Architecture of 8086
8086 internally divide into two separate unit Bus interface unit(BIU) and Execution unit(EU). These two functional unit works simultaneously to increase system speed and throughput. Throughput is measure of number of instruction executed per unit time.

BIS INTERFACE UNIT

BIU provide 16-bit data bus 20-bit address bus interface to the outside world.

The BIU performs all bus operations Send address of memory or I/O fetches instruction from memory read data from port/memory write data into port/memory supports instruction queuing Address relocation facility.
BIU contains Instruction queue, Segment registers, Instruction pointer, Address summer and bus control logic

Instruction Queue
To speed up the program execution BIU fetches 6 instruction ahead if time. These prefetches instruction are held in queue for the execution. Queue operate on the FIFO principal In 8086 it is possible to fetch next instruction while current instruction is in execution While execution unit is busy with executing current instruction BIU fetches the next instruction and stores in queue. BIU continue this process as the queue is not full; instruction is always ready for EU and fetch time eliminated.

Feature of execution next instruction while current instruction is execution is called PIPILINING

Execution Unit
Execution unit of 8086 tells from where to fetch instruction or data. It contains ALU, Flag register, Instruction decoder, Pointer & index register, control circuit. 806 have 16-bit flag register

Lower 5 Sign, Zero, Carry, Auxiliary Carry, Parity flag are similar to 8085. Overflow flag(OF):- This flag set if result if out of range. Trap flag(TF):- Trap flag used for single step debugging through a program. If TF is set after execution of each instruction result is displayed in registers. Programmer can easily trace and correct the error. Interrupt flag(IF):- It is used to allow the interruption of program. Direction flag(DF):- It is used with string instruction. If DF=0 string is processed from beginning with first element having lowest address. Otherwise string is processws from high to low address.