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Introduction
BACK END
FRONT END
What is VLSI??
VLSI means Very Large-Scale Integration. It is an effort to integrate discrete component circuits in a single silicon base (chip). The integration results in a high reliability, low power consumption, high speed, less weight, low volume, and low cost of products.
HISTORY of VLSI
Small-Scale Integration (SSI) 10 gates per chip, 1960s Medium-Scale Integration (MSI) 1001000 gates per chip,1970s Large-Scale Integration (LSI) 100010,000 gates per chip, 1980s Very Large-Scale Integration (VLSI) 10,000100,000 gates per chip,1990s Ultra-Large Scale Integration (ULSI) 1M10M gates per chip, Present
Moores Law
Gordon Moore -- Intels co-founder Statement: Transistors on a IC doubles every 2 years.
nMOS pMOS CMOS Logic (nMOS & pMOS) BiCMOS I/O and Driver circuits GaAs High mobility
M1
M3
M1
M3
Fabrication Technology
Fabrication Technology
Wafers
Wafer is then ready for processing Each wafer will yield many chips
chip die size varies from about 5mmx5mm to 15mmx15mm A whole wafer is processed at a time
N-MOS Fabrication
Si Substrtate
A relatively thick silicon dioxide layer (5000A), also called field oxide, is created on the surface SI Substrate
Photolithography
Spin on photoresist
Photoresist SiO 2 Si-substrate (b) After oxidation and deposition of negative photoresist UV-light Patterned optical mask Exposed resist Si-substrate (c) Stepper exposure
Expose photoresist to UV rays through optical mask layer and strip off exposed photoresist.
N-MOS Fabrication(Contd..)
Photolithography
Remove Silicon dioxide with hydrofluoric acid. Only attacks oxide where resist has been exposed
(d) After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2 Si-substrate (e) After etching
SiO 2
Photo-Lithographic Process
optical mask oxidation
photoresist coating
stepper exposure
Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process step spin, rinse, dry
The field oxide is selectively etched to expose the silicon surface on which the MOS transistor will be created
The surface is covered with a thin, high-quality oxide layer (25A), which will eventually form the gate oxide of the MOS transistor
On top of the thin oxide, a layer of polysilicon (polycrystalline silicon, 3000A) is deposited
After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates
The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed
The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implantation ultimately creating two n-type regions (source and drain junctions) in the p-type substrate
Once the source and drain regions are completed, the entire surface is again covered with an insulating layer of silicon dioxide
The insulating oxide layer is then patterned in order to provide contact windows for the drain and source junctions
The surface is covered with evaporate aluminum (5000A) which will form the interconnects
Finally, the metal layer is patterned and etched, completing the interconnection of the MOS transistors on the surface
CMOS Technology
First proposed in the 1960s. Was not seriously considered until the severe limitations in power density and dissipation occurred in NMOS circuits Now the dominant technology in IC manufacturing Employs both pMOS and nMOS transistors to form logic elements The advantage of CMOS is that its logic elements draw significant current only during the transition from one state to another and very little current between transitions - hence power is conserved. In the case of an inverter, in either logic state one of the transistors is off. Since the transistors are in series, (~ no) current flows.
In p & n-well CMOS process, the doping density of the well region is typically about one order of magnitude higher than the substrate, which results in unbalanced drain parasitics. The twin-tub process avoids this problem.
This technology provides the basis for separate optimization of the nMOS and pMOS transistors. The starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics.
BiCMOS Technology
A known deficiency of MOS technology is its limited load driving capabilities (due to limited current sourcing and sinking abilities of pMOS and nMOS transistors. Bipolar transistors have
BiCMOS gates can be an efficient way of speeding up VLSI circuits. CMOS fabrication process can be extended for BiCMOS
Vgs<Vt
V(x)
p-substrate B
G S n+
-
VGS - VT
n+
Pinch off
VGS= 2.5 V
4
ID (A)
Resistive
VDS = VGS - VT
VGS= 1.5 V
VGS= 1.0 V
0.5
1 VDS (V)
1.5
2.5
Source to Drain Current (Ids) Threshold Voltage (Vt). Transconductance (gm) Figure of Merit (0
The NMOS body or Bulk is known either as the substrate, back gate or more commonly the Body and normally connected to source. However if is left unconnected, its effect on the DC characteristics of the device must be taken into account. If we include the bulk effect the value of the threshold voltage VT, will increase with increasing bulk voltage.
Pass Transistors
NMOS INVERTER
Vo
S D
V0
Vt (pull up)
Vdd
Vin S
Vss
Vt (pull down)
Vin
CMOS Technology
First proposed in the 1960s. Was not seriously considered until the severe limitations in power density and dissipation occurred in NMOS circuits Now the dominant technology in IC manufacturing Employs both pMOS and nMOS transistors to form logic elements The advantage of CMOS is that its logic elements draw significant current only during the transition from one state to another and very little current between transitions - hence power is conserved. In the case of an inverter, in either logic state one of the transistors is off. Since the transistors are in series, (~ no) current flows.
CMOS INVERTER
VDD
VDD
2l
PMOS
Contacts
Out Metal 1
NMOS GND
Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless. Always a path to Vdd or GND in steady state low output impedance (output resistance in k range) large fan-out. Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current. No direct path steady-state between power and ground no static power dissipation. Propagation delay function of load capacitance and resistance of transistors.
Basic Operation
VIN = 0 then VOUT = VDD VGSn = 0 < VTn . NMOS OFF VSGp = VDD > -VTp . PMOS ON VIN = VDD then VOUT = 0 VGSn = VDD > VTn . NMOS ON VSGp = 0 < -VTp . PMOS OFF
No power consumption while idling in any logic state.
V DD
V out CL
V out CL
Rn
V in = 0V (a) Low-to-high
V in = V DD (b) High-to-low
VGS = 2.5V
2 1.5 1 0.5 0 0 0.5 1
VGS = 1.0V
VDS (V)
1.5
2.5
VDS (V)
-1
0 0
VGS = -2.5V
-1
X 10-4
PMOS
Vin = 0.5
Vin = 2
NMOS
1.5
2.5
0.5
0.5
1.5
CL
~
Iav
CL
kn VDD
Vin = V DD
ln(0.5)
VDD
0.5 0.36
Vin = V DD RonCL
t
Gate to Source (CGS). Gate to Substrate (CGB). Gate to Drain (CGD). Drain to Substrate (CDB). Source to Substrate (CSB).
CGS S
CGD
CSB
CGB
CDB
BiCMOS Inverter
Speed is the only restricting factor in CMOS Inverter, especially when large capacitors must be driven. Propagation delay of CMOS inverter is more in that case, which depend on the capacitances. So Speed decreases. So, for this reason BiCMOS inverter is used in current driven circuits (Capacitance). In the BiCMOS structure, the input stage and the phase-splitter are implemented in MOS, which results in a better performance and higher input impedance. Low Power Consumption because of MOS Transistors.
When the input is high, the NMOS transistor M1 is on, causing Q1 to conduct, while M2 and Q2 are off. The result is a low output voltage When the input is low, the PMOS transistor M2 is on, causing Q2 to conduct, while M1 and Q1 are off. The result is a high output voltage.
Latch-up in CMOS
Latch-up is a failure mechanism of CMOS integrated circuits. It is characterized by excessive current drain coupled with functional and parametric failure, and finally device destruction.
Latch-up exists in all junction isolated or bulk CMOS Process Parastic PNPN paths forms NPN and PNP Bipolar Transistors which cause latch-up. Normally, only a small leakage current flows between the substrate and P-well causing only a minute bias and CMOS is well behaved. In the presence of intense ionizing radiation, thermal or over-voltage stress, however, current can be injected into the PNP emitter-base junction, forward-biasing it and the NPN device turns on, increasing the base drive to the PNP. Gain of the PNP and NPN Transistors increases. Then the CMOS draws more current from external network, thus causing Latch-up.
Reduction of substrate
resistance Rs.
Reducing N-well Resistance (Rn) in N-well Process and P-well Resistance (Rp) in P-well