ARM ARCHITECTURE

ARM Architecture

About ARM
Acronym for Advanced RISC Machines Founded in November 1990 Designs the ARM range of RISC processor cores Licenses ARM core design to semiconductor partners
ARM does not fabricate silicon itself

Develops technologies to assist with the designing of the ARM architecture

Software tools, boards, debug hardware, application software, bus architectures, peripherals, etc
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CISC Vs RISC
CISC Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions
ARM Architecture

RISC Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers
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About RISC
Reduced Instruction Set Computer Common Characteristics
One Instruction per cycle Register to Register operations Large register file Simple Addressing Modes Simple Instruction Formats Hardwired Programmed Unit Less number of instructions

More complex compiler design

ARM Architecture

Benefits of RISC approach

Faster Execution
No microcode and simple instructions

Effective pipelining
Lesser pipeline stalling

Programs more responsive to interrupts

ARM Architecture

Features of ARM Architecture

Typical RISC Features
Large uniform register file Load/Store Architecture Simple Addressing Modes Uniform and fixed-length instruction fields

Additional Features
Control over ALU and shifter Auto-increment and auto-decrement addressing modes Load and Store multiple instructions Conditional execution of all instructions
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Evolution of ARM Architecture

version
Future ARM1136JF-S ARMv6 ARM102xE XScaleTM ARMv5
ARM7TDMI-S StrongARM

ARM1026EJ-S

ARM9x6E ARM926EJ-S SC200 ARM92xT

SC100

ARM720T

1994

1996

1998

2000

2002

2004

2006

time
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ARM Architecture Versions

Version 1
Basic data processing instructions No Multiply instruction Byte, word and multi word load/store instructions Branch instructions Software interrupt

Version 2
Multiply and Accumulate Instructions
Coprocessor support Two more banked regs in fast interrupt mode SWP and SWPB load and store instructions 26-bit address space
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ARM Architecture

ARM Architecture Versions

Version 3
32-bit address space CPSR SPSR MRS and MSR instructions to access CPSR & SPSR Two new processor modes

Version 4
Half word load/store instructions Load and sign extend bytes and halfwords instructions T Thumb state transfer instruction Privileged processor mode

ARM Architecture

ARM Architecture Versions

Version 5
ARM/Thumb interworking improved in T variants Count leading zeros instr efficient integer divide and interrupt prioritization routines Software breakpoint instr More coprocessor instructions

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ARM Architecture Variants

T Variants - Thumb Instruction set
Re-encoded subset of ARM instructions Advantages
Half the size of ARM instructions Greater code density

Disadvantages
More instructions for the same job Some exception handling instructions are not included

ARM code best for maximizing performance of time critical code

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ARM Architecture Variants

M Variants Long Multiply Instructions
Four instructions 32 x 32 -> 64 multiplications 32 x 32 + 64 -> 64 multiply accumulate

E Variants Enhanced DSP Instructions

Includes DSP instructions 16-bit MAC instruction Add and sub with saturated signed arithmetic

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Features
Features DSP Jazelle

Architecture
v4T

Thumb

Media

v5TE
v5TEJ v6

P P P P

P P P

P P

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ARM Architecture Versions

Version ARM Instr version Thumb Instr Long Mult version instr Enhanced DSP

V3
V3M V4 V4TxM V4T V5 V5T

3
3 4 4 4 5 5

None
1 1 None 2

No
No Yes No Yes Yes Yes

No

V5TxM
V5TE

5
5

2
2

No
Yes

Yes

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ARM7TDMI T Thumb Code D JTAG Debug M Fast Multiplier I Embedded Cell Macrocell F Vector Floating Point

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Development of the ARM Architecture

Improved
Halfword and signed halfword / byte support System SA - 110

ARM/Thumb Interworking CLZ

5TE

Jazelle Java bytecode execution

5TEJ

Saturated maths DSP multiply -

ARM9EJ - S

ARM926EJ - S

mode
SA - 1110 accumulate instructions ARM7EJ - S ARM1026EJ - S

3
Thumb instruction Early ARM set ARM7TDMI ARM9TDMI ARM1020E

SIMD Instructions Multi - processing

4T
XScale

V6 Memory architecture (VMSA) ARM9E - S Unaligned data ARM720T ARM940T ARM966E - S

ED500

architectures

support

ARM1136EJ - S 16

The ARM Architecture

ARM Architecture

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ARM Powered Products

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Intellectual Property
ARM provides hard and soft views to licensees
RTL and synthesis flows GDSII layout

Licencees have the right to use hard or soft views of the IP

soft views include gate level netlists hard views are DSMs

OEMs must use hard views

to protect ARM IP

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Data Sizes and Instruction Sets

The ARM is a 32-bit architecture. When used in relation to the ARM:
Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes)

Most ARMs implement two instruction sets

32-bit ARM Instruction Set 16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode

ARM Architecture

Programmers Model
Data Types Processor Modes Registers General Purpose Registers Program Status Registers Exceptions Memory

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Data Types
ARM processors support following data types
Byte Halfword Word 8 bits 16 bits 32 bits

Halfwords must be aligned to two-byte boundaries Words must be aligned to four-byte boundaries

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Processor Modes
ARM supports seven processor modes
User: unprivileged mode under which most tasks run FIQ: entered when a high priority (fast) interrupt is
raised IRQ: entered when a low priority (normal) interrupt is raised

Supervisor: entered on reset and when a Software

Interrupt instruction is executed Abort: used to handle memory access violations

Undefined: used to handle undefined instructions System: privileged mode using the same registers
as user mode
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Registers
ARM processor has total 37 registers
31 general-purpose registers (32 bits wide)
Unbanked registers, R0-R7 Banked register, R8-R14 Program Counter R15

Only 16 are visible, others used for exception processing 6 status registers (32 bits wide)
Saved Program Status Register (SPCR) Current Program Status Register (CPSR)

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Register Organization

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Special Registers
Program Counter (R15)
Points to instruction which is two instructions after the instruction being executed ARM instr four bytes (32-bits) and are always word aligned Two LS Bits are always zero

Link Register (R14)

Performs two functions It holds the subroutine return address (address of the next instr after a Branch and Link instr) Each exception modes version of R14 is set to the exception return address

Stack Pointer (R13)

It is by convention only

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Program Status Register

31

28 27

24

23

16

15

N Z C V Q

I F T

mode

Condition Code Flags

N Z C V

Set to 1 when result is negative Set to 1 when result is zero Set to 1 on carry or borrow generation and on shift operations Set to 1 if signed overflow occurs
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ARM Architecture

Program Status Register

31

28 27

24

23

16

15

N Z C V Q

I F T

mode

I F

Disables IRQ interrupts when set Disables FIQ interrupts when set T=0 indicates ARM execution T=1 indicates Thumb execution
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ARM Architecture

Program Status Register

31

28 27

24

23

16

15

N Z C V Q

I F T

mode

Q Indicates occurrence of overflow and/or saturation M[4:0] 0b10000 0b10001 0b10010 0b10011 0b10111 0b11011 0b11111
ARM Architecture

Mode User FIQ IRQ Supervisor Abort Undefined System

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Exceptions
Generated to handle an event ARM supports seven types of exceptions When exception occurs execution is forced from fixed memory address known as exception vector
Exception Type Reset Undefined Instruction Mode Supervisor Undefined Normal Address 0x00000000 0x00000004 Priority 1 6

Software Interrupt Prefetch Abort Data Abort

IRQ (interrupt) FIQ (fast interrupt)
ARM Architecture

Supervisor Abort Abort

IRQ FIQ

0x00000008 0x0000000C 0x00000010

0x00000018 0x0000001C

6 5 2
4 3
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Memory
Address Space
ARM uses a single, flat address space of 232 8-bit bytes Address calculations done using ordinary integer instructions. Address wraps around if there is an overflow or underflow

No support for unaligned memory (instruction and data) accesses Memory-mapped I/O

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Endianness
Big Endian Memory System
31 15 0

Word Address at A Halfword At Address A Halfword At Address A+2

Byte at address Byte at address Byte at address Byte at address A A+1 A+2 A+3

Little Endian Memory System

31 15 0

Word Address at A Halfword At Address A+2 Halfword At Address A Byte at address Byte at address Byte at address Byte at address A+3 A+2 A+1 A

ARM has hardware input to configure the Endianness

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Conditional Execution
Almost all ARM instructions can be conditionally executed If N, Z, C and V flags in CPSR satisfy a condition then the instruction is executed or it is treated as a NOP. Value of 0b1111 in condition field is used for instructions which can be unconditionally executed 4-bit condition code field
31 28 27

cond
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Condition Codes
Suffix Description
Equal Not equal Unsigned higher or same Unsigned lower Minus

Flags tested
Z=1 Z=0 C=1 C=0 N=1

EQ NE CS/HS CC/LO MI

PL
VS VC HI LS GE LT GT LE AL

Positive or Zero
Overflow No overflow Unsigned higher Unsigned lower or same Greater or equal Less than Greater than Less than or equal Always

N=0
V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V

Example:
ARM Architecture

ADDNE

R0,R1,R2
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ARM Instruction Set

Branch Instructions Data-processing Instructions Status register transfer Instructions Load and Store Instructions Coprocessor Instructions Exception-generation Instructions

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Exception-generating Instructions
Two exception generation instructions present
The Software Interrupt (SWI) used to cause a SWI exception. By this the User mode code can make calls to privileged OS code The Breakpoint (BKPT) used for software breakpoints. It causes a Pre-fetch Abort exception to occur

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Enhanced DSP Extension

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About Enhanced DSP Extension

Applications demand for signal processing in addition to control implementation
Typical applications include speech coders, speech recognition and synthesis, networking applications, automotive control solutions, smart phones and communicators, and modems.

DSP extension introduced to implement efficient signal processing without compromising on control capabilities
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Thank You

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