Three Dimensional Integrated Circuits

C.S. Tan, A. Fan, K.N. Chen, S. Das, N. Checka and R. Reif

Microsystems Technology Laboratories M.I.T.

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

3-D Integrated Circuits (3-D IC)

A vertical stack of multiple device and interconnect layers connected together by interlayer vertical vias.

Interlayer Vertical Via

Device/Interconnect Layer

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

3-D IC with Cu-Cu Wafer Bonding

Interlayer Vertical Via
M3 M2 M1 DL2 M4 M3 M2 M1 DL1

Cu-Cu Bonding

DL Device Layer

M Metal Interconnect Layer

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

(R. Reif, MIT)

How Does 3-D Integration Help?

Greater number of nearest neighbors for a given transistor Every transistor, gate, and module has increased wiring bandwidth Interconnect distribution becomes shifted Fewer global wires, more local wires Energy consumption and cycle time reduced More effective use of Si area

(Log-Log Plot)
2-D IC 3-D IC

Wire-length

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

Digital Block Partitioning

Logic

Memory

L
Memory

<<L

Logic

<w

d
<d

2D

3D

Exploit locality to reduce interconnect lengths Reduce chip area for interconnect-dominated applications Increase density for device-dominated applications
Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003
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Mixed-Signal Partitioning

Analog

Digital

Analog

Digital

2D

3D

Mixed-technology/mixed-signal based applications Better signal isolation between analog and digital components

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

Monolithic integration of different dies

Microprocessor

Memory

RF
DSP Memory uP

DSP

RF

Board

Board

2D

3D

-Smaller form factor -Reduced power dissipation and/or energy consumption

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

3-D Approaches
Parallel fabrication, layer transfer by bonding - Dielectric : polymer, SiO2

- Metallic : Cu-Cu
Continuous layer growth/fabrication

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

Cu-Cu Wafer Bonding

Interlayer Vertical Via
M3 M2 M1 DL2 M4 M3 M2 M1 DL1

Cu-Cu Bonding

DL Device Layer

M Metal Interconnect Layer

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

(R. Reif, MIT)

Crystallization of -Si
Gate

Repeaters or optical I/O devices

n+/p+

n+/p+

VILIC
M4

M3 M2 M1 Gate

Recrystallized Si

n+/p+

n+/p+

T2 M2

Memory or Analog

M1 Gate n+/p+ n+/p+ T1

Via

Bulk Si

Logic

(K.Saraswat, Stanford)

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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3-D Research @ MIT

Process Technology Development
CAD Tool Development Applications: 3-D Circuit/System - Partitioning Digital Circuits - Partitioning Mixed-Signal Circuits - Monolithically integrating several dies

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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Process Technology Development

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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Parallel FEOL Processes on 2 Device Wafers

M1 (Al)
LOCOS/STI BOX

Device/Interconnect Layer 2 (SOI)

Cu Pad Cu Via M1 (Al) LOCOS/STI

Device/Interconnect Layer 1 (Bulk Si)

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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Cu Via and Thinning and Precision Pad formation SOIWafer alignment SOI Waferis attached bonding Viahandle etch back toSOIetch, passivation, barrier a wafer wafer
layer and fill Handle wafer provides A combination of Cu Pad for grinding, mechanical support and ease of mechanical bonding wafer handling plasma dry etch and Strong enough to withstand chemical wet etch
subsequent process Ease of release

Advantage of SOI Etch stop on BOX

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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Precision alignment and Handle Wafer Release bonding

Fast process is required toOptical alignment to the minimize damage stack Back-to-face bonding Cu to Cu Bonding Via pad is for electrical connection Dummy pad is to increase bonding strength

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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Cu Contact Bonding
SEM image SEM image

10 um contact

10 m contact

SEM image

TEM image

(K.N.Chen)
Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003
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CAD Tool Development

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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FFT Energy Consumption

27% - 40% reduction in switching energy Can obtain almost all the energy savings while maintaining cycle time

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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Future
Introduce nanotubes/nanowires
Develop active/passive interconnects (wires that process and/or transmit information) Develop insulators with high thermal conductivities (thermal profiles) Develop nano-inductors (RF applications)

Avogadro-Scale Engineering: Form and Function MIT, November 18, 19 2003

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