Programmable Interval Timer 8253

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Introduction
It generates accurate time delays under software control. Instead of setting up timing loops in system software, the programmer configures the 8253, initializes one of the counters, to count the delay and interrupt the CPU when it has completed its tasks. The software overhead is minimized Includes three identical 16-bit counters that can operate independently. Three counters are identical presettable, down counters and can be programmed for either hexadecimal count or BCD count.
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Contd..
At the end of the count, it generates a pulse that can be used to interrupt the CPU. The counter can count either in binary or BCD. It facilitates on-the -fly reading of counters. To operate a counter, a 16-bit count is loaded in its control word register and, on command, it begins to decrement the count until it reaches 0. Counter can be programmed in six different modes. Compatible with all Intel and most other microprocessors. 8253 has powerful command called READ BACK command which allows the user to check the count value, programmed mode and current mode and current status of the counter.

Architecture and Signal descriptions

It has 8-bit, bidirectional data buffer interfaces internal circuit of 8253 to microprocessor system bus. Data is transmitted or received by the buffer upon the execution of IN (reads data) or OUT(writes data to a peripheral) instruction. Read/write logic controls the direction of the data buffer depending upon whether it is read or write operation.
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Each counter has two input signals CLOCK and GATE and one output signal OUT.
CLK: The clock input is the timing source for each of the internal counters. It is often connected to the bus controller. GATE: The gate input controls the operation of the counter in some modes. OUT: A counter output where the wave-form generated by the timer is available.

Data bus buffer has three basic functions.

1. Programming the modes of 8253/54. 2. Loading the count registers. 3. Reading the count values.

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Pin Diagram

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Selection Operations for various Inputs

CS 0 0 0 0 0 0 0 0 0 1 RD 1 1 1 1 0 0 0 0 1 X WR 0 0 0 0 1 1 1 1 1 x A1 0 0 1 1 0 0 1 1 x x A0 0 1 0 1 0 1 0 1 x x selected operation write counter 0 write counter 1 write counter 2 write control word read counter 0 read counter 1 read counter 2 no operation no operation disabled

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Control Word Register

A Control Word must be written in respective Control Word Register by microprocessor to initialize each of the counters . The count is written in the counter only after the data is put on the data bus and falling edge appears at the clock. Each counter is individually programmed by writing a control word into the control word register (A0 -A1 = 11). The complete functional definition of the 8253 is programmed by the system software. Once programmed, the 8253 is ready to perform whatever timing tasks it is assigned to accomplish.

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Control Word Format

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Modes of Operation
Mode 0: Interrupt on terminal count. Mode 1: One-shot mode/ Programmable monoshot Mode 2: Rate generator or divide by N counter Mode 3: Square-wave generator Mode 4: Software triggered one-shot Mode 5: Hardware triggered one-shot

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Mode 0: Interrupt on terminal count

Generates accurate time delays. Counter is initialized by N Output of counter initially becomes low after the mode is set. Counting starts if GATE is high. While counting is going on, the OUT remains low. When terminal count is reached, the output becomes high and remains high until the count is reloaded. When counter becomes 0, it interrupts CPU.

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Mode 1: Programmable Monoshot

OUT is initially high. Low to high on GATE acts as trigger. Counter decrements the count and OUT goes low for N clock cycles for every low to high transition of GATE. OUT goes low at first negative edge of clock after rising edge of GATE input. OUT goes high on terminal count. Width of OUT can be varied by varying N If the GATE is made low to high again, counter reloads.

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Mode 2: Rate generator

When mode sets, OUT is initially high. After that the counter is loaded by N. After a low to high transition on GATE, OUT remains high for (N-1) clock pulses and goes low for one clock pulse. After this the OUT becomes high again and N is automatically reloaded. If the GATE is made low, the counter is disabled and OUT stays high. When GATE returns high, counter resumes and starts from initial count.

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Mode 3: Square-wave generator

After mode is set counter is loaded by N. GATE is kept high. For even values of N the OUT remains high for N/2 clocks and then goes low for next N/2 clocks. For odd values of N the OUT remains high for N+1/2 clocks and then goes low for next N-1/2 clocks. When GATE is made low counter is disabled and OUT stays high. On terminal count the counter is reloaded.

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Mode 4: Software triggered one-shot

After mode is set, OUT becomes initially high. GATE is kept high. Counter begins counting immediately after the count is loaded. When counter reaches terminal count, OUT goes low for one clock cycle and returns to high again. Generation of strobe signal is triggered by loading the count.

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Mode 5: Hardware triggered one-shot

After mode is set, OUT becomes initially high. GATE acts as a trigger. Counter starts decrementing on low to high transition of GATE. Counting begins at the first negative edge of the clock input after rising edge of GATE. When counter reaches terminal count, OUT goes low for one clock cycle and returns to high again. As the low to high on GATE causes triggering this mode is referred to as Hardware triggered strobe.

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THANKS

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