DSM Lecture 1

332:578 Deep Submicron
VLSI Design
Lecture 1
CMOS Transistor Theory
David Harris and Michael Bushnell
Harvey Mudd College and Rutgers University
Spring 2005
Material from: Material from: CMOS VLSI Design CMOS VLSI Design, ,
by Weste and Harris, Addison-Wesley, 2005 by Weste and Harris, Addison-Wesley, 2005
Deep Submicron VLSI Des. Lec. 1 Slide 2 07/18/12
Outline
Conventional non-deep submicron transistor

model
Adjustments to V
T
for non-ideal 2
nd
-order effects
Body Effect
Velocity Saturation
Leakage
Channel Length Modulation
Mobility Variation
Tunnelling
Punchthrough
Avalanche Breakdown
Impact Ionization
Temperature
Summary
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
<
_
<
'
,
>
Shockley 1
st
order transistor models
V
t
Dependencies
Gate material
Gate insulation material
Gate insulator thickness
Channel doping
Impurities at Si SiO
2
interface
V
sb
voltage from source to substrate
|V
t
| 1/T
-4 mV /
o
C High substrate doping
-2 mV/
o
C Low substrate doping
Non Deep-Submicron
Threshold Equations
V
t
= V
t-mos
+ V
fb
V
t-mos
= 2
b
+

b
= ln , bulk potential difference between
Fermi level of doped & intrinsic Si
C
ox
= oxide capacitance
Q
b
= bulk charge = 2
Si
q N
A
2
b
n
i
= 1.45 x 10
10
cm
-3
at 300
o
K
Q Q
b b
C C
ox ox
kT kT
q q
N N
A A
n n
i i
(
(
)
)
Ideal V
t
of
Ideal MOS
Capacitor
Flat-band voltage
point at which energy
levels go flat
Definitions
p
o
is hole concentration in semiconductor in equilibrium
p
p
is hole concentration in semiconductor p side of
junction
n
p
is e
--
concentration in semiconductor in equilibrium
n
i
is intrinsic carrier concentration in undoped
semiconductor of both holes and e
--
k is Boltzmanns constant
T is absolute temperature in degrees Kelvin

N
A
is acceptor concentration
N
D
is donor concentration

s
is dielectric constant of Si
= q / kT (reciprocal of thermal voltage)
E is the electric field

Ideal MIS Diode
E
g
2q
Type p semiconductor
At V = 0,

ms
= energy
difference between
metal & semiconductor
= semiconductor
electron affinity

ms
=
m
( + +
B
) = 0
Flat-band condition usually have to apply V

FB
(flat-band
voltage) to cause this to happen
Accumulation
p
0
= n
i
e
Energy bands when a negative voltage is applied:

(E (E
i i
E E
F F
) / kT ) / kT
Weak Inversion
Energy bands when small positive bias voltage is applied:

E
i
at surface now below E
F
by 2
B
=

B
= potential difference between E
F
and E
i
in bulk
V
T
= voltage necessary to cause strong inversion
Strong Inversion
Threshold Equations
k = Boltzmanns constant = 1.380 x 10

-23
J/
o
K
q = 1.602 x 10
-19
C (1 e
charge)
kT/q = 0.02586 V. at 300

o
K (thermal voltage)

Si
= 1.06 x 10
-12
F/cm
Intrinsic Fermi level midway between conduction & valence

bands
p Fermi level closer to valence band
n Fermi level closer to conduction band

V
fb
=
ms
-
Q
fc
= fixed charge due to imperfections in Si SiO
2
interface and
due to doping
Q Q
fc fc
C C
ox ox
Threshold Equations

ms
=
gate

Si
work function difference
between
gate material & Si substrate

ms
= - +
b
= - 0.9 V (N
A
= 1 x 10
16
cm
-3
)
E
g
= band gap energy of Si
= (1.16 0.704 x 10
-3
)
5

ms
-0.2 V (N
A
= 1 x 10
16
cm
-3
)
E E
g g
2 2
(
(
)
)
T T
2 2
T + T + 1108 1108

Adjustments to V
t
Change V
t
by:
Changing substrate doping N
A
Changing C
ox
(use a different insulator) (usual method)
Changing surface state charge Q
fc
(usual method)
Changing T (temperature)
Often use a layer of Silicon nitride Si

3
N
4

Si
3
N
4
= 7.8 on top
of SiO
2
Dual dielectric process gives combined
relative
= 6
Electrically equivalent to thinner layer of SiO
2
, higher
C
ox
MOS transistors self-isolating if regions between devices

cannot be inverted by normal circuit voltages
Example
volts
b
36 . 0
10 45 . 1
10 8 . 1
ln 02586 . 0
10
16
,
_

Calculate the native threshold voltage for an n-transistor at 300
o
K for a process
with a Si substrate with N
A
= 1.80X10
16
, a SiO
2
gate oxide with thickness 200A.
(Assume
ms
= -0.9V, Q
fc
= 0.)
o
volts
C
qN
cm Farads
t
C with
B
ox
B A Si
ms
ox
ox
ox
16 . 0 72 . 0 384 . 0 9 . 0
2
2 2
/ 10 726 . 1
10 2 . 0
10 85 . 8 9 . 3
2 7
5
14
+ +
+ +


OFF Transistor Behavior
What about current in cutoff?
Simulated results
What differs?
Current doesnt go
to 0 in cutoff
V
t
Sub-
threshold
Slope
Sub-
threshold
Region
Saturation
Region
V
ds
= 1.8
I
ds
V
gs
0 0.3 0.6 0.9 1.2 1.5 1.8
10 pA
100 pA
1 nA
10 nA
100 nA
1 A
10 A
100 A
1 mA
MOS Equations
K
p
= process-dependent gain factor = = C
ox

nbulk

pbulk

nsurface
Si 1350 450 500 Units of cm
2
/ (V sec)
Ge 3600
GaAs 5000

Si
= 4
o
= 4 x 8.854 x 10
-14
F/cm
t
ox
40
For a 0.18 m process:

Typical
n
= 155 W/L A/V
2
Typical
p
= 77.5 W/L A/V
2
t t
ox ox
A
o
Geometric MOSFET View
Spice/Spectre Models
LEVEL 1 Shockley equation + some 2

nd
-order effects
LEVEL 2 Based on device physics
LEVEL 3 Semi-empirical match equations to real circuits based

on parameters
BSIM3 v3 3.1 Berkeley empirical deep sub-micron model

Use this one all other models give incorrect results
Predict too high a V
t
Exaggerate the body effect
Incorrectly calculate leakage currents (drain induced

barrier lowering)
K
P
major Spice/Spectre parameter
77 to 155 A/V
2
, varies 10-20 % in manufacturing process
Second-Order Effects
Cannot Be Ignored
Ideal nMOS I-V Plot
180 nm TSMC process
Ideal Models
= 155(W/L) A/V
2
V
t
= 0.4 V
V
DD
= 1.8 V
I
ds
(A)
V
ds
0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
V
ds
0 0.3 0.6 0.9 1.2 1.5
V
gs
= 1.8
I
ds
(A)
0
50
100
150
200
250
V
gs
= 1.5
V
gs
= 1.2
V
gs
= 0.9
V
gs
= 0.6
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
Less ON current
No square law
Current increases
in saturation
V
ds
0 0.3 0.6 0.9 1.2 1.5
V
gs
= 1.8
I
ds
(A)
0
50
100
150
200
250
V
gs
= 1.5
V
gs
= 1.2
V
gs
= 0.9
V
gs
= 0.6
Velocity Saturation
We assumed carrier velocity is proportional to E-field

v = E
lat
= V
ds
/L
At high fields, this ceases to be true
Carriers scatter off atoms

Velocity reaches v
sat
Electrons: 6-10 x 10
6
cm/s
Holes: 4-8 x 10
6
cm/s
Better model
E
sat 0
0
slope =
E
lat
2E
sat
3E
sat
sat
sat
/ 2
lat
sat sat
lat
sat
1
E
v v E
E
E

+
Vel. Sat. I-V Effects
Ideal transistor ON current increases with V
DD
2
Velocity-saturated ON current increases with V
DD
Real transistors are partially velocity saturated
Approximate with -power law model

I
ds
V
DD
1 < < 2 determined empirically

( )
( )
2
2
ox
2 2
gs t
ds gs t
V V
W
I C V V
L

( )
ox max ds gs t
I C W V V v
Velocity Saturation
is velocity saturation index
Determined empirically by curve fitting

Long-channel or low V
DD
transistors = 2
As vel. sat. increases, approaches 1 for

complete vel. sat.
Saturation refers to transistor operating region
Velocity Saturation refers to limiting of carrier

velocity at high E field
Velocity Saturation Eqns.
P
c
and P
v
are curve fitting parameters
'
>
<
<
saturation V V I
linear V V
V
V
I
cutoff V V
I
dsat ds dsat
dsat ds
dsat
ds
dsat
t gs
ds
0
( )
( )
2
2
t gs v dsat
t gs c dsat
V V P V
V V P I

-Power Model
I
ds
(A)
V
ds
0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0
-law
Simulated
Shockley
Mobility Variation
= average carrier drift velocity (v)

Electric Field
Decreases with increasing doping and with increasing

T
is Spice parameter U0
Use BSIM to model

Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers

Width of depletion L
d
region grows with reverse bias
L
eff
= L L
d
Shorter L
eff
gives more current
I
ds
increases with V
ds
Even in saturation
n+
p
Gate Source Drain
bulk Si
n+
V
DD
GND
V
DD
GND
L
L
eff
Depletion Region
Width: L
d
Chan. Length Mod. I-V
= channel length modulation coefficient
not feature size
Empirically fit to I-V characteristics

( )
( )
2
1
2
ds gs t ds
I V V V
+
I
ds
(A)
V
ds
0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0
Channel length changes for short channels as V
ds
changes
Must now be modeled

Effective channel length: L
eff
= L L
short
L
short
= 2
Si
(V
ds
(V
gs
V
t
))
q N
A
Shorter length increases W/L ratio, increases as V
d
increases
Gives a finite output impedance, not a pure current source
More accurate model (which we must use):
I
ds
= K
P
W (V
gs
V
t
)
2
(1 + V
ds
)
2 L
= channel length modulation factor (Spice parameter LAMBDA)
L
W
K
P

Becomes relatively more important as channels

shorten
inversely dependent on channel length
Important for analog VLSI reduces amplifier gain

Body Effect
V
t
: gate voltage necessary to invert channel
Increases if source voltage increases because source is

connected to the channel
Increase in V
t
with V
sb
is called the body effect
Series devices V
sb
increases as we proceed along series
chain
Result: Channel-substrate depletion layer width increases
Result Increased density of trapped carriers in depletion

layer
For charge neutrality to hold, channel charge must

decrease
Result: V
sb
adds to channel-substrate junction potential,
gate-channel voltage drop increases, effectively get a
higher V
t
Body Effect
Body Effect Model
V
t0
Threshold voltage when V
sb
= 0
V
t
= V
fb
+ 2
b
+ 2
Si
q N
A
(2
b
+ |V
sb
|)
C
ox
= V
t0
+ [ (2
b
+ |V
sb
|) -- 2
b
]
0.4 1.0
= t
ox
2 q
Si
N
A
= 1 2 q
Si
N
A

ox
C
ox
Equivalent SPICE parameters: GAMMA, VT0
NSUB is N
A
, PHI is
s
= 2
b
(surface potential at onset of
strong inversion, i.e., V
t
)
= body effect coefficient

Body Effect
Surface potential:
Is the thermal voltage
T
i
A
T s
v
n
N
v ln 2
Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Junction leakage
Reverse-biased pn junction diode current
Gate leakage
Tunneling through ultra thin gate dielectric
Subthreshold leakage is the biggest source in modern

transistors
Subthreshold Leakage
Subthreshold leakage exponential with V
gs
and V
ds
n is process dependent, typically 1.4-1.5
Affects dynamic storage memory cells
Determined empirically
Use BSIM to model

Increases exponential as V
t
decreases or T rises
0
e 1 e
gs t
ds
T T
V V
V
nv v
ds ds
I I

_

,
2 1.8
0
e
ds T
I v
DIBL
Drain-Induced Barrier Lowering

Drain voltage also affects V
t
High drain voltage causes subthreshold leakage to

________.

is DIBL constant
Bowman extended -power low model to physical

-power law, that included subthreshold
conduction and velocity saturation
ttdsVVV
t t ds
V V V

1 . 0 02 . 0 < <
DIBL
Drain-Induced Barrier Lowering

Drain voltage also affects V
t
High drain voltage causes subthreshold leakage to

________.

is DIBL constant
Bowman extended -power law model to physical

-power law, that included subthreshold
conduction and velocity saturation
ttdsVVV
t t ds
V V V

1 . 0 02 . 0 < <
increase
Junction Leakage
Reverse-biased p-n junctions have some leakage

I
s
depends on doping levels
And area and perimeter of diffusion regions
Typically < 0.1 fA/m

2
e 1
D
T
V
v
D S
I I
_

,
n well
n+ n+ n+ p+ p+ p+
p substrate
Gate Leakage
Carriers may tunnel

thorough very thin
gate oxides
Predicted tunneling
current (from
[Song01])
Negligible for older

processes
May soon be critically

important
10 X higher for nMOS

than for pMOS
V
DD
0 0.3 0.6 0.9 1.2 1.5 1.8
J
G

(
A
/
c
m
2
)
10
-9
10
-6
10
-3
10
0
10
3
10
6
10
9
t
ox
0.6 nm
0.8 nm
1.0 nm
1.2 nm
1.5 nm
1.9 nm
V
DD
trend
Fowler-Nordheim Tunneling
For very thin gate oxides,
Current flows from gate to source or gate to drain

by e
--
tunneling through SiO
2
Exploit in High Electron Mobility Transistor (HEMT)

I
FN
= C
1
W L E
ox
2
e
E
ox
= V
gs
, Electric field across gate oxide
t
ox
E
0
, C
1
are constants
Limits oxide thickness as processes are scaled used

in making EPROMS
-E -E
0 0
E E
ox ox
Drain Punchthrough
Drain depletion region extends to source at high

voltages
Lose gate control of transistor
Used in pin I/O (pad) circuits to make Zener diodes
Forces voltages to be scaled down as device sizes

are scaled down
pMOSFET Punchthrough
Avalanche breakdown for very high V
ds
gate has no
control over I
ds
Impact Ionization Hot e
--
For submicron gate lengths << 1 m, a major problem
e
--
get so much energy that they impact the drain, and
dislodge holes, which are swept toward the grounded
substrate
Creates a substrate current
e
--
may penetrate the gate oxide and cause gate
current
Degrades V
t
, subthreshold current,
Causes circuit failure
Poor DRAM refresh times, noise in mixed analog-

digital circuits, latchup
Hot holes are too slow to cause trouble

Impact Ionization Fixes
Solve with lightly-doped drains

Drop V
DD
to 3 V. or lower
I
substrate
= I
ds
C1 (V
ds
V
dsat
)
C2
C1 = 2.24 X 10
-5
0.1 X 10
-5
V
ds
C2 = 6.4
V
dsat
= V
tm
L
eff
E
sat
V
tm
+ L
eff
E
sat
V
tm
= V
gs
V
tn
0.13 V
bs
- 0.25 V
gs
E
sat
= 1.10 X 10
7
+ 0.25 X 10
7
V
gs
Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces V
t
I
ON
___________ with temperature
I
OFF
is room temperature
is a fitting parameter
( ) ( )

k
T
T
T
T T
r
k
r
r
,
_

Reduces mobility
Reduces V
t
I
ON
I
OFF
is room temperature
( ) ( )

k
T
T
T
T T
r
k
r
r
,
_
decreases
Reduces mobility
Reduces V
t
I
ON
I
OFF
is room temperature
( ) ( )

k
T
T
T
T T
r
k
r
r
,
_
decreases
increases
Negative Temp. Coefficient
in Saturation
I
dsat
vs. Temperature
Benefits of Cooling
Cooling methods:
Natural convection
Fans and heat sinks
Water cooling
Thin-film refrigerators
Liquid nitrogen cooling
Benefits of lower T operation:

Lower threshold voltages
Higher velocity saturation
Higher mobility
Power savings
Wider depletion regions (less junction C)
Reduced transistor wearout methods (more reliability)
Problem of lower T: Lower breakdown V

Spice Model Parameters
Also must use process parameters in LEVEL III model to

calculate VT0, KP, GAMMA, PHI, and LAMBDA
See Section 5.3 in book

Parameter nMOS pMOS Units Description
VT0 0.7 0.7 Volt Threshold voltage
KP 8X10
-5
2.5X10
-5
A/V
2
Transconductance coefficient
GAMMA 0.4 0.5 V
0.5
Bulk threshold parameter
PHI 0.37 0.36 Volt Surface potential at strong
inversion
LAMBDA 0.01 0.01 Volt
-1
Channel length modulation
parameter
LD 0.1X10
-6
0.1X10
-6
meter Lateral diffusion
TOX 2x10
-8
2x10
-8
meter Oxide thickness
NSUB 2x10
16
4x10
16
1/cm
3
Substrate doping density
So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation
Modeling Consequences
Pass transistors suffer threshold drop when passing the wrong

value
Do not operate well now, where V
t
is significant fraction of
V
DD
Use fully complementary transmission gates

Use combination of low V
t
and high V
t
devices in same process
to control leakage with high V
t
devices
Tunneling is becoming a problem

V
DD
is dropping because velocity saturation and degradation
give less current at high V
DD
Series transistors have less velocity saturation than single

transistors, so they are faster than predicted by simple model
Particularly nMOSFETs
Summary
Current Characteristics of MOSFET

Calculation of V
t
and

Important 2
nd
-Order Effects
Models in this lecture
For pedagogical purposes only
Obsolete for deep-submicron technology
Real transistor parameter differences:
Much higher transistor current leakage
Body effect less significant than predicted

V
t
is lower than predicted

DSM Lecture 1

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332:578 Deep Submicron

Conventional non-deep submicron transistor

Gate insulation material

Gate insulator thickness

T is absolute temperature in degrees Kelvin

= q / kT (reciprocal of thermal voltage)

E is the electric field

Flat-band condition usually have to apply V

Energy bands when a negative voltage is applied:

Energy bands when small positive bias voltage is applied:

k = Boltzmanns constant = 1.380 x 10

kT/q = 0.02586 V. at 300

Intrinsic Fermi level midway between conduction & valence

p Fermi level closer to valence band

n Fermi level closer to conduction band

Often use a layer of Silicon nitride Si

MOS transistors self-isolating if regions between devices

Deep Submicron VLSI Des. Lec. 1 Slide 15 07/18/12

What about current in cutoff?

For a 0.18 m process:

LEVEL 1 Shockley equation + some 2

LEVEL 2 Based on device physics

LEVEL 3 Semi-empirical match equations to real circuits based

BSIM3 v3 3.1 Berkeley empirical deep sub-micron model

Exaggerate the body effect

Incorrectly calculate leakage currents (drain induced

180 nm TSMC process

180 nm TSMC process

BSIM 3v3 SPICE models

180 nm TSMC process

BSIM 3v3 SPICE models

We assumed carrier velocity is proportional to E-field

At high fields, this ceases to be true

Carriers scatter off atoms

Real transistors are partially velocity saturated

Approximate with -power law model

1 < < 2 determined empirically

is velocity saturation index

Determined empirically by curve fitting

As vel. sat. increases, approaches 1 for

Saturation refers to transistor operating region

Velocity Saturation refers to limiting of carrier

= average carrier drift velocity (v)

Decreases with increasing doping and with increasing

Use BSIM to model

Reverse-biased p-n junctions form a depletion region

Region between n and p with no carriers

= channel length modulation coefficient

not feature size

Empirically fit to I-V characteristics

Must now be modeled

Becomes relatively more important as channels

inversely dependent on channel length

Important for analog VLSI reduces amplifier gain

Increases if source voltage increases because source is

Result: Channel-substrate depletion layer width increases

Result Increased density of trapped carriers in depletion

For charge neutrality to hold, channel charge must

Transistors cant abruptly turn ON or OFF

Reverse-biased pn junction diode current

Tunneling through ultra thin gate dielectric

Subthreshold leakage is the biggest source in modern

n is process dependent, typically 1.4-1.5