DIGITAL ELECTRONICS LABORATORY List of Experiments:

1. Outline of digital Integrated Circuits (ICs) 2. AND, OR and NOT gate 3. NAND, NOR and EXCLUSIVE-OR gate 4. Boolean Algebra and Combinational Logic Design 5. Half Adder and Full Adder 6. Decoder/Encoder and Multiplexer/De-multiplexer 7. Parity Generator and Parity checker 8. Flip-Flip and Latch 9. Composition of register 10. Asynchronous Counter 11. Synchronous counter 12.(a) Clock Generator (b) A/D Converter

Grading:
Attendance; 20% Lab. Work: 20% Report: 20% Mid-semester Exam: 20% Final Exam: 20%

OUTLINE OF DIGITAL INTEGRATED CIRCUITS (ICs) Aim: To study the digital ICs outline and electrical parameters.

Components Required: Various types of ICs say Transistor - Transistor Logic (TTL) and Complementary Metal Oxide Semiconductor (CMOS) ICs. Description: All digital ICs operate with 5V DC power supply. The number of external pin connection varies with a minimum number of pins as 14. The pins are numbered in anti clockwise starting pin 1 from the marking dot or grove. It is a dual-in-line (DIP) package. Normally all ICs operate in dual state High (1) and Low (0). TTL devices are also available in open collector form. These devices have more drive current. These devices operate in TRISTATE (High, Low and High Impedance State) Electrical Characteristics: Parameter Supply Voltage Power Dissipation Propagation Delay Fan Out Operating Frequency TTL 5VDC 10mW 10nSec 25 30MHz CMOS 3-16VDC < 1mW 100nSec 20 5MHz

Propagation Delay: This is the time taken for the signal to reach the output on applying steady state input. Fan-in: This indicates how many input terminals are connected to a gate. It is normally less than or equal to 15 for a TTL gate Fan Out: It is the output drive that a device can support with out over load.. It is less than or equal to 25 for a TTL gate. Conclusion: The digital ICs Physical & Electrical Characteristics are studied.

AND OR & NOT Gate AIM: To study the logics of AND OR and NOT gates.

Equipments Required: Oscilloscope, Power Supply, Single Pole Double Throw (SPDT) Switch, Diodes, NPN Transistor, Resistors, 7408 (Quad two input AND gate), 7432 (Quad two input OR gate), 7404 (Hex Inverter), LED etc. Description: A logic gate is an electronic circuit, which takes one or more inputs and produces a single output. The possible combinations of the inputs and the corresponding outputs are tabulated in the truth tables for verification. All the digital logics under discussion use Positive logic (High/ True= 1 and Low/ False= 0). The AND, OR and NOT gates are basic gates while NAND, NOR gates are universal gates. The NAND and NOR gates are sufficient enough to build all other gates. (a) AND Gate: The logic of an AND gate is that it produces a High (1) output only if all its inputs are High (1) and produces Low (0) output if any of its inputs are Low (0). The AND gate is realized by the Boolean Expression Y = A.B This can be implemented using diodes as shown in Fig.1
A Y B 1K

+
Fig. 1

-5V

The AND gate is symbolic representation is given in Fig.2. The Truth Table of AND gate is verified using IC 7408 and the same is listed.
A B Fig . 2

Input
Y

B 0 0 1 1

A 0 1 0 1

Output Y 0 0 0 1

(b) OR Gate: The logic of an OR gate is that it accepts one or more inputs and produces a single output which will be High if one or more inputs are High. The gate can be realized by the Boolean expression Y=A+B This can be implemented using diodes as shown in Fig.3.
3

A Y B 1K

- 5V
+
Fig. 3

The logic symbol is given in Fig.4. The truth table of OR gate is verified using 7432 and the same is listed. Input Output B A Y A Y 0 0 0 B 0 1 1 1 0 1 Fig. 4 1 1 1 (c) NOT Gate (INVERTOR) The logic of NOT gate is that it produces the complement of the input. It has single input and single output. The Boolean expression for NOT is
Y=A

That is if the input is A then the output is as given in Fig.5

. The gate may be realized using a transistor

+5V DC 1 k

100 k

Fig. 5

The symbolic representation of NOT is as given in Fig.6 and the truth table is verified using IC 7404. Input Output A Y A Y 0 1 A 1 0 Conclusion: The logics AND, OR and NOT are constructed and their truth tables are verified.

NAND, NOR and EXCLUSIVE-OR Gate AIM: To study the logics of NAND, NOR and EXCLUSIVE-OR gates. EQUIPMENTS REQUIRED: DC Power supply, oscilloscope, SPDT Switch, NAND gate 74LS00, NOR gate 74LS02, and EXCLUSIVE-OR 74LS86, LED etc. DESCRIPTION: (a) NAND gate: It provides the complementary output of AND gate. The equivalent circuit of NAND is as given in Fig.1. That is AND gate followed by NOT gate.

A B AND + NOT

A B

Y = A.B

The Truth table of NAND gate is verified using the IC 74LS00. Input B A 0 0 0 1 1 0 1 1 Output Y 1 1 1 0

(b) NOR gate: It produces the complementary output of OR gate. The equivalent circuit is given in Fig.2 which is OR gate followed NOT gate,
A B OR + NOT Y A B Y = A+B

The Boolean expression for NOR (74LS02) gate is Y = A + B and the truth table is listed. Input B A 0 0 0 1 1 0 1 1 Output Y 1 0 0 0

(c) EXCLUSIVE-OR gate: The output of EXCLUSIVE-OR is High only if any one of the inputs is High. The output will be Low if both the inputs are LOW or HIGH. The exclusive-OR gate may be realized either using NAND gate or NOR gate as given in Fig.3 (a) and Fig.3 (b).

A+B A A B Y

Y B

(a)

A A B Y

Y B

(b) Fig.3

The truth table of EXCLUSIVE-OR is verified using IC 74LS86 and the same is listed.

Input B A 0 0 0 1 1 0 1 1

Output Y 0 1 1 0

CONCLUSION: The logics of NAND, NOR and EXCLUSIVE-OR are studied and their truth tables are verified.

BOOLEAN ALGEBRA AND COMBINATIONAL LOGIC

Aim: To understand the operations of Boolean algebra and use this to build combinational logic with minimum hardware. Requirements: AND, OR, INVERTER (NOT) gates, oscilloscope, DC power supply, LED etc. Description: BOOLEAN ALGEBRA: It is a technique of mathematical manipulation, using the binary numbers 0 and 1. It is widely used while designing digital circuits.

BOOLEAN POSTULATES: If X= 0, then X =1 0x0=0 1x1=1 1+1=1 1x0=0x1=0 1+0=0+1=1 1 = 0; 0 = 1 THEOREMS OF BOOLEAN ALGEBRA Boolean algebra deals with logical relation between Boolean variables. A fundamental rule relating Boolean variables is called a Boolean theorem. 1. Commutative law: X+Y=Y+X X x Y = Y x X. 2. Associative law: (X+Y)+Z=X+(Y+Z) (XxY)xZ=Xx(YxZ) 3. Distributive law: X x (Y + Z) = (X x Y) + (X x Z) X + (Y x Z) = (X + Y) x (X + Z) DMorgans Theorem: Statement: The complement of a product is equal to sum of the complements and the complement of a sum is equal to product of the complements. X xY = Y + X X + Y = X xY COMBINATIONAL LOGIC DESIGN: Here, we want to simplify the given Boolean expression and realize using logic gates. Let us consider a sum of product Y= A B C +A B C+ABC To implement this logic we need Inverters (NOT), AND and OR gates. Its implementation is given in Fig.1

ABC A B C ABC ABC Y

Fig. 1

Simplification of combinational logic: Consider an expression Y=AB+A B C + A B C Y = A B + A C ( B +B ) Y= A B + A C Now, after simplifying the equation, we need two NOT gates, two AND gates and one OR gate other wise we need to use three NOT gates three AND gates and two OR gates for the same function. Thus using Boolean algebra, we can minimize the hardware requirements. This is shown in the Fig.2
AB

A A.B.C Y A.B.C

A B

Fig.2 (a) Fig.2 (b) Y=AB+A B C + A B C Y= A B + A C Now connect the circuit as shown in Fig.2. (a). Note down the outputs for all the possible combinations of inputs. Repeat the same for Fig.2. (b). FIG.2(a) Y A 0 1 0 FIG.2(b) Y

Input C 0 0 0 B 0 0 1

0 1 1 1 1 Conclusion:

1 0 0 1 1

1 0 1 0 1

Boolean algebra is used to build combinational logic with minimum hardware to realize the same function.

HALF ADDER & FULL ADDER

Aim: construct and verify the operation of binary half adder and full adder Requirements: EX-OR, OR, AND gates, oscilloscope, DC power supply etc. Description: There are two types of Adders namely HALF ADDER and FULL ADDER. Let us see the details of hardware and operation in detail. HALF ADDER:

10

Half Adder performs the addition of two binary digits. The Sum in a half adder is provided by an EX-OR gate, while the Carry is provided by the AND gate as shown in Fig.1
A B S

Fig. 1
The truth table is given and the same is verified. ______________________________________________ INPUT SUM CARRY B A (S) (CY) ______________________________________________ 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 ______________________________________________ If we look the truth table closely, the SUM follows truth table of EX-OR and Carry follows AND gate truth table. Hence we need one EX-OR (74LS86) and one AND gate (74LS08) to realize Half Adder. FULL ADDER: Here, if the inputs are more than two, then we need to go for Full Adder. A block diagram sing two half adder is shown in Fig.2. The same can be realized using hardware as given in Fig.3. Here there are three inputs (A, B, C) which in turn produces two outputs (S. CY). The hardware requirements are two EX-OR gates, two AND gates and one OR gates. The truth table is given and the same is verified.
A B

HALF ADDER

HALF ADDER

S CY

C Fig. 2

11

A B S

CY

Fig. 3

Truth Table: ____________________________________________ C B A SUM (S) CARRY (CY) ____________________________________________ 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 ____________________________________________ Conclusion: Half Adder and Full Adder are realized using hardware and their operations are verified.

PARITY GENERATOR AND CHECKER

Aim: To understand and design of Parity generator and checker used in data communication. Requirement: EX-OR, Oscilloscope, DC power supply etc. Description: Parity generator and checker are used in data communication. A parity bit is used for the purpose of detecting errors during transmission of binary transmission. A parity bit is an extra bit included with the message to make the number of 1s either even or odd. The message including the parity bit is transmitted and checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the transmitted one. The circuit that generates the parity bit at the
12

transmitter is the parity generator and the circuit that checks the parity t the receiver is called the parity checker. There are two types of parity bit. Odd Parity Even Parity

Odd Parity: Odd parity is to see that the total number of 1s in the word is ODD including the parity bit. Even Parity: Even parity is to see that the total number of 1s in the word is EVEN including the parity bit. Procedure: Consider a message to be transmitted with an Even Parity. Let A, B and C is input to the Parity generator circuit shown in Fig.1. The EX-OR gate generates 1 if the odd number of inputs is 1 and a 0 if even number of inputs is 1. Hence EX-OR gate output is suitable to generate even parity. Connect the even Parity generator and verify the truth table.

A B C Fig. 1

Truth Table: __________________________________ C B A Parity (P) __________________________________ 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 _________________________________

13

Parity Checking: Message bits along with the parity (3+1) is transmitted to the destination and applied to the parity checker for possible channel error during transmission. Since the information was transmitted with an even parity, the 4 bits must have an even parity of 1s.An error is said to have occurred during transmission if the four bits received have an odd number of 1s indicating that one bit has changed its value. The output of the parity checker denoted by CK is 1 if there is an error. Parity checker circuit is as shown in Fig.2.Connect the circuit using three Ex-OR gates. Verify the truth table as listed

A B CK C P Fig. 2

Even Parity Checker Truth Table: C 0 0 0 0 0 0 B 0 0 0 0 1 1 A 0 0 1 1 0 0 P 0 1 0 1 0 1 Parity Checker (CK) 0 1 1 0 1 0

14

0 0 1 1 1 1 1 1 1 1

1 1 0 0 0 0 1 1 1 1

1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1

0 1 1 0 0 1 0 1 1 0

Conclusion: An even parity generator and checker is designed and verified.

MULTIPLEXER AND DE-MULTIPLEXER

Aim: To understand and design digital Multiplexer and De-multiplexer. Requirements: AND, OR, NOT gates, LEDs, DC Power supply etc. Description: Multiplexer and De-multiplexers are widely used to transmit and receive digital data over a communication channel. Multiplexer: Multiplexing means transmitting a large number of information units over a communication channel. A digital multiplexer is a combinational logic circuit that selects information (data ) from one of the many input lines and direct them to a single output line called a channel. The selection of a particular input line is controlled by a set of selection lines. There are TWO BINARY input lines to select four lines as shown in the Fig.1. This gives 4 to 1 line multiplexer. Here it is necessary to use AND, OR and NOT gates in addition to resistor and LEDs. The
15

LEDs are useful as indicator to see which line has been selected. The truth table may be verified.

Truth Table: _________________________ Data Selection output _______________ B A __________________________ 0 0 D 0 1 D 1 0 D 1 1 D _________________________

DEMULTIPLEXER: It is a circuit that receives information on a single line (channel) and sends this information on one of the possible output lines. The selection of a specific line is controlled by the input binary value. A de-multiplexer is the reverse action of multiplexer. It is used to convert serial data into parallel. The conversion may enabled/disabled by setting 0 or 1. When the data selection is disabled (0) the De-multiplexer will not select any data line. The circuit diagram of de-multiplexer is given in Fig.2.

16

The truth table of de-multiplexer is given here for verification. ___________________________________________________ input Enable/ output Disable ________________________________________________ B A 1/0 y y y y ________________________________________________ 0 0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 0 0 X X 0 X X X X ________________________________________________ Conclusion: Multiplexer and De-multiplexer are designed and verified using their truth table.

ENCODER AND DECODER

Aim: To understand the working principle and design encoder and decoder Requirements: AND, OR, NOT gates, DC power supply, LEDs etc. Description: Encoders and Decoders are widely used in digital systems. Let us first briefly see about encoder. ENCODER: Encoder: It is used to encode decimal number into binary or some other code say BCD. Here let us discuss an encoder, which converts Decimal to Binary number. It has 2 inputs and n output lines. Here only one input should be present at a time to get the corresponding binary output. If more than one input is present the output goes to an undefined state. Io over come this problem it is advisable to use priority encoder. The circuit diagram of encoder is given in Fig.1. The truth table is given for verification.

17

D0

D0

D1 220 D2

D3 220

Fig. 1

Truth Table Input

D3 0 0 0 1 D2 0 0 1 0 D1 0 1 0 0 D0 1 0 0 0 B 0 0 1 1

output
A 0 1 0 1

PRIORITY ENCODER: Here many devices want to communicate simultaneously then, which data is to be taken first results in priority. Here we need to encode decimal to binary and also need to give priority. The highest decimal is given top priority whereas the lowest decimal (0) gets least priority. Accordingly a priority encoder is described. Here the highest number (D) gets the top priority and the lowest number D gets the least priority while encoding, when many devices are ready to transfer data. A priority encoder circuit is sown in Fig.2. The input data lines are D to D. There are three output lines namely A, B, and Y. The bits A and B indicate the data selection and Y indicates High (1) if one or more inputs are High. The Boolean expressions for the outputs of priority encoder are A= D3+D 1D2 B= D2+D3 Y=D0+D1+D2+D3

18

D3

D2

D1 B

D0 220

Fig. 2

The truth table of the priority encoder is given in the Table

Input
D3 0 0 0 0 1 1 0 0 0 D2 0 0 0 1 0 1 1 0 0 D1 0 0 1 0 0 1 1 1 0 D0 0 1 0 0 0 1 1 1 1 B 0 0 0 1 1 1 1 0 0

Output
A 0 0 1 0 1 1 0 1 0 Y 0 1 1 1 1 1 1 1 1

DECODER: A decoder is a combinational logic circuit that converts binary into decimal number. It is also known as decimal converter. Here two to four line decoders is discussed. The input lines are A and B. Depending on the inputs one of the four output lines go high at a time. The decoder can be extended to any number of input lines. Here two to four lines are shown in the Fig.3 for simplicity. Other type of decoders is not covered here.

19

A D0 220

D1 B 220

D2 220

D3 220

Fig. 3

Truth Table: Input B 0 0 1 1 A 0 1 0 1 D3 0 0 0 1 D2 0 0 1 0 Output D1 0 1 0 0 D0 1 0 0 0

Conclusion: Design and implementation of encoder and decoder are studied

RS FLIP FLOPS
Aim: To design, understand and test RS Flip Flop with and without clock Requirements: NAND gate, function generator, oscilloscope, DC Power supply etc. Study of Flip Flop: A Flip Flop is a bi-stable multivibrator, which is capable of storing one bit information. A flip flop has two outputs, one for normal value and the other for complement value. The input to multi vibrator can be fed in a number of ways and
20

this fact gives rise to different types of flip flops. However there are two characteristics shared by all flip flops. (1) The flip flop is a bistable device that can store binary bit information. The output level will remain constant until input condition remains same. (2) The flip has two output levels which is complement of each other. RS FLIP FLOP: It can be realized using either NAND or NOR gates. The gates are cross coupled which give a feedback to the input from the output. The flip-flop has two inputs R and S, i.e., Reset (R) and Set (S) and two outputs Q and Q . RS FLIP FLOP using NAND Gates: The RS FLIP FLOP circuit is as shown in Fig.1. The NAND gate output goes high when any one of its input is low. To start with when the power is on to the gate let Q = 0 and Q =1. 1. When R=0 and S=0, the NAND gate outputs go High. This is an undefined condition and it is not used. 2. When R=0 and S=1, gate 1 of NAND output is SET to High and hence Q=1. This Q goes as one input to NAND gate 2 and the other input S=1. The output of gate 2 Q is 0 ( Q =0). 3. When R=1 and S=0, the NAND gate 2 gets 0 as input and the output of this gate is 1. The inputs to the NAND gate are 1 and the output goes to Low (Q=0). Thus, when the reset input is High the flip-flop is reset to Low (Q=0). 4. When R=1 and S=1. The gate 1 and gate 2 checks their respective second input and produces output as per the NAND gate truth table. If Q =0, then its inputs are High. NAND 2 produces a High output as S = 1 and the other input Q = 0. Thus it remains unchanged.

S
Fig.1 Truth Table --------------------------------------R S Q -------------------------------------0 0 not used 0 1 1 1 0 0 1 1 Q1 _________________________

21

CLOCKED RS FLIP FLOP: In this type, the flip flop operates only when both the clock input and RS flip flop inputs are present simultaneously. The circuit diagram is given in Fig.2. The clock is NAND-ed with R and S inputs as shown. The NAND gate responds when both the inputs are High and hence any change can occur when the clock is High along with other input i.e. R or S. The operation of RS flip-flop with the clock level remains same as previous one.

CLOCK Q

R
Fig.2

Conclusion: The RS flip flop operation is studied in detail with and without clock. Review questions: (1) What is a Flip-Flop ? (2) How does Flip-Flop act as a memory element?

22

JK FLIP FLOP Aim: To understand the principle of operation and test to JK Flip Flop operation. Requirements: NAND, AND Gates, function generator, oscilloscope, DC power supply etc. Procedure: The JK flip Flop has two inputs apart from the clock input. It can be realized using clocked RS Flip Flop. Here the state of the Flip Flop is determined by the clock inputs and the previous state outputs. JK Flip Flop using NAND gate is shown in Fig.1. Consider a clocked RS Flip Flop circuit. The circuit is enabled when the clock is high.

23

gate1 K Q

clock

Q J gate2 Fig.1

(1) When J=0, K=0: The output of AND gate 1 and 2 is Zero and hence the state of the Flop Flop remains unchanged since S=0 and R=0. (2) When J=1, K=0: Here the output of AND gate 2 is Zero and the output of the AND gate 1 is 0 or 1 depending on whether Q is 0 or 1. If Q=0, the state of the Flip Flop is unchanged. If Q=1, the output of AND gate 1 is 1 and hence S=0 and R=1 which resets the Flip Flop. (3) When J=0, K=1: Here the output of the AND gate 1 is 0 and AND gate 2 is 0 or 1 depending on the state of Q . If Q is 0 then S=0, R=0 and the output is unchanged. On the other hand if Q = 1, then the output of
AND gate 2 is goes to 1 and the Flip Flop is set to 1 since S=1 and R=0. (4) When J = 1, K = 1: Here the AND gate outputs depend on the state of Q and

Q . If Q = 0 the output of AND gate 1 is 0.and AND gate 2 is 1. Hence the Flip Flop is set to 1. If Q =1 the AND gate 1 gives 1 and AND gate 2 is 0 thereby resets the Flip Flop. Thus it is clear that the output gets complemented when both the inputs are High. This condition is defined as TOGGLE CONDITION. The measurements are tabulated. ---------------------------------------J K Q Q ---------------------------------------0 1 0 0 0 1 Q 0 1 Q 1 0

24

----------------------------------------Conclusion: The JK Flip Flop is designed and tested.

DELAY Flip Flop Aim: To construct and study the operation of Delay (D) Flip Flop Requirements: AND, NOT, NAND gates, Function generator, DC power supply etc. Description: Flip Flop output changes when both R and S inputs are dissimilar. Here the output with an inverter (NOT) serves as S and R inputs. This resulted in a D Flip Flop, which has one input and the data at the input is transferred to the output after receiving the clock pulse. Since the clock pulse delays the data transfer, the Flip Flop is known as D Flip Flop. The D Flip Flop circuit diagram is as given in Fig.1.

25

This Flip Flop is realized using RS Flip Flop with an inverter in between R and S. The output goes directly to S input and the complement to R input. When the clock input is low the Flip Flop remains disabled. When the clock is high, the data at the D=S is transferred to the output. 1. When =D=0, S=0 and R=1, the output at Q=0. 2. When =D=1, S=1 and R=0, the output at Q=1. Thus it is clear that the data is transferred to the output only when the goes high. Truth Table ------------------------------------------------------Clk =D S R Q Low X X X X High 1 1 0 1 High 0 0 1 0 -----------------------------------------------------------Conclusion: The D Flip Flop is constructed and its operation is verified.

MONOSTABLE MULTIVIBRATOR Aim: To study the monostable multivibrator circuit using IC74121. Components Required: IC 74121, resistors, capacitances, DC power supply etc. Introduction: Multivibrators are used to generate pulse waveforms of different duration and repletion rate. A multivibrator has two states. If both the states of a multivibrator circuit are stable, the circuit, which is in a particular state, continues to remain in that state until some thing is done (triggered) from an external source. This type of circuit is known as bi-stable multivibrator, FLIPFLOPs are said to be BISTALE MULTIVIBRATOR circuits. If one of the states is stable and the other is not stable (quasi-stable), the circuit is known as Monostable Multivibator or One-Shot Multivibrator. If both the states are quasi-stable, it becomes Astable Multivibrator. Monostable multivibrators are used to set the timing of an event or control a sequence of events in a digital system. It is essentially a FLIP-FLOP with only one state is stable state. A trigger pulse initiates the one shot action and generates a pulse of desired width. If additional triggers are applied to a one shot when it is in the quasi-stable state, they are ineffective unless the one shot is re-triggerable. The duty cycle of non-triggerable one shot is limited, where as re-triggerable one-shot have unlimited duty cycle. The non-triggerable one shot needs time to recover after it returns to the stable state subsequent to a triggering event. Therefore trigger pulses should not be applied so often to cause the ON time of the one shot to exceed the duty cycle specified by the manufacturers. The duty cycle of a repetitive pulse waveform is defined as percent duty cycle i.e.

26

Ton

Toff

Input

Output
Q 1 1 1 1

A1 A2 B Q T (P rio ) e d 0 X 1 0 X 0 1 0 Ton 0 0X 100 Percent DutyX Cycle =X 1 1 (Ton + Toff )1 X 1 1 1 1 Procedure: 1 The functional diagram and functional table of 0 X X 0 most popular and commonly used one-shot TTL

IC-74121 are given inFig.1 (a) and (b) respectively. In order to trigger the one-shot, there must be a rising pulse-edge at Z. This is possible in one of the following two ways: (i) One or both of the A inputs are at logic 0 and the B input goes to logic 1. (ii) The B input is at logic 1 and one of the A inputs goes to logic 0 while the other A input remains at logic 1 or both the A inputs go to logic 0 simultaneously.
+5V R 11 A1 A2 Q C 10

+Vcc

GND

Fig.1 (a)

Fig.1 (b)

The duration of the output pulse is determined by the timing resistor and capacitor connected to it. The timing capacitor should be connected between pins 10 and 11. For connecting the timing resistors, there are two options: (i) to connect the pin 9 to Vcc, by which an internal timing resistor of 2K becomes effective , or (ii) to connect an external timing resistor between pin 11 and Vcc in which case the pin 9 must be left open. The timing resistor must be in the range of 1.4 K and 40 K . The maximum allowable value of the timing capacitor is 1000 F. The duration of the output pulse in seconds is given by T ON = 0.7.R.C Where R and C are the timing resistor and capacitor in Ohms and Farads respectively. The maximum allowable duty cycle for IC 74121 is 67 % with the internal timing resistor and goes up to 90 % with external timing resistor of 40K. The monostable multi-vibrator input output waveform is shown in Fig.2

27

Clock Ton Q output

Clock Ton Q output

Fig.2 Conclusion: The monostable multivibrator is designed and tested successfully.

ASTABLE MULTIVIBRATOR
Aim: To study the astable multivibrator circuit using IC gates Components Required: NAND gate, resistors, capacitors, breadboard, DC power Supply etc. Procedure: An astable multivibrator (also known as free-running multivibrator) is an oscillator, which generates square waves. These are required to control the timings in digital circuits. These circuits can be designed using discrete devices, OPAMPs, gates or monostable multivibrators. Here let us design a multivbrator in detail using NAND gates. Astable multivibrator circuit is as shown in the figure 1. The value of resistance R is set to 330 and the capacitance C = 0.01F. Observe the output waveform and calculate the frequency.
330 R output
0.01uF 0.01uF

R 330

Figure 1

28

Toff Ton

Waveform Period (T) = T ON + T OFF Frequency= 1 T

Now change the capacitance from 0.01 to 0.1F measure the period and note down the time constant ( =RC) graph. The frequency is calculated as 1/ period. The waveform is as shown here.

Ton

TOFF

Waveform

Conclusion: It is observed that the frequency is inversely to time constant. Review Question: (1) What is the difference between a one-shot (mono-shot) and free-running multivibrator?

29

SHIFT REGISTER Aim: to understand the functions and operations of shift register. Requirements: Shift registers, oscilloscope, DC Power supply etc. Description: A flip flop is a one bit register which stores either 1 or 0. A shift register is an array of flip flops which shifts data in a particular sequence and direction in response to clock pulse. A shift register takes either serially or parallelly and sends out the data serially or parallelly. When it operates in a serial mode, it has the advantage of less hardware and disadvantage of taking larger execution time. When operated in the parallel mode, the hardware required is more while the execution time is less. The shift register is another building block of a digital system. It is used for temporary data storage, digital delay line, sequence generator, ring counter etc. Shift registers are available in both Bipolar and MOS forms. Here, let us consider 4-BIT BIDIRCTIONAL UNIVERSAL SHIFT REGISTER (74LS194A). (a) 4-BIT BIDIRCTIONAL UNIVERSAL SHIFT REGISTER (74LS194A). It is a Bidirectional high speed shift register. It has the following features: Asnchronous Master Reset Fully synchronous Serial or Parallel data Transfers Shift left or Shift right operation
+V c c 1 6 Q0 1 5 Q1 1 4 1 3 Q2 Q3 1 2 C P 1 1 S1 1 0 9 S0

7 L 14 A 4 S 9
1 M R 2 DSR 3 P0 4 P1 5 P2 6 P3 7 DSL 8

Pin Names: S 0 , S1 Mode control input p 0 -p 3 D SR D SL Parallel data inputs Serial (Shift Right) data input Serial (Shift Left) data input

30

CP

MR
Q 0 -Q 3

Clock (active high going edge) input Master Reset (active LOW) input Parallel output.

Mode Selection - truth Table Operating Mode Input Output MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L X X X X X L L L L H H L X L X q1 q2 q3 L SHIFT LEFT H H L X H X q1 q2 q3 H H L H L X X L q0 q1 q2 SHIFT RIGHT H L H H X X H q0 q1 q2 Parallel Load H H H X X Pn P0 P1 P2 P3 Check the following operations: The Truth Table indicate the functional characteristic of the 74LS194A.All data and mode control inputs are edge triggered, responds only to the LOW to HIGH transition of the clock (CP). All the operation is in synchronous with the clock pulse. 1. Master Reset: It is an asynchronous operation and all the output goes to ZERO (Q 0 -Q 3 ) when MR is LOW.
2.

Parallel load: Set the 4 bit parallel data input at P 0 -P 3 (say 1011) then set the mode control input MR=HIGH, S 0 = S 1 = High. When the CP goes from LOW

to HIGH transfer of data from P 0 -P 3 inputs to Q 0 -Q 3 outputs is taking place. 3. SHIFT LEFT: SET MR= HIGH and S 1 =HIGH and S 0 = LOW. The SERIAL DATA (shift Left) Input may be set to HIGH or LOW. For every clock pulse (Low to High) the output will change as given in the Table: Table: Q 3 Q 2 Q1 Q 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 Set D SL =0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 4. SHIFT RIGHT: For this operation set MR= HIGH, S 1 =LOW, S 0 =HIGH and the D SL may be set to HIGH or LOW. For every clock pulse (Low to High) the output will change as given in the Table: Q 3 Q 2 Q1 Q 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 Set D SR =1 Set D SL =1

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1 1 1 1 0

1 1 1 1 1 0 1 0 0 0 0 0 0 0 0

Set D SR =0

Conclusion: The operation of 4 Bit Shift BIDIRECTIONAL UNIVERSAL Shift Register(74LS194A) operations are studied in detail.

SYNCHRONOUS COUNTER Aim: To design and test the count sequences of a synchronous counter. Requirements: Synchronous counter (74LS161), Oscilloscope, DC Power supply etc. Description: Synchronous Counters eliminate the cumulative propagation delays of
Flip Flops, which generally limits the performance of the ripple counters. All the Flip Flops in this counter are under the control of the same clock pulse. Therefore the repetition rate is limited only by the propagation delay of one Flip Flop.

The 74LS161 is a high speed 4-bit synchronous counter. It is edge triggered synchronously pre-settable and cascadable MSI building blocks for counting, memory, addressing, frequency division and other applications. It has an asynchronous Master Reset (clear) input that overrides and is independent of the clock and all other control inputs. It has the following features:
Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge Triggered Operation.
+Vc c 1 6 T C 1 5 Q0 1 4 1 3 Q1 Q2 1 2 Q3 1 1 CT E 1 0 P E 9

PIN NAMES:

711 46
1 M R 2 C P 3 P0 4 P1 5 P2 6 P3 7 CP E 8

PE
P 0 -P 3 CEP CET CP

Parallel Enable (active LOW) input. Parallel Inputs. Count Enable Parallel Input. Count Enable Trickle Input. Clock (active High Going Edge) input. Master Reset (active LOW) Input. Synchronous Reset (active LOW) input.

MR SR

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Q 0 -Q 3 TC

Parallel Output. Terminal Count Output. CEP X X H X L Action on the Rising Clock Edge Reset (Clear) Load (P n Q n ) Count (increment) No Change No Changego

Mode Select Table: SR PE CET L X X H L X H H H H H L H H X

1.

Master Reset: Switch on the Power Supply. The counter output at Q 0 -Q 3 may take a random value of 0s and 1s. Set MR = LOW (0). It overrides all other input conditions and set the output to ZERO. Parallel Load: Set the number to be loaded on P 0 -P 3 say 1010. Set the control inputs MR =H, PE =L. Now apply a clock pulse CP. When the clock pulse goes from LOW to HIGH the contents of P 0 -P 3 is transferred to Q 0 -Q 3 respectively. Synchronous Count Incrementing: Set the control inputs MR =H, PE =H, CET=H, CEP=H and then apply clock at CP. Note that the counter increments for every rising edge transition of the clock. It is a 4 Bit counter and hence the counting is from 0000 to 1111. Note the waveforms of the output on the oscilloscope with reference to clock pulse. Note that all count change takes place only at the Low to High transition period of the clock pulse. The Counter output divides the clock frequency by a factor of TWO. The Terminal Count goes HIGH when the counter reaches its maximum Value of 1111.

2.

3.

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Clock input Q0 output

Q1 output

Q2 output

Q3 output Terminal Count(TC)

Conclusion: The control bits function and the counter operations are studied in detail.

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