The Ninth International Conference on Electronic Measurement & Instruments

ICEMI2009

A Built-in Self-test Design with Low Power Consumption Based on Genetic Algorithm
Enmin Tan Li Wang
School of Electronic Engineering, Guilin University of Electronic Technology, Guilin, 541004, China Email: tem0135@guet.edu.cn

Abstract A low peak power consumption built-in self-test (BIST) design based on genetic algorithm (GA), which is denoted by GAITPG, has been proposed in our previous study. This paper presents an improved performance of GAITPG, which also aims at the reduction of the changes between successive test patterns. (m-1) vectors were inserted between two successive n-bit pseudorandom test patterns generated by the original linear feedback shifted register (LFSR), while m and the element of groups were optimized by GA. Experimental results based on ISCAS85 benchmark circuits show that the test pattern generator (TPG) with low power consumption proposed in this paper is efficient, without losing stuck-at fault coverage. Also, a comparison of reduction of power consumption between GAITPG and other scheme (such as inserted TPG (ITPG)) was reported. Keywords low power consumption design, GA, BIST, TPG, LFSR, weighted switching activity (WSA)

current value during the cycle of CSR, at the same time, the n-bit outputs of LFSR perform XOR operation with the n-bit outputs of CSR one by one, to produce the vectors inserted in two successive patterns from the LFSR. Although the pattern and succedent inserted vectors are correlative, the next pattern generated by LFSR is random, leading to a pseudo single-input-change test set, which reduce the peak power consumption ineffectively. A low peak power consumption BIST TPG based on genetic algorithm (GA), which is denoted by GAITPG, has been proposed in reference [2]. It aimed at the reduction of the changes between successive test patterns and adopts the test-per-clock structure. As shown in figure 2.

. INTRODUCTION Approaches on power consumption reduction during built-in self-test (BIST) have appeared. Reference [1] has a brief overview. A method of them, which was denoted by inserted test pattern generator (ITPG), i.e. the BIST TPG proposed in [1], was based on a linear feedback shifted register (LFSR), leading to pseudo single-input-change test set to reduce the number of weighted switching activity (WSA) at inputs of the circuit under test (CUT), as shown in figure 1.
Fig. 2. Structure of GAITPG.

This paper presents an improved performance of GAITPG, followed by a compare of reduction of power consumption with other low power BIST TPG design, as indicated by figure 1. . OPTIMIZING PROCESS BASED ON GA
Fig. 1. Structure of ITPG.

For an n-bit cycle shifted register (CSR), only after performing one cycle (which equals 2n CLK cycles) and returning to all-zero state can the LFSR generate the next pattern. That is to say, the outputs of LFSR maintain

_____________________________
978-1-4244-3864-8/09/$25.00 2009 IEEE

As showed in reference [2], (m-1) vectors are inserted between two successive n-bit pseudorandom test patterns generated by the original LFSR, and moreover the transition density of test patterns is lowered availably. In order to minimize the power consumption, m and the element of a group are needed to be optimized by GA, as described in figure 3. The evolutionary process includes roulette selection, one-point crossover, mutations and inversions. By

2-526

The Ninth International Conference on Electronic Measurement & Instruments calculating and modifying in this paper, mutation probability was set to 0.05, and crossover probability was set to 0.8. Optimized individuals obtained from some ISCAS85 benchmark circuits are shown in table 1.

ICEMI2009

Then, for example, according to the input ports number of table 2, the selected primitive polynomial of LFSR for C432 circuit was 36: 25, 0, by which the VC development tools schemed out a 36-stage LFSR to generate test patterns. At last, Faultsim was used to perform fault simulation and analysis one by one on the original LFSR and the GAITPG. The results were indicated respectively in figure 4 and 5.
Table 1. Optimized individual by GA.

circuits C432 C499 C880 C1355 C1908 C3540

Fig. 3. Procedure flow chart of GA.

optimized individual 11011111101010000001111111 0000000001 010101011001010110011011000 10000011011111 001110111111010011110110000 0010001100010101111 000100011001010 000111010111111001010101000 10011110101100 10100001110011001010111111 0010011 011110111000110101100110001 00001011011001001011010 1001110100011001101110001 0011110

For example, the input ports number n of circuit C432 is 36, while the inserted vectors number V is 18. After setting a seed f101bb288 to the LFSR, the optimized individual calculated by GA is 110111111010100000011111110000000001, which means the optimized groups of input ports for low power consumption are 1, 2, 3~4, 5, 6, 7, 8, 9, 10~11, 12~13, 14~20, 21, 22, 23, 24, 25, 26, 27~36. . EXPERIMENT RESULT Firstly C codes were used to perform the simulations one by one on the original LFSR, the inserted TPG (as described in figure 1) and the GAITPG, and experiments were performed on some ISCAS85 benchmark circuits. The goal of the experiments is first to make sure that the stuck-at fault coverage keeps the same when the test length of the GAITPG is the same with the original LFSR, and next to measure the total power, the average power and the peak power savings that the GAITPG allows to obtain on the CUT by calculating the WSA, the WSAa and the WSAp reduction. A. Simulation on stuck-at fault coverage The stuck-at fault coverage calculations were performed with a concurrent fault simulator Faultsim of our group. Firstly, the foundational data of some ISCAS85 benchmark circuits are listed in table 2.

C6288

Table 2. Foundational data of some circuits.

circuits C432 C499 C880 C1355 C1908 C3540 C6288

input ports number 36 41 60 41 33 50 32

output ports number 7 32 26 32 25 22 32

gates number 160 202 383 546 880 1669 2416

faults number 524 758 942 1574 1879 3228 7744

Furthermore, a comparison of the stuck-at fault coverage can be made between the original LFSR and the GAITPG, under the condition that their test length is equal, as shown in table 3. For most of the ISCAS85 benchmark circuits, both stuck-at fault coverage obtained by the two schemes are very similar. B. Simulation on power consumption Analogically, C codes were used to simulate the aforementioned test generation process, which includes the original LFSR, the inserted TPG shown in figure 1 and the GAITPG. Then test set were obtained and applied to the CUT: some ISCAS85 benchmark circuits.

2-527

The Ninth International Conference on Electronic Measurement & Instruments

ICEMI2009

WSA and the WSAa achieved, without losing the stuck-at fault coverage.
Table 3. Simulation result of fault coverage.

Fig. 4. Fault simulation on original LFSR.

Fig. 5. Fault simulation on GAITPG.

f101bb2 88 8000001 5101 16a3376 60 C880 34d00a1 1 0 3 41 aaaaaaaa C1355 aa1 3 0 33 44bd2a4 C1908 b0 20 0 50 49 f811814 C3540 181172 24 23 0 32 31 C6288 aaaaaaaa 5 4 0

primicircu- tive its polynomial 36 C432 25 0 41 C499 38 0

LFSR test seeds [1] length 2000 1600 10000 4000 2000

stuck-at fault coverage (FC)% original GAITPG LFSR 99.237 98.813 99.894 99.492 97.339 98.885 98.813 98.832 99.492 94.201

4000

95.741

94.341

2000

99.561

99.561

In the experiment, WSA was used to evaluate the energy/power consumption of the circuit [4]. That is to say, as defined in reference [4], WSA is usually used for evaluating total power consumption, while WSAa for average power consumption and WSAp for peak power consumption. With the same test length, a comparison of the WSA, the WSAa and the WSAp can be made between the GAITPG and the ITPG, as reported in table 4. As mentioned above, the test length and LFSR parameters were adopted from table 2 and 3, while the WSA was counted under the zero-delay model. Table 4 shows that the WSA and the WSAa reduction obtained by GAITPG are similar to that by the inserted TPG, while the WSAp reduction obtained by GAITPG are much higher than that by the ITPG, as farther described in figure 6. . CONCLUSION As showed in table 4 and figure 6, GAITPG can highly reduce the WSA, the WSAa and the WSAp during BIST application, that is, all the total power/energy, the average power and the peak power consumption are highly reduced. Experimental results based on ISCAS85 benchmark circuits show that about 26% to 64% reductions in the number of the WSAp are attained, additionally, approximate 50% to 90% reductions of the
2-528

Table 4. Comparison of power consumption between ITPG and GAITPG.

circuits WSA

ITPG
WSAa WSAp WSA

GAITPG
WSAa WSAp

C432 C499 C880 C1355 C1908 C3540

32203 91199 199403 367221

16 14 19 91

173 24238 169 83970

13 11

136 107 193 199 422 839 1830

362 136005 13 521 238958 59 728 140033 87 1283 309515 75 2591 914455 815

258069 129 441324 110

C6288 1691785 845

A comparison of reduction of power consumption between GAITPG and ITPG was reported, to demonstrate that GAITPG is much more efficient in the reduction of peak power consumption.

The Ninth International Conference on Electronic Measurement & Instruments REFERENCES

[1]

ICEMI2009

[2]

[3]

[4]

[5] [6] Fig. 6 Peak power consumption reduction rate between GAITPG and ITPG

R. H. He, X. W. Li, and Y. Z. Gong, A low power BIST TPG design. Proceedings of the 5th international conference on ASIC, 2003. 1136-1139, vol. 2. E. M. Tan, S. D. Song, and W. K. Shi, Power Reduction in BIST Design Based on Genetic Algorithm and Vector-Inserted TPG. Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments. Xian,2007,Vol. . 4-533-537. X. D. Zhang, W. L. Shan, and K. Roy. Low-power weighted random pattern testing. IEEE Transactions on CAD of ICs and Systems, 2000, 19(11): 1389-1398. N. Ahmed, M. H. Tehranipour, and M. Nourani, Low power pattern generation for BIST architecture. Proc. of the 2004 International Symposium on Circuits and Systems, (ISCAS '04), pp. II - 689-92 Vol.2, May 23-26,2004. P. Girard. Survey of Low-Power testing of VLSI Circuit. IEEE Design & Test of Computers, 2002, 19(3): 82-92. M. L. Bushnell, and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Publishing House of Electronics Industry, pp.369-395, 2005.

ACKNOWLEDGMENT This paper was supported by the Natural Science Foundation of China (No. 60861003). Specially, the authors wish to thank Jia Lei for the opportunity he gave the authors to present this work at the CAT laboratory of Guilin University of Electronic Technology, Xuelong Yan for many discussions on algorithms, and the anonymous reviewers for their valuable comments. This work was supported by the Natural Science Foundation of China (NSFC) under grant No. 60861003.

2-529