MODE Cut-O

VGS VGS < VT

VDS -

CGB

CGS 0

CGD 0

Noise Margins NMH = VOH-VIH NML = VIL - VOL

Nicholas Laughton 100807575 ELEC3500

Triode

VGS > VT

VDS < VGS - VT

Substrate Bias Eect

(reduces to Body Eect when phi = 0)

Saturaon

VGS > VT

VDS > VGS - VT

Digital Design Methods Behavioural Structural Physical

Levels of Abstrac!on for Simula!on Stochas c Behaviour Gate Switch

Types of Coding
1.

Mealy / Moore Machines

Mealy - output is dependent on both the current inputs and the current state Moore - output is dependent solely on the current state

Procedural Structural
2.

Latches and Flip - Flops

1. 2. 3. 4. RS Latch - asynchronous set and reset D Latch - transparent on half clock / storage on other half D Flip-Flop - Master and Slave D-Latches store data on clock edge (either rising or falling) Enabled D Flip-Flop - use MUX to gate the ip-op or gate the clock (gated clock has issues)

The Design Process

1. 2. 3. Simulate at high-level (behavioural simula on) Synthesis (similar to compiling; determines gate level design) Gate level verica on through simula on, fault simula on and ming verica on.

System Clocking

AND / NOR Gated Clock NAND / OR Gated Clock Latched Gated Clock

no change when clock high / hard to design no change when clock low / easy to design use D latch to block glitches in banned region

Module Header Module Instance

module #(rising delay, falling delay, turnoff delay) module_name(pins); eg: nand #(3, 4) nandme(OUT, INA, INB); module_name #(param1 value, ) instance_name (.pin1(pin1), .pin2(pin2), , .pinN(pinN)); eg: mymodule #(16) mymodule_A(.clk(clk), .rst(rst), .outputA(outputA)); * the param1_value modifies the first parameter statement within the module

Timescale Specification

`timescale reference_unit / accuracy_unit eg: `timescale 100 ps / 10 ps

Data storage types Wire left hand side of structural code (i.e. assign statements) Reg left hand side of procedural code (i.e. initial or always statements) Scalar / [cols] Vector / [cols] Array [rows]

1. 2. 3. 4.

Finding Hazards Algebraically DeMorgan all NANDS and NORS Find variables which cannon have hazards (need both var and its inverse) Determine what combina on of variable values reveals hazard Use these variable values to mask hazard

Masking Sta!c-1 1. On K-Map, draw loop to cover adjacent ones 2. Algebraically, add an OR of the product of terms that reveal the hazard ( of ) Masking Sta!c-0 1. On K-Map, draw loop to cover adjacent zeros 2. Algebraically, add an AND of the terms that reveal the hazard ( of )
Masking Dynamic Hazard (Edge Triggered Hazard) Mask the embedded sta c hazard!!

Gate Iner!a / Gate Delay A glitch whose dura on is shorter than the propaga on delay of a gate will not pass through that gate

Two-Variable Hazards A two-variable hazard is maskable when the path passes through all ones or all zeros. A two-variable hazard is non-maskable when the opposite is true.

There is an error within the code (should be n-2)