TMOS E-FET.

Power Field Effect Transistor

NChannel EnhancementMode Silicon Gate
This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over time. In addition, this advanced TMOS EFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Robust High Voltage Termination Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode G Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature

MTP6N60E
ON Semiconductor Preferred Device

TMOS POWER FET 6.0 AMPERES 600 VOLTS RDS(on) = 1.2 OHMS

CASE 221A09, Style 5 TO220AB

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage Continuous NonRepetitive (tp 10 ms) Drain Current Continuous Continuous @ 100C Single Pulse (tp 10 s) Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS 405 RJC RJA TL 1.0 62.5 260 C/W C Value 600 600 20 40 6.0 4.6 18 125 1.0 55 to 150 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ

Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds

Preferred devices are ON Semiconductor recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2001

March, 2001 Rev. 5

Publication Order Number: MTP6N60E/D

MTP6N60E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 600 Vdc, VGS = 0 Vdc) (VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) DraintoSource OnVoltage (VGS = 10 Vdc, ID = 6.0 Adc) (VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 300 Vdc, ID = 6.0 Adc, VGS = 10 Vdc) (VDS = 300 Vdc, ID = 6.0 Adc, VGS = 10 Vdc, Vdc RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage (1) (IS = 6.0 Adc, VGS = 0 Vdc) (IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr (IS = 6.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD LS 7.5 3.5 4.5 nH nH ta tb QRR 0.83 0.72 266 166 100 2.5 1.2 C ns Vdc 14 19 40 26 35.5 8.1 14.1 15.8 30 40 80 55 50 nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss 1498 158 29 2100 220 60 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 2.0 6.0 5.5 8.6 7.6 mhos 3.0 7.1 0.94 4.0 1.2 Vdc mV/C Ohms Vdc V(BR)DSS 600 IDSS IGSS 1.0 50 100 nAdc 689 Vdc mV/C Adc Symbol Min Typ Max Unit

Reverse Recovery Time

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MTP6N60E
TYPICAL ELECTRICAL CHARACTERISTICS
12 I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 4V 0 0 2 4 6 8 10 12 14 16 18 0 2.0 2.5 3.0 3.5 4.0 4.5 5V 8V TJ = 25C VGS = 10 V 7V 12 6V I D , DRAIN CURRENT (AMPS) 10 8 6 4 2 100C 25C TJ = -55C 5.0 5.5 6.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS 10 V

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 2.5 VGS = 10 V 2.0 1.5 1.0 0.5 0 25C -55C TJ = 100C 1.4

Figure 2. Transfer Characteristics

TJ = 25C 1.3 1.2 1.1 1.0 0.9 0.8 15 V VGS = 10 V

6 4 8 ID, DRAIN CURRENT (AMPS)

10

12

10

12

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current and Temperature

2.5 2 1.5 1 0.5 0 -50 10000

Figure 4. OnResistance versus Drain Current and Gate Voltage

RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

VGS = 10 V ID = 3 A

VGS = 0 V TJ = 125C 100C

1000 I DSS , LEAKAGE (nA)

100 25C

10

-25

0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)

125

150

100 200 300 400 500 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

600

Figure 5. OnResistance Variation with Temperature

Figure 6. DrainToSource Leakage Current versus Voltage

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MTP6N60E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted calculating td(on) and is read at a voltage corresponding to the by recognizing that the power MOSFET is charge onstate when calculating td(off). controlled. The lengths of various switching intervals (t) At high switching speeds, parasitic circuit elements are determined by how fast the FET input capacitance can complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring be charged by current from the generator. which is common to both the drain and gate current paths, The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance produces a voltage at the source which reduces the gate drive varies greatly with applied voltage. Accordingly, gate current. The voltage is determined by Ldi/dt, but since di/dt charge data is used. In most cases, a satisfactory estimate of is a function of drain current, the mathematical solution is average input current (IG(AV)) can be made from a complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have rudimentary analysis of the drive circuit so that finite internal gate resistance which effectively adds to the t = Q/IG(AV) resistance of the driving source, but the internal resistance During the rise and fall time interval when switching a is difficult to measure and, consequently, is not specified. resistive load, VGS remains virtually constant at a level The resistive switching time variation versus gate known as the plateau voltage, VSGP. Therefore, rise and fall resistance (Figure 9) shows how typical switching times may be approximated by the following: performance is affected by the parasitic circuit elements. If tr = Q2 x RG/(VGG VGSP) the parasitics were not present, the slope of the curves would tf = Q2 x RG/VGSP maintain a value of unity regardless of the switching speed. where The circuit used to obtain the data is constructed to minimize VGG = the gate drive voltage, which varies from zero to VGG common inductance in the drain and gate circuit loops and RG = the gate drive resistance is believed readily achievable with board mounted and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the During the turnon and turnoff delay times, gate current is data in the figure is taken with a resistive load, which not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power values from the capacitance curves in a standard equation for MOSFETs may be safely operated into an inductive load; voltage change in an RC network. The equations are: however, snubbing reduces switching losses. td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when
3200 Ciss C, CAPACITANCE (pF) C, CAPACITANCE (pF) 2400 1000 Coss Crss 10 VDS = 0 V VGS = 0 V TJ = 25C 10000 TJ = 25C VGS = 0 V

Ciss

1600

Crss

Ciss

100

800 Coss 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25

10

100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1000

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance Variation

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MTP6N60E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT 10 8 6 4 2 0 Q3 0 6 12 18 24 QT, TOTAL CHARGE (nC) VDS 30 Q1 Q2 100 VGS 200 300 1000 VDD = 300 V ID = 6 A VGS = 10 V TJ = 25C VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

100

ID = 6 A TJ = 25C

10

td(off) tf tr td(on)

0 36

10 RG, GATE RESISTANCE (OHMS)

100

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

6 I S , SOURCE CURRENT (AMPS) 5 4 3 2 1 0 0.50 VGS = 0 V TJ = 25C

0.55

0.60

0.65

0.70

0.75

0.80

0.85

VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTP6N60E
SAFE OPERATING AREA
E , SINGLE PULSE DRAINN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 s 450 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 ID = 6 A

10 100 s 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100

1.0

0.1 0.1

dc 1000

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 0.0001 0.001 0.01 t, TIME (SECONDS) t2 DUTY CYCLE, D = t1/t2 0.1 t1 P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1 10

0.1

0.01 0.00001

Figure 13. Thermal Response

di/dt IS trr ta tb TIME tp IS 0.25 IS

Figure 14. Diode Reverse Recovery Waveform

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MTP6N60E
PACKAGE DIMENSIONS CASE 221A09 ISSUE AA
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04

T B
4

SEATING PLANE

F T S

Q
1 2 3

A U K

H Z L V G D N R J

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EFET and TMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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MTP6N60E/D

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