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Guglielmo Marconi 1897 : Wireless Telegraph Company 1909 : Nobel Price in Physics It is dangerous to put limits on wireless Gordon Moore 1968 : Co founded INTEL Corporation 2005 : Marconi Society Lifetime Achievement Award Moores law (1965/75) paces the evolution of integrated circuits until today

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First transistor radio: TI Regency TR-1 (1954) Texas Instruments first silicon transistor (1954)

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M.Witte, 2010

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Introduction: Some History Scaling Laws, Trends, and Observations Are there still challenges??

Some examples why I think YES

The limit of wireless OR motivation for some more fancy research

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2x every 18 months

New multiplexing schemes allow to allocate more bandwidth to a single user for higher peak throughput Spectral efficiency increases due to LTE A

Higher order modulation schemes Spatial multiplexing HSPA

UMTS E EDGE EDGE GSM

270 kHz GMSK 270 kHz 8 PSK 2x270kHz 32 QAM 5 MHz QPSK 5 MHz 16 QAM

LTE HSPA+

2x2 MIMO 64 QAM 4x4 MIMO 20 MHz

40 MHz 64 QAM 4x4 MIMO 80 160 MHz 256 QAM 8x8 MIMO 1.7 GHz 16 QAM

64 QAM 20 MHz 40 MHz 64 QAM 2x2 MIMO

802.11b 802.11

D BPSK 11 MHz CCK 11 MHz

Imbalance between complexity and integration density Data rate doubles every 18 months Algorithm complexity grows (spectral efficiency)

2x every 18 months

2x every 24 months

100M

Complexity [Gate equivalents] 10M

1M

100k

Data collected by M.Witte, 2010

2010

10

100M

Complexity [Gate equivalents] 10M

1M

Number of Transistors required for integrationSome empirical data: grows less rapidly than evolution of baseband complexity

complexity over time

Data collected by M.Witte, 2010

100k

2010

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Op. frequency # Gates/mm2 Gops/s/mm2 Some saturation around 65-45nm

180

45

180

45

180

45

Example

Clock freq. 16x16 Mult + overhead (50/50)

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2000

Liu et al.

2004

46mm2 130nm

2006

43mm2 90nm

2009

Shirasaki et al.

112mm2 250nm

66mm2 45nm

2G

2.5G

3G

3.5G

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Cellular modems require multi standard support Nevertheless the number of discrete modem components decreases rapidly

GSM EDGE WCDMA HSPA+ LTE LTE-A Legacy support guarantees coverage

Source: Dr. H. Eul, Keynote at 2010 VLSI Conference

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Components

10 5 0 94 97 00 03 06

2G (GSM/EDGE) 3G (WCDMA/HSPA)

Reduces cost (PCB, packaging, and manufacturing More space for battery and display

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Communication Application

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Additional air interfaces, connectivity options, and storage 3D Graphics and Video Powerful application processors

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Technology: 0.18 um

Data download

Technology: 0.18 um

Power consumption

J. Ayers, et al..,An Ultralow-Power Receiver for Wireless Sensor Networks, JSSC 2010

Simple OOK radio for sensor nodes 0.18 nJ/bit (complete transceiver)

Energy efficiency

P. Petrus, et al., An Integrated Draft 802.11n Compliant MIMO Baseband and MAC Processor, ISSCC 2007

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Power

Standby Poor

Voice OK

Data Good

Energy efficiency

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Leakage and standby currents dominate as Power DSP becomes more energy efficient Workload decreases (e.g., standby)

Useful data traffic

OFF Very poor Standby Poor Voice OK

Data Good

Energy efficiency

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130nm

1000 300 500 0 345 285 Tx RF 800 600 400 200 0 BB 540 360 Rx PA

>70% area covered by baseband signal processing DSP consumes significant power compared to RF (especially RX)

S. G. Sankaran, et al., Design and Implementation of a CMOS 802.11n SoC, Comm. Magazine 2009

45nm

>40% of the digital die covered by baseband signal processing RX: Baseband consumes most of the total power

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S. Kunie, et al., Low power architecture and design techniques for mobile handset LSI Medity M2, ASPDAC, 2008

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MIMO: Transmit multiple data streams concurrently in same frequency band Used in almost all important standards Task of the MIMO detector: Separation of multiplexed data streams Choice of the MIMO detector has significant impact on performance Optimum MIMO detection:

Straightforward solution: Check all candidates Number of candidates: exponential in spectral efficiency

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2002: 4 stream MIMO over UMTS Spectral efficiency 8 bits/s/Hz Examine 256 candidates 4 million times per second

2009: MIMO WLAN Spectral efficiency 24 bits/s/Hz Examine 224 candidates 40 million times per second

2009 : MIMO WLAN 600 Mbps (24 bits/s/Hz)

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Sphere decoding Map the problem to a tree search Use branch and bound strategy for complexity reduction STS sphere decoding provides soft information for channel decoder

2007 : STS Soft-output sphere-decoding with 10-40 Mbit/s

250nm 2mm2 71M nodes/s

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Sphere decoding 802.11n 4 parallel instances Map the problem to a tree search work at at 320MHz Use branch and bound strategy 25mm2 1.28G nodes/s 2mm for complexity reduction 2mm STS sphere decoding provides soft information for channel decoder Near optimum performance @ 600Mbps

2007 : STS Soft-output Technology shrink & sphere-decoding architecture optimization with 10-40 Mbit/s

250nm 2mm2 71M nodes/s

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Exchange reliability information between MIMO detector and channel decoder Converge to optimum solution in multiple iterations

Iterations require soft in soft out MIMO detection, which is even more complex Complexity for N iterations increases at least N fold

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3GPP 2007: Extension of 2G system GSM / EDGE toward higher data rates Higher modulation order (16QAM and 32QAM) 1.2x higher symbol rate Bandwidth remains unaltered

32QAM Tx-signal (Evolved EDGE)

Optimum receiver: Maximum likelihood sequence estimation (MLSE) Complexity grows exponentially in spectral efficiency and channel length

Impractical even in a 32nm process

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Solution: channel shortening with decision feedback sequence estimation Orders of magnitude channel coefficients Viterbi complexity reduction estimation computation DFSE with decoder

input buffer FIR filter adaptive number of trellis states: 8 (GMSK) 8 (8PSK) 16 (16QAM) 32 (32QAM) decoder input memory shared memory turbo decoder

channel decoder

8 6 GOps 4 2 0 GSM

130nm

Complexity

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Solution: channel shortening with decision feedback sequence estimation Orders of magnitude channel coefficients Viterbi complexity reduction estimation computation DFSE with decoder

Dedicated ASIC solution [Benkeser et al., ISSCC2010]

input buffer FIR filter adaptive number of trellis states: 8 (GMSK) 8 (8PSK) 16 (16QAM) 32 (32QAM) decoder input memory shared memory turbo decoder

channel decoder

8 6 GOps 4 2 0 GSM

130nm

6.8mW

Complexity

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Performance close to the Shannon limit (on par with Turbo codes) Initially considered to complex for economic implementation

VLSI technology allowed for the implementation of LDPC codes

Today: LDPC codes are optional or mandatory in almost all relevant standards

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Iterative message passing Large number of identical computational units, operating in parallel exploits resources available from scaling

Different standards use different codes Different codes required within each standard Computational effort across standards spans 3 orders of magnitude Computational effort per bit remains almost constant

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208 MHz clock frequency 780 Mbps throughput 3.4mm2 silicon area Workload ~50 100 GOps

180nm

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208 MHz clock frequency 780 Mbps throughput 3.4mm2 silicon area Workload ~50 100 GOps

180nm

Constant throughput

90nm

Can we do still better??

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Voltage Frequency Scaling: make things worse to make them better Design a circuit that works faster than planned (e.g., by replication)

When running at the same speed and voltage, energy efficiency becomes worse

Reduce voltage until it just meets the delay constraint

/N

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Voltage Frequency Scaling: make things worse to make them better Design a circuit that works faster than planned (e.g., by replication)

When running at the same speed and voltage, energy efficiency becomes worse

/N

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Voltage Frequency Scaling: make things worse to make them better Design a circuit that works faster than planned (e.g., by replication)

When running at the same speed and voltage, energy efficiency becomes worse

/N

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Production test is needed Identify chips with production defects Classify functional dies according to the speed they can reach

Manufacturing

Production test

Microprocessors: functional dies sold at Speed binning improves yield different prices depending on their speed Communication ASICs: need to run at a predefined fixed clock speed

Slow dies must be discarded Fast dies do not exploit better performance

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Voltage Scaling Quadratic power savings x Increases mean delay making circuits slower x Increases also delay variance making harder to meet target performance

# of occurances

path delay

More dies may fail to meet target performance

Conventional Solution Overdesign: assume pessimistic guard bands (timing, voltage) x Higher power consumption on average x Limit the returns performance, power) from technology scaling

130nm

90nm

65nm

45nm

32nm

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SNR (distance)

Throughput (rate)

Error rate

6 bits

MIMO detector

4 streams

Channel decoder

600 Mbps

48 tones every 4 m s

MIMO detector

Channel decoder

Rate adaptation is routinely used to deal with constantly varying channel conditions

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SNR (distance)

Throughput (rate)

Error rate

Put this scalability to service for better energy efficiency and 6 bits tolerance against process variations

MIMO detector

4 streams

Channel decoder

600 Mbps

48 tones every 4 m s

MIMO detector

Channel decoder

Rate adaptation is routinely used to deal with constantly varying channel conditions

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Iterative receivers / decoders: data passes multiple times through the same algorithm Performance improves with each iteratrion Deminishing returns after few iterations

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Iterative receivers / decoders: data passes multiple times through the same algorithm Performance improves with each iteratrion Yield improvement: exploit scalability Deminishing returnsretain few iterations under process to after functionality variations

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Baseband processor is comprised of logic and memory (on chip and sometimes off chip) Prediction from ITRS roadmap:

Memory becomes dominant issue

Primary concern: embedded (small medium size) memories in DSP blocks Occupy a significant percentage of the area Consume a significant share of the power Memories are the primary source of failure (yield loss)

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Denser and larger memories are more susceptible to radiation Process variation leads to static errors and dysfunctional cells Reduced noise margins and supply noise induce errors in weak cells

Manufacturing circuits (memories) that are actually functional and robust becomes increasingly difficult

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Fault tolerant by design: Channel fading (random fluctuation of signal strength) Unknown (noisy) channel parameters Thermal noise and interference System level mechanisms to restore reliable behavior: Forward error correction coding Automatic repeat request Application level fault tolerance (e.g., video over UDP)

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Conventional Paradigm

100% reliability, accept area & power overhead Sell only defect free dies

Proposed Paradigm

Relax yield requirement (for inherently resilient systems) Sell dies with limited amount of defects (broken memory cells)

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Conventional yield definition Accepting only chips with no defects Proposed yield definition Y(Nf) for systems with inherent hardware error resilience Chips with at most Nf faulty memory cells pass inspection Accepting more defects means Higher yield, and/or Lower voltage & power

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Example : Communication system with bit interleaved coded modulation (BICM) HSPDA. WiMAX, 3GPP LTE, GSM, WLAN, Interleaver memory: stores reliability information of the received data bits

Fault model : de interleaver built from unreliable memory (5% BER) Binary symmetric channel Randomized error locations

8 7 6 5 4 3 2 1 0 0 5 10 15 20

SNR [dB]

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Example : Communication system with bit interleaved coded modulation (BICM) HSPDA. WiMAX, 3GPP LTE, GSM, WLAN, Interleaver memory: stores reliability information of the Unreliable circuit received data bits

Fault model : de interleaver built from unreliable memory (5% BER) Binary symmetric channel Randomized error locations

8 7 6 5 4 3 2 1 0 0 5 10 15 20

SNR [dB]

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Explore the resilience limits of wireless communication systems to hardware defects Simulation of complete HSPA+ system, with error injection (in HARQ memory)

HSPA+ System

Transmitter

LLR Storage

For various defect rates (Nf) Inject create memory instances Circuit Errors with random fault locations

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20 errors (Nf=0.01%, 200kb LLR storage) (Almost) same throughput as for defect free hardware 2000 errors (Nf=1%) Achieve required throughput (but clear penalty w.r.t. defect free hardware) Power reduction by allowing low voltages (~200 mV less)

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New Algorithms and Architectures for Bypassing the Exponential Complexity Associated with Spectral Efficiency

Exploiting System Level Error Tolerance to Cope with the Issues of Depp Submicron Integration

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Signal processing algorithms: MIMO detection, sparse channel estimation, equalization, CS ADCs for spectrum sensing System design and test (prototype implementations): MIMO, visible light communication, communication over plastic optical fibers, GSM/Evolved EDGE, TD SCDMA VLSI circuits for communications: circuit techniques for low power and ultra high speed signal processing, fault tolerant signal processing for deep submicron VLSI, VLSI for embedded systems andreas.burg@epfl.ch http://tcl.epfl.ch/

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