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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 51, NO.

11, NOVEMBER 2004

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A Novel Common-Subexpression-Elimination Method for Synthesizing Fixed-Point FIR Filters


Chia-Yu Yao, Member, IEEE, Hsin-Horng Chen, Tsuan-Fan Lin, Chiang-Ju Chien, and Chun-Te Hsu
AbstractIn this paper, we propose a novel common-subexpression-elimination (CSE) method for the synthesis of xed-point nite-impulse response (FIR) lters. The proposed CSE algorithm considers both the redundancy among the canonic-signed-digit (CSD) lter coefcients and the length of the critical path in the multiplier block of a transposed-form FIR lter. Therefore, the proposed CSE method can perform tradeoff designs between complexity and the throughput rate. The number of adders synthesized by our method is commensurate with that by the graph-dependence algorithms. On the other hand, our method can synthesize a high-order complicated FIR lter in a few seconds. Index TermsCanonic signed digit (CSD), common subexpression elimination (CSE), nite-impulse response (FIR) lters, xed point arithmetic, high-level synthesis.

I. INTRODUCTION

Fig. 1. (a) -tap transposed-form FIR lter. (b) Coefcient multiplications are replaced by a multiplier block.

O DESIGN a nite-impulse response (FIR) lter with xed-point coefcients, it is inevitable that we have to nd the lters coefcients in a discrete space rst. It is well known that representing an integer in the signed-powers-of-two (SPT) space is more efcient than representing it in the twos complement binary space when the number of nonzero digits is concerned. It is also well known that the so-called canonic-signed-digit (CSD) code is the best SPT code because the number of nonzero digits of a CSD code is minimal. Clearly, having the CSD coefcients of an FIR lter is not enough. From the hardware design perspective, translating the CSD coefcients of an FIR lter into a considerably simple hardware is as important as nding them. In the past decades, many researchers aimed at reducing the number of adders for realizing the FIR lters. They considered all coefcients of a transposed-form FIR lter as a whole and replaced coefcient multiplications by a multiplier block, as is shown in Fig. 1. Their methods nd the redundancy across the SPT coefcients in the multiplier block of a transposed-form FIR lter, for example, the common-subexpression-elimination (CSE) methods [1][5] and the graph-dependence (GD) algorithms [6][9]. Hence, some adders in the multiplier block can be shared and the hardware complexity is reduced. The idea of CSE is to nd multiple SPT patterns (the common subexpressions) in the coefcient set. These patterns are used in the way that the input signal multiplies each SPT pattern only

Manuscript received December 23, 2003; revised March 11, 2004 and June 8, 2004. This work was supported by the National Science Council of Taiwan, R.O.C. under Grant NSC 92-2218-E-211-002. This paper was recommended by Associate Editor Z. Wang. The authors are with the Department of Electronic Engineering, Huafan University, Taipei 223, Taiwan R.O.C. (e-mail: chyao@huafan.hfu.edu.tw). Digital Object Identier 10.1109/TCSI.2004.836853

once. The problem left is how to nd proper SPT patterns such that sharing these patterns has advantages over sharing other patterns. On the other hand, in GD algorithms, an SPT coefcient is represented by a graph. (It is noticed that the graph representation of a coefcient is not unique.) Each vertex of a graph represents a partial sum. These partial sums can be shared across coefcients if possible. In general, the more partial sums are shared, the more adders are saved. A kind of GD algorithm that we have to mention is the -dimensional reduced adder graph (RAG- ) algorithm. The RAG- algorithm produces lters with the least number of adders in the examples given in reference [7]. Therefore, the results produced by the RAG- method are employed for comparison in this paper. Usually, the GD algorithms outperform the CSE algorithms in terms of the required number of adders. However, references [4], [8] and [9] indicate that the conventional GD algorithms may produce FIR lters with long critical paths in their multiplier blocks. Therefore, reference [8] employs a step-limiting RAG- method to achieve tradeoff designs between the required number of adders and the length of the critical path in the multiplier block and reference [9] uses a minimum-depth processing to reduce the depth of an adder graph. In this paper, we propose a new CSE method that considers not only the SPT patterns in coefcients but also the length of the critical path in the multiplier block. The examples in Section V will show that the number of adders synthesized by our method is commensurate with that by the RAG- algorithm. In addition, the run time of the proposed CSE method is acceptable. For the most complicated design in [10] (a 121-tap FIR lter with 15-bit wide coefcients), our method can complete the synthesis job in a few seconds on a P4-1.8-GHz personal computer.

1057-7130/04$20.00 2004 IEEE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 51, NO. 11, NOVEMBER 2004

Fig. 2. Example of realizing a coefcient in AS = 3 and AS = MAS = 2.

This paper is organized as follows. In Section II, we introduce some terminologies and notations that are used in the proposed CSE method. In Section III, we present our new CSE method. In Section IV, we use a worked-out example to explain the operations of the proposed CSE algorithm. In Section V, we show some design results of our procedure in comparison with the results designed by other methods. Finally, some conclusions are drawn in Section VI. II. TERMINOLOGIES AND NOTATIONS Before we go through the detail of the proposed CSE method, we have to introduce some terms. Adder Step (AS ): An AS of a coefcient is the number of adders along the critical path when that coefcient is realized. minimum AS (MAS): The MAS of a coefcient is the number of adders along the shortest critical path among all possible realizations of that coefcient. Fig. 2 is an , example of implementing a CSD coefcient or . It can where means 1, in adds faster than be seen that the realization with the realization with . It is noticed that the number of adders required to implement a coefcient equals its number of SPT terms minus one and is independent of its AS. Denote the number of nonzero SPT terms of a CSD number as . Using a complete binary tree of adders to construct the multiplication by that CSD number, we can . determine that Filter AS (FAS ): The FAS is the number of adders along the critical path of the multiplier block of a transposedform FIR lter. FAS cannot be less than the MAS of any coefcient. It is noticed that although the MAS is the number of adders along the shortest critical path for realizing a coefcient, it is not necessary to implement every coefcient of an FIR lter in its MAS form because the throughput rate of the FIR lter is limited by the FAS. Even if every coefcient is implemented in its MAS form, the throughput rate of the multiplier block without pipelining is still limited by the largest MAS of all coefcients. Therefore, it is the FAS of a multiplier block, not the MAS of a coefcient, that serves as a constraint when a coefcient is realized. If a coefcient is allowed to be realized in an

AS longer than its MAS, it will offer extra SPT patterns that can be shared with other coefcients. For example, we can nd 6 SPT patterns for the coefcient among all its possible realizations if the AS is limited to . However, we can nd extra 4 SPT patterns its (that makes a total of 10 SPT patterns) among all possible realizations of it if the limit of the AS is relaxed to be 3. Because some extra SPT patterns are offered, the probability of nding sharable SPT patterns across coefcients increases and the probability of sharing adders across coefcients also increases. Next, we introduce some notations that will be used to describe the proposed CSE method in the next section. : is the set of absolute values of CSD numbers that have been decomposed as a sum of some other CSD numbers. : is the set of absolute values of CSD numbers that are waiting to be decomposed as a sum of some other CSD numbers. In our algorithm, we have to decompose all CSD until becomes empty. numbers in : The set is constructed as follows: All possible combinations of SPT terms of each CSD coefcient result in some CSD numbers. These CSD numbers are continuously right-shifted (continuously divided by 2) until they become odd. Next, take the absolute values of these odd CSD numbers and collect them in the set . Finally, erase 1 and any CSD coefcient or its right-shift versions from . For example, if a CSD coefcient equals the set , then the CSD numbers in calculated from combining different SPT terms of are

If there exists another CSD coefcient 1 000 010(66), then . After is con100 001(33) must be erased from structed, all CSD coefcients can be composed of some . elements in : is the set of positive CSD numbers that possess . , , and : , , and . : represents an element in . : is denoted as the number that is synthe(directly or indirectly) and possesses . sized by III. PROPOSED CSE METHOD

In the beginning of the proposed CSE algorithm, the set is empty and the set contains the absolute values of CSD numbers that are from continuously right-shifting all CSD coefcients until they become odd. The idea of our algorithm is: We to synthesize CSD numuse CSD numbers in as far as we can because, in this way, we do not need bers in and, thus, require the new CSD numbers to be included in least number of extra adders. When some CSD numbers in cannot be synthesized in this way, we then employ CSD numbers in to synthesize them. The procedure of our method is as follows.

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Fig. 3. Rule 1 for evaluating the number of extra adders required for d in the second loop of the proposed algorithm.

1) Construct the set from the CSD numbers in . 2) Classify all numbers in and according to their MAS. (an empty set){ 3) While down to 1 { For Decompose all (if ( or ) then , ; ), else , and , with properly chosen , , and where . to . Move } Do { down to 1 { For Decompose all (if ( or ) then , ; else , ), , , and , with all possible , and where .} Find the smallest set of excluding . is not uniquely determined, then { If Select the set whose elements require the least number of extra adders evaluated in Rule 1 . of Fig. 3 as is still not uniquely determined, then { If Count the frequency of appearance of (excluding 1). Select the set whose elements possess the . most frequency of appearances as is still not uniquely determined, then If Select the set whose elements possess the . shortest accumulated wordlength as } } to and move to . Move } until no new is obtained. Do { down to 1 { For Decompose all

(if ( or ) then , ; ), else , , , and , with all possible where , .} Find excluding 1. is not uniquely determined, then { If Select the set whose elements require the least number of extra adders evaluated in Rule 2 of . Fig. 4 as is still not uniquely determined, then { If Count the frequency of appearance of and (excluding 1). Select the set whose elements possess the . most frequency of appearances as If is still not uniquely determined, then Select the set whose elements possess the . shortest accumulated wordlength as } } to and move to , Move , . and are obtained. } until no new } Unlike the conventional CSE method that searches matched SPT patterns across coefcients, the proposed algorithm looks for pairs of available CSD numbers to synthesize the CSD , as is shown above. The proposed method has numbers in an advantage of nding some unobvious SPT relations between CSD numbers over the conventional CSE methods. We use the following example to show this point: Suppose there are three . In conventional CSD numbers: 100001, 1001, and CSE methods, the only common subexpression found in these . However, our method can nd three CSD numbers is

where 1 means one-bit left shift. There are three loops in Step 3. In the rst loop, we search that can be used to defor numbers in the set under inspection. Because compose the number contains numbers that have been synthesized or are about to be synthesized, if we nd the required pair of numbers in the rst . (This pair loop, we only need an extra adder to synthesize is of numbers is a pair of common subexpressions.) After decomposed, it moves from the set to the set . is not empty, then we need After the rst loop, if the set to decompose . First, we to search for numbers in the set is from look for the case that one number (a common subexpression) and the other number is from , as is shown in the second loop of Step 3. Next, we and , in to decompose look for both numbers, , as is shown in the third loop of Step 3. When the synthesis procedure is complete, the number of elements in equals the number of adders required in the multiplier block. is In the proposed algorithm, the number of elements in the number of adders that we have to realize later. Therefore, the

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 51, NO. 11, NOVEMBER 2004

Fig. 4. Rule 2 for evaluating the number of extra adders required for d and d in the third loop of the proposed algorithm.

number of new elements joining the set is of great concern. , we want the When some new elements are joining the set joining of them as efcient as possible. Thus, in the second and , we have to nd the third loops, after we decompose some smallest set that contains the least amount of new elements . These new elements in that can be used to synthesize are moved from to . is not unique, we rst evaluate the number of When required extra adders for the new elements in the sets under consideration. We next count the frequency of appearances of the new elements in the sets under consideration because the frequency of appearances reect the possibility of sharing these still can not be determined new elements in the future. If uniquely, then we will select the set whose elements have the shortest accumulated wordlength. It is noticed that the wordlength of a CSD number will not affect the nal number of adders but it will affect the routing area of the nal hardware. Multiplication by a short CSD number will produce a small intermediate value and the signal lines carrying the small intermediate value occupy a small routing area. Because the proposed method always looks for common rst, it is a subexpressions to decompose the numbers in contains the CSE algorithm. On the other hand, because least amount of new elements that can be used to synthesize in the second and third loops, it will contain common exist. subexpressions if the common subexpressions for containing common subexThus, we always keep the set pressions as far as we can in the proposed algorithm.

IV. WORKED-OUT EXAMPLE We employ the example given in [1] to explain our CSE method. The coefcients are

In order not to occupy too many pages, in this example, the CSD numbers are represented in their integer forms. , In the beginning First, let

Next, we construct by taking all possible SPT-term combinations of the CSD coefcients. Take as an example. The CSD numbers calculated from combining are summarized in Table I. The posidifferent SPT terms of tions of the SPT terms of these CSD numbers are aligned with so the reader the corresponding positions of SPT terms of can easily check them. It is noticed that the rst ve digits of can be extracted two 3s, but only one counts beand . cause the third digit is shared by the patterns The set constructed from all CSD coefcients is

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CSD NUMBERS IN

TABLE I CALCULATED FROM

= 10101 001

The numbers in are classied into two sets: and . The numbers in and also classied into two sets:

are

The other numbers in are in . In our algorithm, is synthesized by numbers with the number with . The equality holds only when the FAS constraint is not violated. During the rst loop of the rst iteration, we use the numbers to synthesize the numbers in . We nd a in pair of common subexpressions, 831 and 105, that can be used to decompose 815 and 621 as

(Because 105 is the lter coefcient we need to synthesize, it is also considered as a common subexpression here.) Thus, and . Next, during the second loop of the rst iteration, We nd that 105 is again a common subexpression that can be use to decompose 831 as (1) . It is noticed that both 831 and 105 have the where same MAS (=2). Using 105 to synthesize 831 leads to increasing the AS of 831 by one. Since 815 and 621 are synthesized by 831, their ASs are also increased by one. This will not vio. Therefore, late the FAS constraint because , , , and 9 is eliminated from . Next, still in the same loop, we determine a common subexpression 9 that

Fig. 5. Multiplier blocks for coefcients {105, 831, 621, 815} synthesized by (a) the proposed method for FAS = 4, (b) the proposed method for FAS = 3, and (c) the RAG- method.

On the other hand, if , (1) will result in a violation of the FAS constraint. In this case, we can not determine how to decompose 831 and 105 in the second loop so we proceed to the third loop. It is noticed that we cannot use any number in to synthesize 831 or 105 without leading to a violation of the FAS constraint. Thus, we use the numbers in to synthesize 105 and 831. We have

where . Because 3 and 9 have , the AS of 105 , , , remains as 2. Hence, and 3 is eliminated from . Finally, still in the same loop, we have

To determine how to decompose 105 and 831, we nd the . Because 15 is used to synthesize smallest set both 105 and 831, 15 is a common subexpression. Therefore, , , , and . Finally, still in the third 15 and 129 are eliminated from loop, we determine that

where , and . The synthesis procedure is complete. It is noticed that in this case, only the rst two loops are executed.

Thus, and . The multiplier blocks synthesized by the proposed CSE method for and 3 are shown in Fig. 5(a) and 5(b),

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TABLE II SUMMARY OF NUMBER OF ADDERS AND FAS IN MULTIPLIER BLOCKS OF SEVERAL METHODS FOR WORKED-OUT EXAMPLE

TABLE IV COMPARISON OF SYNTHESIS RESULTS OF PROPOSED METHOD, ILP-BASED CSE METHOD [5], RAG-n METHOD [7], AND C1 ALGORITHM [9] FOR FIR FILTER USED IN EXAMPLE 2

TABLE III COMPARISONS OF FILTERS IN EXAMPLE 1 SYNTHESIZED BY OUR CSE ALGORITHM, THE CSE METHOD OF [3], AND THE RAG-n METHOD OF [7]

TABLE V COEFFICIENT REALIZATION OF FIR FILTER IN EXAMPLE 2 WITH FAS = 4. NUMBERS IN BOXES ARE ABSOLUTE VALUES OF FILTER COEFFICIENTS

respectively. Fig. 5(c) shows the multiplier block for the same coefcients synthesized by the RAG- method. (In Fig. 5, represents left-shifting by bits.) All multiplier blocks have six adders. However, the Fig. 5(a) multiplier block possesses , the Fig. 5(b) multiplier block possesses , but the Fig. 5(c) multiplier block possesses . The same example was also studied in [4]. Together with the results given in [4], we summarize all results in Table II. V. DESIGN EXAMPLES Example 1: We use the proposed CSE method to synthesize six lters: and are the lters originally given in Examples , , and are lters originally given in 1 and 2 of [11]. is the lter modied from Examples 1, 2, and 3 of [10]. by the authors of [3] such that the maximum number of nonzero SPT terms per coefcient of is reduced by one compared with that of . Table III summaries the results of six lters synthesized by the proposed CSE algorithm, the CSE methods of [3], and the is the lter length, RAG- method of [7]. In Table III, represents the maximum number of SPT terms per coefcient, represents the number of adders required to realize the multiplier block after the process of CSE or RAG- method, and denotes the minimum FAS of the multiplier block. Because is the same as the greatest MAS of all coefcients, . It can be seen that, with the minimum FAS, the proposed CSE method outperforms the CSE method of [3] in two and ). On the other hand, when the FAS is inlters ( creased by one, the number of adders required to realize the multiplier block by the proposed CSE method decreases in four , and ). In all lters, we reach the same cases ( , , as the RAG- method has when . It is well known that the RAG- method usually produces multiplier blocks with a small amount of adders but with a long FAS [4], [8], [9]. From this example, we see a tradeoff design between the number of adders and the FAS in a multiplier block can be achieved by our CSE algorithm. , , , and , For simple to moderate FIR lters the proposed CSE method complete the design works in less and (lter than 0.1 second. For the complicated lters length 121, coefcient wordlength 15-bit wide), the proposed CSE method complete the design works in 4.531 and 0.953 s, respectively. The run time of the proposed CSE algorithm is acceptable for most design works. Example 2: In this example, we synthesize a symmetric 25-tap FIR lter whose coefcients are given in [9]. The number of digits required for these CSD coefcients is 13. The maximum number of SPT terms of a coefcient is 6. Therefore, . the minimum FAS is Table IV summarizes the synthesis results of the lter in [9] by the proposed CSE method, the ILP-based CSE method[5], the RAG- method [7], and the C1 algorithm [9]. In Table IV, represents the number of adders in the multiplier blocks syn, the thesized by different methods. We see that when proposed method produces the same number of adders as the ILP-based CSE method does. When the FAS is increased to 4, the proposed method produces the same number of adders as the RAG- method does. However, the RAG- method lead to . On the other hand, the C1 algorithm a result with uses 19 adders for , one more adder is required than

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the result synthesized by the proposed CSE method. The coefby the proposed CSE method cient realizations for are given in Table V for reference, where the numbers in boxes are the absolute values of lter coefcients. VI. CONCLUSION A novel CSE method used for synthesizing xed-point FIR lters is presented. The proposed method can nd unobvious SPT relations between CSD numbers. We also argue that when the multiplier block of an FIR lter is realized, the FAS should be considered as a constraint. Increasing the FAS, the proposed CSE method can produce a lter whose number of adders in the multiplier block is commensurate with that synthesized by the RAG- method. As far as we know, this is the rst CSE method that can perform tradeoff designs between complexity and the throughput rate. The run time of the proposed CSE method is acceptable. For given in [10] (lter length 121, the most complicated lter coefcient wordlength 15-bit wide), the proposed CSE method complete the synthesis job in about 4.531 s on a P4-1.8 GHz personal computer. ACKNOWLEDGMENT The authors wish to express their appreciation to Prof. A. Dempster for his kindly sharing a Matlab code of his RAG- algorithm. His kindness enabled the authors to complete the comparative jobs in the examples of this paper. REFERENCES
[1] M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, Multiple constant multiplications: efcient and versatile framework and algorithms for exploring common subexpression elimination, IEEE Trans. Computer-Aided Design, vol. 15, pp. 151165, Feb. 1996. [2] R. I. Hartley, Subexpression sharing in lters using canonic signed digit multipliers, IEEE Trans. Circuits Syst. II, vol. 43, pp. 677688, Oct. 1996. [3] R. Pako, P. Schaumont, V. Derudder, S. Vernalde, and D. Durackov, s A new algorithm for elimination of common subexpressions, IEEE Trans. Computer-Aided Design, vol. 18, pp. 5868, Jan. 1999. [4] M. Martnez-Peir, E. I. Boemo, and L. Wahammar, Design of highspeed multiplierless lters using a nonrecursive signed common subexpression algorithm, IEEE Trans. Circuits Syst. II, vol. 49, pp. 196203, Mar. 2002. [5] O. Gustafsson and L. Wahammar, ILP modeling of the common subexpression sharing problem, in Proc. 9th IEEE Int. Conf. Electronic Circuits Systems, vol. 3, Dubrovnik, Croatia, Sept. 2002, pp. 11711174. [6] D. R. Bull and D. H. Horrcks, Primitive operator digital lter, in Proc. Inst. Elect. Eng. Circuits Devices Syst., vol. 138, June 1991, pp. 401412. [7] A. G. Dempster and M. D. Macleod, Use of minimum adder multiplier blocks in FIR digital lters, IEEE Trans. Circuits Syst. II, vol. 42, pp. 569577, Sept. 1995. [8] H.-J. Kang and I.-C. Park, FIR lter synthesis algorithms for minimizing the delay and the number of adders, IEEE Trans. Circuits Syst. II, vol. 48, pp. 770777, Aug. 2001. [9] A. G. Dempster, S. S. Dimirsoy, and I. Kale, Designing multiplier blocks with low logic design, in Proc. IEEE Int. Symp. Circuits Systems, vol. 5, Phoenix, AZ, May 2002, pp. 773776. [10] Y. C. Lim and S. R. Parker, Discrete coefcient FIR digital lter design based upon an LMS criteria, IEEE Trans. Circuits Syst., vol. CAS-30, pp. 723739, Oct. 1983. [11] H. Samueli, An improved search algorithm for the design of multiplierless FIR lters with powers-of-two coefcients, IEEE Trans. Circuits Syst., vol. 36, pp. 10441047, July 1989.

Chia-Yu Yao (S88-M92) was born in Taiwan, R.O.C., in 1963. He received the B.S. degree from National Taiwan University and the M.S. and Ph.D. degrees from University of California at Los Angeles, in 1985, 1988 and 1992, respectively, all in electrical engineering. During 1985-1987, he served as a Second Lieutenant in the Chinese Military Academy. During 1990-1991, he was with LinCom corporation, Los Angeles, CA, and was engaged in a program about satellite communication system analysis granted by the NASA. In 1992, he joined the Department of Electronic Engineering, Huafan University, Taipei, Taiwan, R.O.C., where he is currently an Associate Professor. His research interests include digital lter design, CMOS RF integrated circuits, and neural networks Dr. Yao was one of the recipients of the Group Achievement Award from the Computer Sciences Corporation in 1991 and was the advisor of the Best Student Paper Award in signal processing of 2000 National Symposium on Telecommunications, Taiwan, R.O.C.

Hsin-Horng Chen was born in Taiwan, R.O.C., in 1979. He received the B.S. degree in electronic engineering and the M.S. degree in mechatronic engineering from Huafan University, Taipei, Taiwan, R.O.C., in 2001 and 2003, respectively. He is currently a Design Engineer at Weltrend Semiconductor Inc., Hsinchu, Taiwan, R.O.C.

Tsuan-Fan Lin was born in Taiwan, R.O.C., in 1977. He received the B.S. degree in electronic engineering and the M.S. degree in mechatronic engineering from Huafan University, Taipei, Taiwan, R.O.C., in 2000 and 2002, respectively. He is currently a Design Engineer at Kinpo Electronics Inc., Taipei, Taiwan, R.O.C.

Chiang-Ju Chien was born in Taiwan, R.O.C., in 1963. He received the B.S. degree in nuclear engineering from National Tsing Hua University, Hsinchu, Taiwan, R.O.C., and the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1985 and 1992, respectively. Since 1993, he has been with the Department of Electronic Engineering, Huafan University, Taipei, Taiwan, R.O.C., where he is currently an Associate Professor and the Chair of the Department. His present research interests are mainly in iterative learning control, adaptive control, fuzzy-neuro systems and control circuit design. He is a member of the Chinese Automatic Control Society.

Chun-Te Hsu was born in Taiwan, R.O.C, in 1976. He received the B.S. degree in electronic engineering, the M.S. degree in mechatronic engineering from Huafan University, Taipei, Taiwan, R.O.C., in 1999 and 2001, respectively, and is currently working toward the Ph.D. degree at the same university. His research interests include fuzzy control, system identication, and application-specied integrated circuit design.

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