CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION

Instructor Dr. smail Enis Ungan

Circuit Characterization and Performance Estimation

Resistance Estimation
The resistance of a uniform slab of conducting material is R=(/t)(l/w) where
: resistivity t : thickness l : conductor length w : conductor width
l w

An other expression is

R = Rs ( l / w ) where Rs is the sheet resistance having the units of / square ( / ! ).

Circuit Characterization and Performance Estimation
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Resistance Estimation
Resistance of multiple connected slabs is R = Rs ( 2l / 2w ) = Rs ( l / w )

t w w

Circuit Characterization and Performance Estimation

Resistance Estimation
Resistance of the layer divided into the squares;
l w w R = Rs ( l / w ) l=5xw w R = Rs ( l / w ) = 5 Squares x Rs R = 2 x Rs ( l / w ) l l

Circuit Characterization and Performance Estimation

Resistance Estimation
Typical sheet resistances of the layers in CMOS process;
Metal-1, metal-2 Polysilicon Diffusion n+ Diffusion p+ nWell 0.07 / ! 20 / ! 30 / ! 70 / ! 2.5 K / !

Resistance of a non-rectangular shape can be found from a table. Resistance of contanct and via is dependent on the area and the contact material. Typical values for 2m x 2m contact are;
Contact to p+ active Contact to n+ active Contact to polysilicon Via to metal-1 35 75 20 50 20 50 0.05 0.08
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Circuit Characterization and Performance Estimation

Capacitance Estimation
Dynamic response of MOS circuits are dependent on the parasitic capacitances associated with the MOS device and interconnection capacitances. The total load capacitance on the output of a CMOS gate is the sum of;
Gate capacitances of the other gate inputs Diffusion capacitances of the drain regions connected to the output. Routing capacitances of interconnections to the other gates.

During the design, it is essential to know the source of parasitic loads and their effects on the circuit characteristics.

Circuit Characterization and Performance Estimation

Metal Oxide Semiconductor as a Capacitor

MOS capacitor structure is similar to MOSFET without drain and source diffusion regions. MOS capacitor capacitance depend on the state of the semiconductor surface. Depending on the potential difference between the gate and the bulk, the surface may be in;
accumulation depletion inversion

Therefore, capacitance of the MOS capacitor is dependent on the voltage at the gate.

Circuit Characterization and Performance Estimation

Metal Oxide Semiconductor as a Capacitor

Capacitance when accumulation is formed by VG < 0 (for p-type substrate);
gate gate ( VG < 0 )

CO
VSS VSS

tox

p - substrate mobile holes

Circuit Characterization and Performance Estimation

Metal Oxide Semiconductor as a Capacitor

Single capacitance is calculated as; Co = A ( SiO2 0 ) / tox where
A : gate area

SiO2 : dielectric constant ( relative permittivity of SiO2) 0 : permittivity of free space

Circuit Characterization and Performance Estimation

Metal Oxide Semiconductor as a Capacitor

Capacitance when depletion layer is formed by Vt >> VG > 0;
gate gate ( VG ~ 0 )

CO
tox depletion layer d

Cdep
p - substrate VSS VSS negatively charged ions mobile holes

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor as a Capacitor

Two capacitances are calculated as; Co = A ( SiO2 0 ) / tox and Cdep = A ( Si 0 ) / d then Ceq = Co Cdep / ( Co + Cdep ) where
d : depletion layer depth

Si : dielectric constant ( relative permittivity of Si)

Circuit Characterization and Performance Estimation
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Metal Oxide Semiconductor as a Capacitor

Capacitance when inversion layer is formed by VG ~ Vt (for p-type substrate);
gate gate ( VG ~ Vt )

CO
tox shorted inversion layer depletion layer d

Cdep
VSS VSS p - substrate mobile electrons (minority carriers) negatively charged ions mobile holes

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor as a Capacitor

Source of free carriers at the surface is slow thermal generation of carriers. Charges on poly are mirrored by charges in inversion layer. Therefore, thermal generation of carriers will short out the depletion layer capacitance. Single capacitance is calculated as; Co = A ( SiO2 0 ) / tox If VG changes at a rate faster than 1KHz. Inversion layer formation can not follow the rate and Cdep appears again as; Cdep = A ( Si 0 ) / d and Ceq = Co Cdep / ( Co + Cdep )
Circuit Characterization and Performance Estimation
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Metal Oxide Semiconductor as a Capacitor

Capacitance variation as a function of VG is;
accumulation depletion inversion

Normalized as C/Co

1.0

high frequency

0.02 - 0.2 0 Vt VG

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor Device Capacitances

Capacitances in the MOSFET device are;
Cgs, Cgd : Gate to channel capacitances at source and drain regions, resp. Csb, Cdb : Source and drain-diffusion capacitances to bulk (substrate). Cgb : Gate to bulk capacitance. Gate overlap capacitances over source and drain are not shown.
gate tox source Cgs channel Csb depletion layer Cdb Cgb Cgd drain

substrate (bulk)

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor Device Capacitances

Total gate capacitance Cg is; Cg = Cgb + Cgs + Cgd Cg behaviour depends on the MOSFET operation regions;
Off region;
there is no channel => Cgs = Cgd = 0 there is depletion layer => Cgb = Co Cdep / (Co + Cdep)

Linear region;
Uniform channel formation => Cgs = Cgd = Co / 2, Cgb = 0.

Saturation region;
Drain region is pinched off => Cgd = 0 Thicker channel at source region => Cgs = (2 / 3) Co, Cgb = 0.

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor Device Capacitances

Total gate capacitance Cg is; Off Linear Cgb Cgs Cgd Cg A / tox 0 0 A / tox 0 A / (2 tox) A / (2 tox) A / tox 0 A 2 / (3 tox) 0 (finite for short channel) A 2 / (3 tox) 0.9 A / tox (short channel) Therefore, approximate Cg = Co for all operating regions.
Circuit Characterization and Performance Estimation
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Saturation

Metal Oxide Semiconductor Device Capacitances

Diffusion-to-substrate junction capacitances
Bottom area junction capacitance Sidewall area junction capacitances at the periphery
Cjp' Cjp'

diffusion Cjp'

Cjp'

Cja substrate (bulk)

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor Device Capacitances

Diffusion (source and drain regions) capacitance; Cd Cd = Cja x (a b) + Cjp x (2 a + 2 b) where
substrate Junction Perimeter Capacitance, Cjp poly

b a

Cja : junction capacitance per 2 Cjp : periphery capacitance per a : diffusion region width in b : diffusion region length in

Junction Area Capacitance, Cja poly

substrate (bulk)

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor Device Capacitances

Juntion capacitance under bias is; Cj = Cj0 ( 1 Vj / b ) where m : grading coefficient (0.3 for graded junction, 0.5 for abrupt junction) b : built-in junction potential (~0.6V) Vj : junction voltage (negative for reverse bias) Cj0 : zero-bias junction capacitance
m

Circuit Characterization and Performance Estimation

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Metal Oxide Semiconductor Device Capacitances

SPICE Modeling of MOS Capacitances
M2001 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U . . . .MODEL NFET NMOS TOX=200E-8 CGBO=200P CGSO=600P CGDO=600P + CJ = 200U CJSW=400P MJ=0.5 MJSW=0.3 PB=0.7 . . .

Calculations; Cox = / TOX Cg = W L Cox + W CGSO + W CGDO + 2L CGBO Cdrain = AD CJ (1 + VD / PB )MJ+ PD CJSW (1 + VD / PB )MJSW Csource = AS CJ (1 + VS / PB )MJ+ PS CJSW (1 + VS / PB )MJSW
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Circuit Characterization and Performance Estimation

Routing Capacitances
Single Wire Capacitances
Approximated by using a parallel-plate capacitance model. Fringing fields at conductor edges occur.

metal-1

insulator

insulator poly insulator

substrate

Circuit Characterization and Performance Estimation

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Routing Capacitances
Multiple Wire Capacitances
Multiple routing layers have capacitances to substrate and also have capacitances among them (overlapping and side-wall). Capacitances can be very complex to calculate.
metal-1 metal-1 insulator

insulator poly poly insulator

substrate

Circuit Characterization and Performance Estimation

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Routing Capacitances
Typical Capacitance values;
Layer to Layer Poly-1 to Subs (tox) Poly-2 to Subs. (tox) Poly-1 to Poly-2 Poly-1 to Subs. (fox) Metal-1 to Poly-1/Poly-2 Metal-1 to Subs. Metal-1 to Diff. Metal-2 to Poly-1 Metal-2 to Subs. Metal-2 to Diff. Metal-2 to Metal-1 Seperation m 0.040 0.046 0.070 0.600 1150 1500 900 1900 2500 1900 1000 Plate Cap. aF/2 863 750 493 58 38 23 38 18 14 18 35 Fringe Cap. aF/m

88 88 79 88 87 81 87 100
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Circuit Characterization and Performance Estimation

Distributed RC Effects
For very long wires with high sheet resistance, RC transmission line effect is seen. The line is represented by many number of RC sections. Signal propagation delay between input and output is approximated by;

tdwire = 0.35 R C l2
where R and C are resistance and capacitance per section or unit length of wire, and l is the number of sections or total unit length of wire. In order to optimize delay of a long wire, wire is divided in to segments and a buffer is inserted between successive segments. For a line that is divided into two segments, the total delay is;

tdwire = 0.7 R C (l / 2)2 + tdbuffer

Circuit Characterization and Performance Estimation

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Wire Length Design Guide

For sufficiently small wire lengths, RC delays can be ignored. This can be satisfied when wire delay is much smaller than the typical logic gate delay;

tdwire << tgate => 0.35 R C l2 << tgate => l << tgate/(0.35 R C)
Conservatively, ignore the wire delay if ;

l < 0.5 (tgate/RC)0.5

Circuit Characterization and Performance Estimation

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Switching Characteristics of Logic Gate

Switching speed of a CMOS gate is limited by the time taken to charge and discharge the load capacitance, CL, at the gate output.

Analytic delay model:

Fall time analysis;

tf = tf1 + tf2
where tf1 is the period during which output falls down from the level 0.9VDD down to VDD-Vtn. In this period, NMOS is SAT, PMOS is OFF. And tf2 is the period during which output continues to fall down from the level VDD-Vtn down to 0.1VDD. In this period, NMOS is LIN, PMOS is OFF. After the analysis the tf can be approximated by;

tf = k CL / n VDD
where k=3 to 4 for VDD=3V to 5V and Vtn=0.5V to 1V. Circuit Characterization and Performance Estimation
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Switching Characteristics of Logic Gate

Rise time analysis;

tr = tr1 + tr2
where tr1 is the period during which output rises up from the level 0.1VDD to |Vtp|. In this period, PMOS is SAT, NMOS is OFF. And tf2 is the period during which output continues to rise up from the level |Vtp| up to 0.9VDD. In this period, PMOS is LIN, NMOS is OFF. After the analysis the tr can be approximated by;

tr = k CL / p VDD
where k=3 to 4 for VDD=3V to 5V and |Vtp|=0.5V to 1V. For equally sized NMOS and PMOS, tf < tr due to n > p

Circuit Characterization and Performance Estimation

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Switching Characteristics of Logic Gate

Delay time is dominated by the output rise and fall times. It is approximately given by;

tdr = tr/2 tdf = tf/2

Average delay is;

td = (tdr + tdf)/2 => td = (tr + tf)/4

The delay of a gate can be determined by tuning the three parameters of;
(Width of MOSFETs) VDD CL

Circuit Characterization and Performance Estimation

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Switching Characteristics of Logic Gate

Empirical delay model:
A simulator is used to model the gate. The measured values are backsubstituted into appropriate delay equations.

Gate delay
The delay of simple gates may be approximated by the delay of an equivalent inverter. In a simple gate circuit, series connected i number of MOSFETs result in an effective of; 1/eff = 1/1 + 1/2 + + 1/i In a simple gate circuit, parallel connected i number of MOSFETs result in an effective of; eff = min{1, 2, , i}

Circuit Characterization and Performance Estimation

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Switching Characteristics of Logic Gate

Input waveform slope affects the delay
Input signal is not a step function, it has a finite rise and fall times.

Input capacitance affects the delay

Gate input capacitance is a function of gate input voltage. MOSFET gate to drain capacitance increases effective input capacitance (bootstrapping).

Switch-Level RC models
This is an RC modeling technique that represents transistors as a resistance discharging or charging a capacitance. The models include
Simple RC delay model, RC-tree model

Circuit Characterization and Performance Estimation

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Switching Characteristics of Logic Gate

Simple RC delay model
Delay while output is falling;

tdf = (Rpulldown)(Cout+Cint_pulldown)
where Rpulldown is the total resistance at the pull-down path and Cint_pulldown is the total internal parasitic capacitances at the pull-down path. Delay while output is rising;

tdr = (Rpullup)(Cout+Cint_pullup)
where Rpullup is the total resistance at the pull-up path and Cint_pullup is the total internal parasitic capacitances at the pull-up path. Average delay is;

td=(tdf + tdr) / 2

Circuit Characterization and Performance Estimation

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Switching Characteristics of Logic Gate

RC-Tree delay model
Delay while output is falling(rising);

tdf(r) = R1 C1+(R1+R2) C2 + (R1+R2+R3)C3 + + (R1+R2+ + Ri)Cout

where R1 is the effective resistance and C1 is the internal parasitic capacitance of the MOSFET closest to the VSS(VDD) power rail. And Ri is the effective resistance and Cout is the loading parasitic capacitance of the MOSFET closest to the output. Average delay is;

td=(tdf + tdr) / 2
Effective resistance of the MOSFET is determined by SPICE simulations.

Circuit Characterization and Performance Estimation

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Switching Characteristics of Logic Gate

Macro modeling
Logic gates are simple delay elements. Simulated gate delay characteristics are approximated as;

td= tinternal + k toutput

where k is the loading capacitance, toutput is delay per loading capacitance and tinternal is delay for zero loading capacitance. Simulator (SPICE) can be used to calibrate the delay equation.

Body Effect as a dynamic problem

Place the transistors with the latest arriving signals nearest to the gate output. If diffusion is used as wiring then use it for MOSFETs closest to the gate output.

Circuit Characterization and Performance Estimation

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CMOS Gate Transistor Sizing

Let a unit sized transistor has length, L, and width, W. Let the effective resistance of a unit sized transistor is R. So that, a transistor with length L and width 2W has effective resistance of R/2. Let Cd and Cg be the drain and gate capacitances of a unit sized transistor. Consider two cascaded inverters; inverter pair. So that, all MOSFET lengths are L, width of NMOSFETs are W, width of PMOSFETs are 2W. Given n=2p . Assume that the capacitance at the first inverter output is the same as the capacitance at the output of the second inverter. The capacitance is;

C=(Cd+2Cd)+(Cg+2Cg) Ceq = Cd+Cg C= 3 Ceq

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Circuit Characterization and Performance Estimation

CMOS Gate Transistor Sizing

The effective resistance of the PMOSFETs is; Rp=(R/2)(n/p)=R The effective resistance of the NMOSFETs is; Rn=R Delay of the pair is approximated as;

tdpair=tdf + tdr tdpair = Rn (3 Ceq) + Rp (3 Ceq) tdpair = 6 R Ceq

For the width of both NMOSFETs and PMOSFETs of W, the delay is;

tdpair = Rn (2 Ceq) + Rp (2 Ceq) tdpair = 6 R Ceq

Remember that the changes in n and p affect the gate threshold voltage, Vm.

Circuit Characterization and Performance Estimation

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