ISA Level

How the machine appears to a machine language programmer ISA specifies: Instruction Set Register Model Memory Model (alignment and semantics) Addressing Modes

Introduction to Software & Hardware Engineering A

The Instruction Set Architecture (ISA) Level
Instruction Sets: Characteristics , Functions, Formats and Addressing Modes
School of Computer Science The University of Birmingham Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Instruction Set: Definition

The operation of a CPU is determined by the instruction it executes: machine instructions The collection of different machine instructions that a CPU can execute is referred to as the CPUs instruction set

Instruction Representation
Each instruction is represented as a sequence of bits which is devided into fields (elements). Symbolic representation Elements:
Operation Code (Opcode): These are represented by abbreviations (mnemonics). E.g. ADD, SUB, MPY, DIV, LDA, STA Operands:
Source/result operand reference
Register Memory I/O device

FORTRAN 90 program FORTRAN 90 program compiled to ISA program ISA level

C program C program compiled to ISA program Software Hardware ISA program executed by microprogram or hardware

Hardware

Next instruction reference

School of Computer Science The University of Birmingham Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Instruction Types

Instruction Types (cont.)

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Instruction Types and CPU Actions Summary

Shift/Rotate

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Flow of Control
In von-Neumann architecture, successively executed instructions are fetched from consecutive memory locations except in the presence of:
branches and conditional branches (jumps and loops) procedures/subroutines coroutines traps interrupts
Program counter

Branches
Program counter

Jumps

Time (a)

Time (b)

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Procedures
The return address may be saved in :
register
RN PC+d : PC X

Nested Procedures

Start of subroutine:
X PC +d : PC X+1

Top of stack (X :target address, d: instruction length)

(a) Calling procedure A called from main program (b) Called procedure

CALL

CA
RE

LL

TU

RN

RETU

RN

CA

LL

RE

TU

RN

A returns to main program

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Coroutines
When a coroutine is resumed, execution begins at the statement where it left off the previous time, not at the beginning as in subroutines
(a) A called from main program (b)

Interrupts
Changes in the flow of control caused by some external event (usually related to I/O) Context switching:
Save old PC, PSW and registers Execute interrupt handler

B RESUME
RESUME A

RESUME

RESU

ME A

RESUM

EB

RE

SU

ME

A returns to main program

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001 Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

School of Computer Science The University of Birmingham

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Instruction Cycle with Interrupts

Traps
An automatic procedure call initiated by some condition caused by the program:
Overflow (integer and floating point) protection violation undefined opcode stack overflow non-existent I/O device division by zero

Flow of control is switched to some fixed memory location which contains a branch to the trap handler

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Instruction Formats
Instruction format: The layout of bits, in terms of its constituent parts Efficiency of format depends on the technology Two major issues:
Instruction length Bit allocation
OPCODE (a) OPCODE ADDRESS (b)

Instruction Formats
Instruction length
memory size memory bandwidth vs. CPU speed caches short instructions increase memory transfer rate (e.g. if bandwidth is t bps, and average instruction lengthis r bits, then fetch rate t/r instructions per second) CPU complexity

OPCODE

ADDRESS1 ADDRESS2 (c)

OPCODE ADDR1 ADDR2 ADDR3 (d)

Bus structure and memory organisation

integral number of instructions during a fetch cycle RISC vs CISC
School of Computer Science The University of Birmingham Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

1 Word Instruction Instruction Instruction Instruction (a)

1 Word Instruction Instruction Instruction Instruction (b) Instruction Instruction Instruction Instruction

1 Word Instruction Instruction Instr. Instr.

Instruction (c)

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Instruction Formats
Bit allocation: number of opcodes vs. addressing capability
Number of addressing modes Number of operands Register vs memory addressing Number of register sets Address range Address granularity

Expanding Opcodes
Variable opcode and operand sizes e.g. consider a machine with 16-bit instructions and 4-bit addresses:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Opcode Address 1
16 bits 4-bit opcode 0000 xxxx yyyy zzzz 0001 xxxx yyyy zzzz 0010 xxxx yyyy zzzz 1100 xxxx yyyy zzzz 1101 xxxx yyyy zzzz 1110 xxxx yyyy zzzz 8-bit opcode 1111 0000 yyyy zzzz 1111 0001 yyyy zzzz 1111 0010 yyyy zzzz 1111 1011 yyyy zzzz 1111 1100 yyyy zzzz 1111 1101 yyyy zzzz 12-bit opcode 1111 1110 0000 zzzz 1111 1110 0001 zzzz 15 3-address instructions

Address 2

Address 3

14 2-address instructions

Example:
8-bit word vs.
Memory of 232 bytes, 0-4,294,967,295 character fetches faster

31 1-address instructions

1111 1111 1111 1111

1111 1111 1101 zzzz 1111 1111 1110 zzzz 16-bit opcode 1111 1111 1111 0000 1111 1111 1111 0001 1111 1111 1111 0010

1110 1110 1111 1111 1110 1111 0000 0001 zzzz zzzz zzzz zzzz

32-bit word
Memory of 0-1,073,741,823 shorter instruction fetches faster
School of Computer Science The University of Birmingham Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

16 0-address instructions

230 bytes,

1111 1111 1111 1101 1111 1111 1111 1110 1111 1111 1111 1111 15 12 11 8 7 4 3 0 Bit number

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Long vs. Short Instructions

Addressing Modes
How the bits of an address field in the instruction are interpreted to find the operand Types of addressing:
Immediate Direct Indirect Register Register Indirect Displacement
relative base-register Indexed

Stack
School of Computer Science The University of Birmingham Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Immediate Addressing
The operand is present in the instruction (Operand=A) Advantages
No memory reference to fetch data

Direct Addressing
Full memory address of operand: Effective Address EA=A Advantages
Simple:
Single memory reference to access data No additional calculations to work out effective address

Disadvantages
Limited operand magnitude

Disadvantages
Limited address space Global variables known at compile time
Instruction Opcode Address A Memory

Instruction Opcode Operand

Operand

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Indirect Addressing
Effective address in memory location pointed by address field: EA=(A) Advantages
large address space different memory words on different executions of the instructions (pointers) May be nested, multilevel, cascaded e.g. EA = (((A)))

Register Addressing
Similar to direct but specifies a register instead of memory location: EA=R Advantages
no memory reference (load/store architectures) Very small address field needed
Shorter instructions Faster instruction fetch

Disadvantages
Multiple memory references - Hence slower
Instruction
Opcode Address A

Disadvantages
limited address space
Opcode

Memory
Pointer to operand

Instruction Register Address R

Registers

Operand

Operand

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Register Indirect
Similar to indirect but specifies a register instead of memory location: EA=(R) Advantages
one memory reference less than indirect

Displacement Addressing
Combines the capabilities of direct and register indirect addressing EA=A+(R) Relative addressing: The implicitly referenced register is the PC (branches) EA = A + (PC) Base-register addressing (A=offset) Indexed addressing (R=offset, loops)
autoindexing: EA=A+R ; R (R)+1 postindexing: EA=(A)+(R) preindexing: EA=(A+(R))

Disadvantages
limited address space
Instruction
Opcode

Register Address R

Memory

Registers

Pointer to Operand

Operand

Advantage:Flexibility Disadvantage: Complexity

School of Computer Science The University of Birmingham Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Memory

Operand

Stack Addressing
Implied addressing using stack pointer (similar to register indirect addressing but no register mentioned): EA=top of stack Advantages
No memory reference very short

Address A

Disadvantages
limited applicability
Instruction

Instruction

Register R

Pointer to Operand

Registers

Implicit

Opcode

Top of Stack Register

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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Typical Stack Organisations

School of Computer Science The University of Birmingham

Introduction to Software & Hardware Engineering A Dr. Georgios K. Theodoropoulos 2000/2001

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