524 CA2

October 2000

NO IS A T DUC PRO

LE BSO

TE

CA1524, CA2524 CA3524

Regulating Pulse Width Modulator
Description
The CA1524 and CA3524 are silicon monolithic integrated circuits designed to provide all the control circuitry for use in a broad range of switching regulator circuits. The CA1524 and CA3524 have all the features of the industry types SG1524, SG2524, and SG3524, respectively. A block diagram of the CA1524 series is shown in Figure 1. The circuit includes a zener voltage reference, transconductance error amplier, precision R-C oscillator, pulse-width modulator, pulse-steering ip-op, dual alternating output switches, and current-limiting and shutdown circuitry. This device can be used for switching regulators of either polarity, transformer-coupled dc-dc converter, transformerless voltage doublers, dc-ac power inverters, highly efcient variable power supplies, and polarity converter, as well as other power-control applications.

Features
Complete PWM Power Control Circuitry Separate Outputs for Single-Ended or Push-Pull Operation Line and Load Regulation . . . . . . . . . . . . . . . 0.2% (Typ) Internal Reference Supply with 1% (Max) Oscillator and Reference Voltage Variation Over Full Temperature Range Standby Current of Less Than 10mA Frequency of Operation Beyond 100kHz Variable-Output Dead Time of 0.5s to 5s Low VCE(sat) Over the Temperature Range

Applications
Positive and Negative Regulated Supplies Dual-Output Regulators Flyback Converters DC-DC Transformer-Coupled Regulating Converters Single-Ended DC-DC Converters Variable Power Supplies

Ordering Information
PART NUMBER CA1524E CA1524F CA2524E CA2524F CA3524E CA3524F TEMPERATURE RANGE -55oC -55oC 0oC 0oC 0oC 0oC to to to to to to +125oC +125oC +70oC +70oC +70oC +70oC PACKAGE 16 Lead Plastic DIP 16 Lead CerDIP 16 Lead Plastic DIP 16 Lead CerDIP 16 Lead Plastic DIP 16 Lead CerDIP

Pinout
CA1524, CA3524 (PDIP, CERDIP) TOP VIEW
INV. INPUT NONINV. INPUT OSC OUT (+) C.L. SENSE (-) C.L. SENSE RT CT GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREF V+ EMITTER B COLLECTOR B COLLECTOR A EMITTER A SHUTDOWN COMPENSATION AND COMPARATOR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 2000

File Number

1239.4

CA1524, CA2524, CA3524 Functional Block Diagram

REFERENCE REGULATOR 5V +5V TO ALL INTERNAL CIRCUITS +5V 16 VREF FLIP FLOP 3 OSC OUT +5V OSCILLATOR RT +5V 7 CT 1 INV. INPUT 2 NON-INV. INPUT 1k 10 9 SHUTDOWN 10k COMPENSATION AND COMPARATOR ERROR AMP + +5V COMPARATOR +5V + C.L. EB 4 5 - SENSE SB 14 SA 11 EA CB 13 6 CA 12

15 V+

+ SENSE

GND

Test Circuit
8 - 40V ls V+ 15 13 OUT B 2k 1W 2k 1W 12 OUT A

CA1524
3 16 11 14

10

2k

2k

10 k

0.1F

RT

CT

10k 1k 2k

Specications CA1524, CA2524, CA3524

Absolute Maximum Ratings
Input Voltage (Between VIN and GND Terminals). . . . . . . . . . . . 40V Operating Voltage Range (VIN to GND) . . . . . . . . . . . . . . . . 8 to 40V Output Current Each Output: (Terminal 11, 12 or 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Output Current (Reference Regulator) . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Thermal Information
Thermal Resistance JA Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100oC/W Device Dissipation Up to TA = +25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W Above TA = +25oC . . . . . . . . . . . . . . .Derate Linearly at 10mW/oC Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 in. (1.59mm 0.79mm) from case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

Electrical Specications

TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and f = 20kHz, Unless Otherwise Stated. CA1524, CA2524 CA3524 MIN TYP MAX UNITS

PARAMETER REFERENCE SECTION Output Voltage Line Regulation Load Regulation Ripple Rejection Short Circuit Current Limit Temperature Stability Long Term Stability OSCILLATOR SECTION Maximum Frequency Initial Accuracy Voltage Stability Temperature Stability Output Amplitude Output Pulse Width (Pin 3) Ramp Voltage Low (Note 1) Ramp Voltage High (Note 1) Capacitor Charging Current Range Timing Resistance Range Charging Capacitor Range Dead Time Expansion Capacitor on Pin 3 (when a small osc. cap is used) ERROR AMPLIFIER SECTION Input Offset Voltage Input Bias Current Open Loop Voltage Gain Common Mode Voltage Common Mode Rejection Ratio Small Signal Bandwidth TA = TA =

TEST CONDITIONS

MIN

TYP

MAX

4.8 V+ = 8 to 40V IL = 0 to 20mA f = 120Hz, TA = VREF = 0, TA = 25oC -

5 10 20 66 100 0.3 20

5.2 20 50 1 -

4.6 -

5 10 20 66 100 0.3 20

5.4 30 50 1 -

V mV mV db mA % mV/khr

25oC

Over Operating Temperature Range TA = 25oC

CT = 0.001F, RT = 2K RT and CT Constant V+ = 8 to 40V, TA = 25oC

0.03 1.8 0.001 100

300 5 3.5 0.5 0.6 3.5 -

1 2 2 120 0.1 1000

0.03 1.8 0.001 100

300 5 3.5 0.5 0.6 3.5 -

1 2 2 120 0.1 1000

kHz % % % V s V V mA k F pF

Over Operating Temperature Range Terminal 3, TA = 25oC CT = 0.01F, TA = Pin 7 Pin 7 Pin 7 (5-2 VBE)/RT Pin 6 Pin 7 Pin 3 25oC

VCM = 2.5V VCM = 2.5V

72

0.5 1 80 70 3

5 10 3.4 -

60 1.8 -

2 1 80 70 3

10 10 3.4 -

mV A dB V dB MHz

25oC 25oC 25oC

1.8 -

AV = 0dB, TA =

Specications CA1524, CA2524, CA3524

Electrical Specications
TA = -550C to +125oC for CA1524, 0oC to +70oC for the CA2524 and CA3524; V+ = 20V and f = 20kHz, Unless Otherwise Stated. (Continued) CA1524, CA2524 PARAMETER Output Voltage Amplifier Pole Pin 9 Shutdown Current COMPARATOR SECTION Duty Cycle Input Threshold Input Threshold Input Bias Current CURRENT LIMITING SECTION Sense Voltage for 25% Output Duty Cycle Sense Voltage T.C. Common Mode Voltage Rolloff Pole of R51 C3 + Q64 OUTPUT SECTION (EACH OUTUT) Collector-Emitter Voltage Collector Leakage Current Saturation Voltage Emitter Output Voltage Rise Time Fall Time Total Standby Current: (Note 2) IS NOTES: 1. Ramp voltage at Pin 7 High Low VCE = 40V V+ = 40V, IC = 50mA V+ = 20V RC = 2K, TA = RC = 2K, TA = V+ = 40V 25oC 25oC 40 17 0.1 0.8 18 0.2 0.1 4 50 2 10 40 17 0.1 0.8 18 0.2 0.1 4 50 2 10 V A V V s s mA Terminal 9 = 2V with Error Amplifier Set for Max Out, TA = 25oC 190 200 210 180 200 220 mV % Each Output On Zero Duty Cycle Max. Duty Cycle 0 1 3.5 1 45 0 1 3.5 1 45 % V V A External Sink TA = TEST CONDITIONS 25oC MIN 0.5 TYP 250 200 MAX 3.8 MIN 0.5 CA3524 TYP 250 200 MAX 3.8 UNITS V Hz A

-1 -

0.2 300

+1 -

-1 -

0.2 300

+1 -

mV/oC V Hz

where t = OSC period in microseconds t RTCT with CT in microfarads and RT in ohms. t Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency when each output is connected in parallel.

2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.

CA1524, CA2524, CA3524 Schematic Diagram

15 VIN A R1 500 Q1 Q2 Q7 Q6 R12 10K Q3 Q4 R2 2.7K Q10 RC 10K R3 6.3K D1 10K Q11 1.9K R14 450 C4 Q19 RA 5.3K R8 8.4K QA R19 R18 18.7 18.7 K K Q12 R6 500 C2 20pF Q14 R9 500 Q15 N+ R4 500 8 GND OSC SECTION ERROR AMP Q42 Q43 Q47 Q48 R43 7.4K Q59 Q60 R10 1K P Q20 Q22 R15 25K F G H I Q24 PULSE STEERING FLIP-FLOP R17 R18 18.7 18.7 K K Q21 Q23 C Q9 C1 20pF RD Q16 R11 500 R13 6 Q13 Q17 Q18 R5 1K R7 1K B

R16 16.2K 16 VREF +5V

D2

RB 4.8K

D E

Q5

6 RT

Q44 Q49 Q50 R44 1.8K Q51 Q46 Q45 R39 1K R41 24K R40 560 R42 19.8K Q52 R45 25K Q53 Q54

Q55 INV. IN 1 Q56 Q57 2

Q61

NON-INV. INPUT J

7 CT

Q58 OSC. OUT 3 R47 1K R46 3.3K R48 2K

Q62

K L

CA1524, CA2524, CA3524 Schematic Diagram (Continued)

A OUTPUT A B Q33

OUTPUT B

COLL. A

12 Q34

R33 200

Q35

Q40

R36 200 Q41

13

COLL. B

R32 1K R34 500

CA 1pF Q36 Q39 D4

CB 1pF

R37 1K R35 500

R31 4.7 EMIT A 11

D3 RE 500

RF 500

R38 4.7 14 EMIT B

Q37

Q38

C R21 43.3K D E R23 8.7K Q26 Q27 F G H I R52 1.96K R54 1.96K COMPARATOR R27 5K R24 5K NOR NOR R30 43.3K

R25 5K

R26 5K Q29 Q30 Q31

R28 8.7K

COMP 10 9

Q65

Q67

Q68 J R49 1K Q64 Q63 R51 10K CURRENT LIMIT SECTION Q66 Q72 C3 45pF Q68 R53 1.8K

Q70 Q71

R50 10K K L 5

Q73

4 (+) C.L. SENSE

(-) C.L. SENSE

CA1524, CA2524, CA3524 Circuit Description

Voltage Reference Section The CAl524 series contains an internal series voltage regulator employing a zener reference to provide a nominal 5-volt output, which is used to bias all internal timing and control circuitry. The output of this regulator is available at terminal l6 and is capable of supplying up to 50mA output current. Figure 1 shows the temperature variation of the reference voltage with supply voltages of 8V to 40V and load currents up to 20mA. Load regulation and line regulation curves are shown in Figures 2 and 3, respectively. Osclllator Section Transistors Q42, Q43 and Q44, in conjunction with an external resistor RT, establishes a constant charging current into an external capacitor CT to provide a linear ramp voltage at terminal 7. The ramp voltage has a value that ranges from 0.6V to 3.5V and is used as the reference for the comparator in the device. The charging current is equal to (5-2VBE)/RT or approximately 3.6/RT and should be kept within the range of 30pA to 2mA by varying RT. The discharge time of CT determines the pulse width of the oscillator output pulse at terminal 3. This pulse has a practical range of 0.5s to 5s for a capacitor range of 0.001 to 0.1F. The pulse has two internal uses: as a dead-time control of blanking pulse to the output stages to assure that both outputs cannot be on simultaneously and as a trigger pulse to the internal ip-op which controls the switching of the output between the two output channels. The output dead-time relationship is shown in Figure 4. Pulse widths less than 0.5s may allow false triggering of one output by removing the blanking pulse prior to a stable state in the ip-op.
100 TA = +25oC
-60 -40 -20 0 20 40 60 80 100 120 140 (oC)

5.02 REFERENCE VOLTAGE (V)

V+ = 40V, IL = 0mA V+ = 20V, IL = 0mA V+ = 40V, IL = 20mA V+ = 8V, IL = 0mA V+ = 20V, IL = 20mA

5.00

4.98

V+ = 8V, IL = 20mA

4.96

AMBIENT TEMPERATURE

OUTPUT DEAD TIME (s)

V+ = 8V - 40V 10

FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION OF AMBIENT TEMPERATURE

5.1 V+ = 40V REFERENCE VOLTAGE (V) 4.9 4.7 4.5 V+ = 20V 4.3 4.1 3.9 V+ = 8V 3.7 3.5 0 8 16 24 32 40 48 56 64 72 80 REFERENCE OUTPUT CURRENT (mA) TA = +25oC V+ = 20V

1.0

0.1 0.0001

0.001

0.01

0.1

1.0

TIMING CAPACITOR, CT (F)

FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A FUNCTION OF TIMING CAPACITOR VALUE

FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION OF REFERENCE OUTPUT CURRENT

8 REFERENCE VOLTAGE (V) 7 6 5 4 3 2 1 0 0 10 20 30 40 SUPPLY VOLTAGE, V+ (V) TA = +25oC

If a small value of CT must be used, the pulse width can be further expanded by the addition of a shunt capacitor in the order of 100pF but no greater than 1000pF, from terminal 3 to ground. When the oscillator output pulse is used as a sync input to an oscilloscope, the cable and input capacitances may increase the pulse width slightly. A 2-K resistor at terminal 3 will usually provide sufcient decoupling of the cable. The upper limit of the pulse width is determined by the maximum duty cycle acceptable. The oscillator period is determined by RT and CT, with an approximate value of t = RTCT, where RT is in ohms, CT is in F, and t is in s. Excess lead lengths, which produce stray capacitances, should be avoided in connecting RT and CT to their respective terminals. Figure 5 provides curves for selecting these values for a wide range of oscillator periods. For series regulator applications, the two outputs can be connected in parallel for an effective 0-90% duty cycle with the output stage frequency the same as the oscillator frequency. Since the outputs are separate, push-pull and yback applications are possible. The ip-op divides the frequency such that the duty cycle of each output is 0-45% and the overall frequency is half that of the oscillator. Curves

FIGURE 3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION OF SUPPLY VOLTAGE

CA1524, CA2524, CA3524

of the output duty cycle as a function of the voltage at terminal 9 are shown in Figure 7. To synchronize two or more CAl524s, one must be designated as master, with RT CT set for the correct period. Each of the remaining units (slaves) must have a CT of 1/2 the value used in the master and approximately a 1010 longer RTCT period than the master. Connecting terminal 3 together on all units assures that the master output pulse, which occurs rst and has a wider pulse width, will reset the slave units.
105 TA = +25oC V+ = 8V - 40V CT = 0.001F CT = 0.002F CT = 0.005F 104 CT = 0.02F CT = 0.05F CT = 0.1F 103 1
10

The output amplier terminal is also used to compensate the system for ac stability. The frequency response and phase shift curves are shown in Figure 7. The uncompensated amplier has a single pole at approximately 250Hz and a unity gain cross-over at 3MHz. Since most output lter designs introduce one or more additional poles at a lower frequency, the best network to stabilize the system is a series RC combination at terminal9 to ground. This network should be designed to introduce a zero to cancel out one of the output lter poles. A good starting point to determine the external poles is a 1000-pF capacitor and a variable series 50-K potentiometer from terminal 9 to ground. The compensation point is also a convenient place to insert any programming signal to override the error amplier. internal shutdown and current limiting are also connected at terminal 9. Any external circuit that can sink 200A can pull this point to ground and shut off both output drivers. While feedback is normally applied around the entire regulator, the error amplier can be used with conventional operational amplier feedback and will be stable in either the inverting or non-inverting mode. Input common-mode limits must be observed; if not, output signal inversion may result. The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure 8. If the error amplier is connected as a unity gain amplier, a xed duty cycle application results.
TA = +25oC V+ = 20V OUTPUT DUTY CYCLE (%) 48 40 32 24 16 8 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 COMPARATOR VOLTAGE (V) CT = 2700pF RT = 6.19k fOSC = 60kHz

TIMING RESISTANCE, RT ()

CT = 0.01F 102 103 104

OSCILLATOR PERIOD, t (s)

FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION OF RT AND CT

Error AmplIfIer Section The error amplier consists of a differential pair (Q56,Q57) with an active load (Q61 and Q62) forming a differential transconductance amplier. Since Q61 is driven by a constant current source, Q62, the output impedance ROUT, terminal 9, is very high ( 5M). The gain is: AV = gmR = 8 lC R/2KT = 104,
ROUT RL

where R =

ROUT + RL

, RL = , AV 104

CT =1000pF RT = 5k fOSC = 20kHz

Since ROUT is extremely high, the gain can be easily reduced from a nominal 104 (80dB) by the addition of an external shunt resistor from terminal 9 to ground as shown in Figure 6.
80 70 RL = 3M VOLTAGE GAIN (dB) 60 50 40 0o RL = 1M RL = 300k RL =100k RL =

FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF COMPARATOR VOLTAGE (AT TERMINAL 9).
1.1

OUTPUT SATURATION VOLTAGE (V)

OPEN LOOP GAIN PHASE ANGLE (DEGREES) 90o OPEN LOOP PHASE 50

1.0

0.9

0.8

0.7 -75 -50 -25 0 25 50 75 100 125 150 175 AMBIENT TEMPERATURE (oC)

10

102

103 FREQUENCY (Hz)

104

105

FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE CHARACTERISTICS.

FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A FUNCTION OF AMBIENT TEMPERATURE.

CA1524, CA2524, CA3524

Output Section The CA1524 series outputs are two identical n-p-n transistors with both collectors and emitters uncommitted. Each output transistor has antisaturation circuitry that enables a fast transient response for the wide range of oscillator frequencies. Current limiting of the output section is set at 100mA for each output and 100mA total if both outputs are paralleled. Having both emitters and collectors available provides the versatility to drive either n-p-n or p-n-p external transistors. Curves of the output saturation voltage as a function of temperature and output current are shown in Figures 8 and 9, respectively. There are a number of output congurations possible in the application of the CA1524 to voltage regulator circuits which fall into three basic classications: 1. Capacitor-diode coupled voltage multipliers 2. Inductor-capacitor single-ended circuits 3. Transformer-coupled circuits The internal 5V reference can be used for conventional regulator applications if divided as shown in Figure 11. If the error amplier is connected as a unity gain amplier, a xed duty cycle application results.
VREF 5K 2 1 5K R1 GND VREF R1 5K 2 1 OUTPUT SATURATION VOLTAGE (V) 2.0 TA = +25oC V+ = 8V to 40V 1.5 GND 5K R2 NEGATIVE OUTPUT VOLTAGES + VO 2.5V (R1 + R2) R1 R2 POSITIVE OUTPUT VOLTAGES

+ -

R1R2 = 2.5KW R1 + R2

FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS

1.0

0.5 16 0 0 20 40 60 80 100 15 OUTPUT CURRENT, IL (mA) VREF

VT

CA1524 REFERENCE SECTION

FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A FUNCTION OF OUTPUT CURRENT

V+ CANNOT EXCEED 6V

Device Application Suggestions For higher currents, the circuit of Figure 10 may be used with an external p-n-p transistor and bias resistor. The internal regulator may be bypassed for operation from a xed 5V supply by connecting both terminals 15 and 16 to the input voltage, which must not exceed 6V.
Q1 IL TO IA DEPENDING ON CHOICE FOR Q1 16 VREF + 10F 8 GND 8 5K 9

NOTE: V+ Should Be in the 5V Range And Must Not Exceed 6V FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE REFERENCE REGULATION

To provide an expansion of the dead time without loading the oscillator, the circuit of Figure 13 may be used.

16

100 V+ 15

CA1524 REFERENCE SECTION

FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE CURRENT CAPABILITY

FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITHOUT USING A CAPACITOR ON PIN 3 OR WHEN A LOW VALUE OSCILLATOR CAPACITOR IS USED

CA1524, CA2524, CA3524

VO = 5V SA//SB
R1

TABLE 1. INPUT vs. OUTPUT VOLTAGE, AND FEEDBACK RESISTOR VALUES FOR IL = 40mA (FOR CAPACITOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)
VOR2 VTH + R1 + R2 WHERE

R2

IMAX = I RS
RS

VO (V) -0.5 -2.5 -3 -4 -5 -6

R2 (K) 6 10 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45

V+ (Min.) (V) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

5 + SENSE 4

ISC =

VTH RS

VTH = 200mV

FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED TO REDUCE POWER DISSIPATION UNDER SHORTED OUTPUT CONDITIONS
D1 V+ SA SB +VO V+ > VO

-7 -8 -9 -10 -11 -12 -13 -14 -15

D1 V+ SA SB V+ < VO +VO

-16 -17 -18 -19

D1 V+ SA SB | V+ | > | VO | -VO

-20
V+

VO

NOTE: Diode D1 Is Necessary To Prevent Reverse Emitter-Base Breakdown of Transistor Switch SA. FIGURE 15. CAPACITOR-DIODE COUPLED VOLTAGE MULTIPLIER OUTPUT STAGES
SA

SA-B FLYBACK VO V+

SA/SB V+ +VO

SB PUSH-PULL V+ > VO + VO SA V+ CAN BE SA OR SA CAN DRIVEQ1 Q1 CAN BE SB OR SB CAN DRIVEQ2 Q2

V+ SA/SB

+VO SB V+ < VO V+ SA/SB

V+

-VO | V+ | < | VO |

+ -

VO

FIGURE 16. SINGLE-ENDED INDUCTOR CIRCUITS WHERE THE TWO OUTPUTS OF THE 1524 ARE CONNECTED IN PARALLEL

FULL BRIDGE

FIGURE 17. TRANSFORMER-COUPLED OUTPUTS

10

CA1524, CA2524, CA3524 Applications (Note 1)

A capacitor-diode output lter is used in Figure 19 to convert +15VDC to -5VDC at output currents up to 50mA. Since the output transistors have built-in current limiting, no additional current limiting is needed. Table 1 gives the required minimum input voltage and feedback resistor values, R2, for an output voltage. Capacitor-Diode Output Circuit A capacitor-diode output lter is used in Figure18 to convert +15VDC to -5VDC at output currents up to 50mA. Since the output transistors have built-in current limiting, no additional current limiting is needed. Table 1 gives the required minimum input voltage and feedback resistor values, R2, for an output voltage range of -0.5V to -20V with an output current of 40mA. Single-Ended Switching Regulator The CA1524 in the circuit of Figure 19 has both output stages connected in parallel to produce an effective 0% 90% duty cycle. Transistor Q1 is pulsed on and off by these output stages. Regulation is achieved from the feedback provided by R1 and R2 to the error amplier which adjusts the on-time of the output transistors according to the load current being drawn. Various output voltages can be obtained by adjusting R1 and R2. The use of an output inductor requires an R-C phase compensation network to stabilize the system. Current limiting is set at 1.9 amperes by the sense resistor R3.
NOTE: 1. For additional information on the application of this device and a further explanation of the circuits below, see Intersil Application Note AN6915 Application of the CA1524 series PWM lC.

V+ +15V R2 15K 5K 1 5K 0.1F 2K 6 1 7 1 0.01F 3 1 10 1 8 1 2 1 R1 5K 16 1 12 1 IN4001 11 1 CA3524 13 1 14 1 4 1 5 1 9 1 0.01F IN4001 50F R1 = 5K R2 = R1 ( | VO | + 2.5) (VREF - 2.5) 20F IN4001 -5V 20mA 6 1

FIGURE 18. CAPACITOR-DIODE OUTPUT CIRCUIT

V+ +28V R2 5K 5K 5K 3K 6 1 7 1 0.02F 3 1 10 1 8 1 R1 5K 1 2 1 16 1 CA3524 0.9mH 15 1 12 1 11 1 2K 13 1 14 1 4 1 5 1 9 1 0.001F 50K 0.1 RURD410 2N6388 Q1 500F +5V IA

0.1F

V-

FIGURE 19. SINGLE-ENDED LC SWITCHING REGULATOR CIRCUIT

11

CA1524, CA2524, CA3524

Flyback Converter Figure 20 shows a yback converter circuit for generating a dual 15V output at 20mA from a 5V regulated line. Reference voltage is provided by the input and the internal reference generator is unused. Current limiting in this circuit is accomplished by sensing current in the primary line and resetting the soft-start circuit. Push-Pull Converter The output stages of the CA1524 provide the drive for transistors Q1 and Q2 in the push-pull application of Figure 21. Since the internal ip-op divides the oscillator frequency by two, the oscillator must be set at twice the output frequency. Current limiting for this circuit is done in the primary of transformer T1 so that the pulse width will be reduced if transformer saturation should occur. Low-Frequency Pulse Generator Figure 22 shows the CA1524 being used as a low-frequency pulse generator. Since all components (error amplier, oscillator, oscillator reference regulator, output transistor drivers) are on the lC, a regulated 5-V (or 2.5-V) pulse of 0% - 45% (or 0% - 90%) on time is possible over a frequency range of 150 to 500Hz. Switch S1 is used to go from a 5-V output pulse (S1 closed) to a 2.5-V output pulse (S1 open) with a duty cycle range of 0% to 45%. The output frequency will be roughly half of the oscillator frequency when the output transistors are not connected in parallel (75Hz to 250Hz, respectively). Switch S2 will allow both output stages to be paralleled for an effective duty cycle of 0%-90% with the output frequency range from 150 to 500Hz. The frequency is adjusted by R1; R2 controls duty cycle.

V+ +5V + 100F 25K 5K 2 1 5K 16 1 2K 6 1 7 1 0.02F 3 1 10 1 8 1 CA3524 13 1 14 1 4 1 5 1 9 1 + 0.001F 4.7F 2N2102 620 IN914 510 11 1 5K 1 15 1 300 12 1 1M 200 20T 0.1F

RURD620 +15V 50T 50T 50F -15V RURD620 2N6290 CORE: FEROX CUBE 2213P - A250 - 387 OR EQUIVALENT

50F

FIGURE 20. FLYBACK CONVERTER CIRCUIT

V+ +28V 5K 5K 5K 0.1F 5K 2K 6 1 0.01F 7 1 3 1 10 1 8 1 4 1 2N6292 5 1 9 1 0.001F 20K 0.1F + 100F RURD620 14 1 1 2 1 16 1 15 1 1K 1W 12 1 11 1 13 1 1K 20T 5T 1K 20T 5T + 1500F 5V 5A 1K 1W

2N6292

RURD620 1mH

FIGURE 21. PUSH-PULL TRANSFORMER-COUPLED CONVERTER

12

CA1524, CA2524, CA3524

+5 VREFERENCE

2K

TO PIN 9

1.1K

1.1K

R2 10K

DUTY CYCLE ADJUSTMENT

1 2 3

16 15 14 V+ = 9V

1/ S2 2 TO PIN 12 TO PIN 13 OUTPUT 1 OUTPUT 2

OUTPUT 1A 1.5K
1/ 2S1 1/ 2S2

2K

4 5 6

CA3524

13 12 11 10 9

OUTPUT 2A 1.5K
1/ 2S1

FREQUENCY ADJUSTMENT 20K

R1 50K 0.1F

7 8

SILVER MICA

TO PIN 1

SWITCH S1 S2

OUTPUT PULSES 0V - 5V -

DUTY CYCLE 0% - 45% 0% - 90%

FIGURE 22. LOW-FREQUENCY PULSE GENERATOR

The Variable Switcher The circuit diagram of the CA1524, used as a variable output voltage power supply is shown in Figure 23. By connecting the two output transistors in parallel, the duty cycle is doubled, i.e., 0% - 90%. As the reference voltage level is varied, the feedback voltage will track that level and cause the output voltage to change according to the change in reference voltage.

D1 AC IN D2

D3 36 VDC

2N6385 (PNP DARLINGTON) Q1 R2 1.5 10W 0.01F L1 20mH D5 RURD410 C3 10000F 100V C4 0.1F L2 50mH

7V - 30V 0A - 3A C5 25F VOUT

D4 5100F 100V

R1 1K 1W

NON-POLAR

D1-D4 - A15A

RETURN BIFILAR WINDING C6 25F NON-POLAR C7 0.1F R3 10K R6 2K 1 R7 10K R9 15K 1% R8 2K C8 0.1F C9 3300 pF 1% 2 3

16

15

14

13

12

11

10

9 R10 16K

CA1524
4 5 6 7 8

R4 5K

C11 0.01F C10 1100pF SILVER MICA

R5 2K

VOLTAGE CONTROL

fOSC = 20KHz

FIGURE 23. THE CA1524 USED AS A 0-5A, 7-30 V LABORATORY SUPPLY

13

CA1524, CA2524, CA3524

Digital Readout Scale The CA1524 can be used as the driving source for an electronic scale application. The circuit shown in Figures 24 and 25 uses half (Q2) of the CA1524 output in a low-voltage switching regulator (2.2V) application to drive the LEDs displaying the weight. The remaining output stage (Q1) is used as a driver for the sampling plates PL1 and PL2. Since the CA1524 contains a 5V internal regulator and a wide operating range of 8V to 40V, a single 9V battery can power the total system. The two plates, PL1 and PL2, are driven with opposite phase signals (frequency held constant but duty cycle may change) from the pulse-width modulator lC (CA1524). The sensor, S, is located between the two plates. Plates PL1, S and PL2 form an effective capacitance bridgetype divider network. As plate S is moved according to the objects weight, a change in capacitance is noted between PL1, S and PL2. This change is reected as a voltage to the ac amplier (CA3160). At the null position the signals from PL1 and PL2 as detected by S are equal in amplitude, but opposite in phase. As S is driven by the scale mechanism down toward PL2, the signal at S becomes greater. The CA3160 ac amplier provides a buffer for the small signal change noted at S. The output of the CA3160 is converted to a dc voltage by a peak-to-peak detector. A peak-to-peak detector is needed, since the duty cycle of the sampled waveform is subject to change. The detector output is ltered further and displayed via the CA3161E and CA3162E digital readout system, indicating the weight on the scale.

PL1 OSCILLATOR 20KHz (PART OF CA1524) S PL2 AC AMP CA3130 PEAK TO PEAK DETECTOR LOW PASS FILTER

DC VOLTAGE

COUPLED TO MECHANICAL SCALE MECHANISM FULL SCALE NO WEIGHT

DISPLAY DRIVE (PART OF CA1524)

DIGITAL METER AND DISPLAY

FIGURE 24. BASIC DIGITAL READOUT SCALE

2.5V 0.27 F 9 12 14 0.1 F 16

+5V

ZERO ADJUSTMENT

50K 8

POWER 2N2907 OR EQUIVALENT MSD NSD LSD COMMONANODE LED DISPLAYS (NOTE 1)

A B C 5 3 4 CA3162E DIGIT DRIVERS 11 HIGH INPUTS: LOW 10 13 GAIN ADJUSTMENT 10K 7 16 15 1 2 6 2 1 7 8 3 CA3161E 13 12 11 10 9 15 14

BCD OUTPUTS

NOTE: 1. FAIRCHILD FND507 OR EQUIVALENT

FIGURE 25. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE (CONTD)

14

CA1524, CA2524, CA3524

9V 10K 200pF 100F PL1 TO SCALE MECHANISM 39K 430K 30K 2N4037 125H 470F 200 4.7K 5V 9V 3 100 M 22M 22M 2 1 8 7 + CA3160 4 0.1F 6 68K 6.2K 10K 10F 300K 9V 2.5V A B C 2F 0.47 F 2F 910K 910K

S PL2

16 15 14 13 12 11 10 9

CA1524
4.7K

0.01F 24K 4700pF

4.7K 4.7K

6.2K

FIGURE 26. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE

DIMENSIONS AND PAD LAYOUT FOR CA3524RH CHIP NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The layout represents a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

15

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
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File Number 16

This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.