Hi ngh ton quc v iu khin v T ng ho - VCCA-2011

VCCA-2011
Cu hnh chip CNN gii bi ton thy lc mt chiu bng cng ngh FPGA

Config CNN Chip for Solving One-Dimension Hydraulic Equation
Using FPGA Technology

V c Thi, Bi Vn Tng
Trng i hc Cng ngh Thng tin v Truyn thng H Thi Nguyn
e-Mail: vdcthai@gmail.com; buitungbg@gmail.com
Phm Thng Ct
Vin Cng ngh Thng tin - Vin Khoa hc v Cng ngh Vit Nam
e-Mail: ptcat@ioit.ac.vn


Tm tt
Vic gii bi ton thy lc mt chiu c nhiu
ngi nghin cu v thc hin gii trn my PC,
tuy nhin tc tnh ton trn my PC l tun t
nn thi gian tnh ton ln. Cng ngh Mng n
ron t bo l mt kin trc tnh ton song song vt
l nn c tc tnh ton cc k nhanh. Bo co
trnh by qu trnh phn tch, thit k chip CNN
thc thi gii bi ton thy lc mt chiu. Kt qu
thc nghim cho thy u th tc tnh ton ca
cng ngh v chnh xc m bo yu cu thc
t. Bo co c 04 phn: Phn m u gii thiu m
hnh ton hc ca bi ton thy lc mt chiu; phn
hai phn tch m hnh bi ton theo thut ton
CNN; phn 3 thit k chip CNN thc thi tnh ton;
phn 4 kt qu thc nghim v nh gi thut ton,
gii php cng ngh.
Abstract: The problem of hydraulic channel
equation (HCE) is researched and solved by many
researchers on PC, however there are some
limitations in speed especially when we need to
process at high speed as in real time mode. In this
paper, we introduce the new method using CNN
technology, the model of physical paralelle
architecture for solving HCE. There are 4 parts in
this: Part 1: Introduction problem; part 2 analyse
problem following CNN algorithm; part 3 design
and implement computing; part 4 evaluate result
and technical solution.
K hiu:
K hiu n v ngha
h m cao mc nc
Q m
3
/s Lu lng nc
B m rng ca knh
I lch y knh
J H s nhm lng knh
S m
2
Din tch mt ct ngang knh
A, B, z Cc mu ca mng CNN
C, R
x
in dung, in tr trong mch
t bo Chua.
; x y Bc sai phn
n: S im tnh trn li sai phn
Ch vit tt:
CNN : Cellular Neural Network.
CNN 1D: CNN-One Dimension
FPGA: FIeld Programmable Gate Array.
LE: Logic Element.
DSP: Digital Signal Processing.
CLK: Clock.

1. Gii thiu bi ton thy lc mt chiu
Knh thy lc mt chiu v mt c hc l mt h
thng ng lc rt phc tp c nhiu tham s, trong
hai tham s quan trng m ta cn bit l cao
mc nc v lu lng dng chy [2,3]. nghin
cu, ta t knh vo h ta hai chiu: chiu
ngang dc theo dng knh, chiu dc l cao
dng knh. Cc tham s c quan h v mt ton hc
c biu din bng h phng trnh o hm
ring:
- Phng trnh bo ton khi lng:
( , ) ( , ) h x t Q x t
b q
t x
c c
+ =
c c
(1)
trong h l cao dng nc l hm ca v tr
im xt trn h ta
- Phng trnh ng lng
2
( , )
[ ]
( , ) ( , ) ( , )
( )
( , )
( , ) ( , )
( , )
q
Q x t
Q x t h x t S x t
gS xt
t x x
Q x t
gIS x t gJS x t k q
S x t
c
c c
+
c c c
+ =
(2)
trong Q l lu lng dng chy, cng l hm ty
thuc mi v tr trn dng knh. Cc tham s khc
trong hai phng trnh trn c lm r trong [4].
- iu kin ban u, iu kin bin ca cc
phng trnh (1) v (2)
Ti cng mt thi im ta o cc thng s Q, h ti
mt s im cn theo di dc theo chiu di knh
gi l cc iu kin ban u:
h(x=x
i
,t
0
) = h
0i
; Q(x=x
i
,t
0
) = Q
0i
;
(vi i=1..N)
2. Phn tch bi ton theo kin trc gii
trn CNN
97
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011

VCCA-2011
gii h phng trnh trn bng cng ngh CNN
chng ta phi phn tch bi ton, tm ra cc mu
thch hp, t thit k kin trc mng thc hin
tnh ton [4].
Vic phn tch m hnh ton hc ca mng CNN
da vo phng trnh trng thi [1]:
( , ; , ) ( , )
ij
( , ; , ) ( , )
( )
1
( ) ( , ; , ) ( )
( , ; , ) ( )
r
r
ij
xij ykl
C k l i j S i j x
ukl
C k l i j S i j
dv t
C v t A i j k l v t
dt R
B i j k l v t I
e
e
= + +
+

vi N j M i s s s s 1 ; 1
mc ch l tm ra tp mu A, B, z ca phng
trnh o hm ring ban u.
- Bin i phng trnh (1)
( , ) ( , ) h x t Q x t
b q
t x
c c
+ =
c c


1 h Q q
t b x b
c c
= +
c c
(3)
Sai phn v phi ca (3), ta c phng trnh sai
phn:

1 1
1
( )
2
i i
i i
h q
Q Q
t b x b
+
c
= +
c A

=>
1 1
2 2
i i i i
h Q Q q
t b x b x b
+
c
= +
c A A
(4)
Trong phng trnh (4) ta ch ch s (i) ni ln
phng trnh ny vit cho im sai phn th (i), v
tng ng vi t bo ti v tr i trong mng CNN.
(Tuy nhin cc t bo c cng phng trnh ton
hc m t, c cng mu, nn ta ch cn xc nh
mu cho mt t bo).
- tm mu cho bi ton, t phng trnh (4) v
phng trnh trng thi ca mng CNN 1D, gi s
chn: 1
h
C = ta c cc mu cho h:
1
[0 0]
h
h
A
R
=
;
1 1
[ 0 ]
2 2
hQ
A
b x b x

=
A A
;

1
[0 0]
h
B
b
=
; z
h
=0
- Xt phng trnh (2) :

2
( , )
[ ]
( , ) ( , ) ( , )
( , )
( , ) ( , )
q
Q x t
Q x t h x t bh x t
gbh x t
t x x
gIbh x t gJbh x t k q
c
c c
+ +
c c c
+ =

Bin i v cho gn chng ta khng vit cc
bin:
2
[ ]
( )
q
Q
Q h
bh
gbh gbh I J k q
t x x
c
c c
= +
c c c
(5)
Sai phn v phi (5), v v gi thit q>0 nn k
q
=0 ta
c:

2 2
1 1
1 1
1 1
1
( ) ( )
2 2
( )
i i i i
i i
i i
i
Q Q Q gbh
h h
t b x h h x
gb I J h
+
+
+
c
=
c A A


1 1
1 1 1
1 1
1
2 2 2
( )
2
i i i
i i i
i i
i
i i
Q Q gbh
Q Q h
bh x bh x x
gbh
h gb I J h
x
+
+
+
+
= +
A A A

A
(6)
Da vo thut ton tm mu ca CNN, t phng
trnh (6), chn C
Q
= 1, ta c cc mu:
1 1
1 1
1
[ ]
2 2
Q i i
Q
i i
Q Q
A
bh x bh x R
+
+

=
A A

[ ( ) ]
2 2
Qh i i
gbh gbh
A gb J I
x x

=
A A

B
Q
=0

; z=0;
gii bi ton ny ta thy c 2 n hm Q(x,t) v
h(x,t), mi hm l mt hm s hai bin khng gian
x v thi gian t, do vy x l bi ton chng ta
cn h CNN c 2 lp CNN 1D.



























3. Cu hnh chip CNN gii bi ton
thy lc mt chiu

Nh ta thy my tnh CNN-UM l mt kin trc
a nng, gii mi bi ton phi ch to mt phn
cng c kin trc ring [1]. Da trn cc mu tm
c, ta phi thit k, ch to kin trc chip CNN
thc thi tnh ton. Ty theo loi chip FPGA s
dng, ta cn c vo ti nguyn, c tnh ca mi
loi chip thit k cho ph hp vi yu cu tnh
ton (s lng t bo, s ln tnh, chnh xc...)
Trn th trng hin nay ph bin c hai hng sn
xut chip FPGA l Xinlinx v Altera. Nhm nghin
cu s dng loi chip Vertex 6 (XC6VLX240T-
1FFG1156) ca Xilinx. Ti nguyn ca chip
XC6VLX240T-1FFG1156 gm c 37,680 Slice
(tng ng vi 241,152 logic element -LE); 416
H. 2 Mch tnh ton cho mi t bo hm h(x,t); Q(x,t)

hi,t




B
h

q


+



A
hQ

Qi1


h i1



A
Q

Qi1


hi


A
Qh





+



/

Qi1


H. 1 Kin trc mch khi cho bi ton
dng chy mt chiu
Qi-1
Qi+1
hi-1 hi+1 hi
q
i

1
1
2
i
i
Q
b xh
+
+

A

-gb(I-J)

Qi
x 2
gbh
i
A

x 2
gbh
A

x b 2
1
A

x b 2
1
A

1 i
1 i
xh b 2
Q

A

q
i
k
q
1

1
b

98
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011

VCCA-2011
khi RAM36K tc truy xut 350 MHz; 768 khi
nhn 25x18 bit (DSP481) tc 275 MHz; 12 b
nhn/chia tn MMCM; s chn vo ra 600. Tc
xung ng h ti a c th cp cho chip l 700
MHz. Mt u im ca vic s dng chip ca
Xilinx l Xilinx cung cp nhiu khi chuyn dng
IP core s dng cho cc php ton s hc vi tc
tnh ton c th ti 1CLK/1 php ton. Chip Virtex
6 c tc nhanh v cu trc phn t LE ci tin
gip tit kim c nhiu cc phn t LE khi ci
t mt phn cng trn chip.
Theo thit k l gic mc (2) ta c mng hai lp
CNN 1D. Khi thit k mch phn cng, m bo
kin trc tnh ton song song nhm thit k theo
tng phn t mi phn t l mt cp tnh gi tr ca
h, Q. Nh trong Hnh 3 gi s khng gian tnh ton
cho n im ta c n phn t cho n cp (h,Q). Vi
kin trc ny ta cn rt nhiu ti nguyn nhng tc
tnh ton cc nhanh 07 xung CLK cho mt ln
tnh (vi chip XC6VLX240T-1FFG1156 khong
70 ns).



















Trong thc t, khi cu hnh ch to phn cng iu
quan trng l vic s dng ti nguyn trn chip. D
cng ngh FPGA hin nay c ti nguyn rt ln
nhng cng khng phi l v hn, v gi thnh ca
cc chip kch thc ln cng cn kh cao. Vi tnh
hnh c th nhm nghin cu thit k mt s m
hnh kin trc la chn.
3.1. M hnh x l tun t
M hnh ny chia khng gian tnh ton n im
thnh k khi tnh ton mi khi c (n/k) phn t,
cc khi tnh c kin trc ging ht nhau v tnh
ton song song vi nhau. Kin trc trong mt khi
c m t nh trong Hnh 4, (cc khi tnh ton
cng, tr, nhn, chia s hc c cu hnh t cc
phn t LE v DSP ca chip FPGA). Trong m
hnh ny ta thy sau khi a d liu vo thit lp
trng thi ban u cho t bo (ng vi cc iu kin
ban u ca phng trnh o hm ring), khi iu
khin (CU) gi cc khi tnh ton (Add, Mult, Div)
thc hin cc php ton s hc thc hin.
Cc khi x l s hc c th dng chung cho cc
phn t trong khi v c iu khin bi khi CU.
Gii php ny s dng t ti nguyn hn, ta chia
c nhiu khi song song. Vi chip
XC6VLX240T-1FFG1156 chia c khong 95
khi. Trong mi khi cc phn t thc hin tnh
ton tun t nn thi gian tnh ton chm (nu c
10 phn t thi gian tnh ton l 10 x 9 CLK = 90
CLK, khong 900 ns cho mt ln tnh).
















3.2. M hnh x l pipepline
Gii php ny cng chia khng gian tnh ton thnh
cc khi, tuy nhin trong mt khi s dng nhiu
khi tnh ton s hc hn nn gim vic dng
chung ti nguyn, (s nh trong Hnh 5). Do vy
gii php ny tn ti nguyn tnh ton (cng chip
XC6VLX240T-1FFG1156 chia c 24 khi), tuy
nhin tc tnh ton nhanh hn nhiu, phn t u
tin cn 7 CLK cho mt ln tnh ton cc phn t
sau ch cn 1 CLK, (nh vy, nu khi c 10 phn
t tc tnh ton l 7 + 9=16 CLK ).
























H. 3 Kin trc Chip CNN c cc khi t
bo tnh ton cho mt cp h,Q

T bo
1

h
0
h
1
h
2
h
1,
t
q
1,
t
q
2
q
1
q
0

T bo
i

h
i-
1
h
i
h
i+
1
h
i,t
q
i,t
q
i+
1 q
i
q
i-
1
H. 5 M hnh tnh ton Pipeline
Q
i,t
Mult
Mult
Add
Add
Sub
Div Div
Mult Mult
Add
Mult
Sub
Mult
Q
i-1
Q
i+1
h
i-1
h
i+1
Add
Mult
Add
Mult
Sub
h
i-1 h
i+1
h
i,t
H. 4 Kin trc mt t bo tnh ton
Add/Sub
h
i
h
i+1
h
i-1
Cc
thanh
ghi
TG
h
i-1
Q
i,t
h
i-1
, h
i+1

Q
i-1
, Q
i+1

h
i
h
i+1
h
i-1
Mult Div Control
99
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011

VCCA-2011
Ngoi cc khi tnh ton, ta cn phi s dng ti
nguyn lu tr d liu. Vi chip XC6VLX240T-
1FFG1156 ta s dng b nh RAM 36K c sn.
Mch tnh ton c thit k nh trong Hnh 6, d
liu a vo RAM qua my PC (dng file data)
hoc np trc tip t cm bin o. Trng hp thc
nghim y l np trc tip d liu vo RAM. C
6 u vo song song v cn 6 b nh RAM cho mi
cp t bo h,Q (ng vi cc gi tr bin trong
phng trnh sai phn h
i-1
;h
i
;h
i+1
;Q
i-1
;Q
i
;Q
i+1
) cho
php a d liu vo khi tnh ton tnh ton
c mt u ra cho i lng h,Q.



















gii quyt vn trn nhm s dng thm
thanh ghi dch cho 3 gi tr lin tc c d liu vo
khi tnh ton (Hnh 7). Gii php ny tit kim b
nh RAM ch thm c 02 xung ban u sau mi
ln c ch cn 1 xung).






















Tnh ton ti nguyn s dng cho vic cu hnh
chip
- Ti nguyn lu tr d liu
Mi phn t (h, Q) cn 32 bit lu tr, s bit nh
RAM ca vertex 6 l:
416 x36 Kb (1024 bit) = 15 335 424 bit
t ta tnh c s phn t (h, Q) c th thit k:
15335424
239, 616
2x32

- Ti nguyn dnh cho tnh ton
Ti nguyn ca chip s dng cho cu hnh mng
gm: 150,726 LUT; 301,440 REG;768 DSP.
Ta c hai gii php nh phn tch trn, nhm
chn gii php Pipelines lm thc nghim.
Nh tnh ton trn ta c th cu hnh c 24 khi,
mi khi khong 10 000 phn t (h,Q), tnh c
cho khng gian 24x10 000 l 24 000 im. Tc
tnh ton ht (7+49) CLK = 56 CLK (560 ns) cho
mt ln tnh. Thc t, nhm thc nghim tnh
ton cho 500 im, 50 ln tnh; khng gian tnh
ton l 500x50 tng ng vi dng sng di 250
km, tnh ton cho 500 im dc theo chiu di,
khong cch gia hai im tnh l 500 m.

4. Kt qu thc nghim

Nhm nghin cu cu hnh v tnh ton trn chip
XC6VLX240T-1FFG1156, h thng kt ni gia
my PC v chip nh trong Hnh 8.





Hnh 9 cho thy kt qu tnh ton trn khng gian
tnh ton cho 500x50 ca cao mc nc h.





Hnh 10 l kt qu tnh ton lu lng mc nc Q
H. 6 Ghp gia khi tnh ton v b nh RAM
M36K
RAM h
Qi
Qi-1
Qi+1
hi
hi-1
hi+1
Q3
Q2
Q1
Q0
Qk-2
Qk-1
Control
T
1

M36K
RAM Q
h3
h2
h1
h0
hk-2
hk-1
H. 7 S mch CNN ti u dng thanh ghi dch
Q
3

Q2
Q1
Q0
Qk-2
Qk-1
Control

T
1

TG
dch
M36K
RAM h
M36K
RAM Q
Qi+1
Qi
Qi-1
h3
h2
h1
h0
hk-2
hk-1
hi+1
h
i

hi-1
TG
dch
H. 8 H thng thit b thc nghim
H. 9 Hnh nh kt qu tnh ton ca h
100
Hi ngh ton quc v iu khin v T ng ho - VCCA-2011

VCCA-2011




5. Kt lun
Bi bo gii thiu gii php phn tch thit k v
cu hnh chip CNN gii bi ton thy lc chiu.
Thng qua vic thc nghim, nhm nghin cu
khai thc tt ti nguyn ca chip XCVL240T-
1FFG1156 thc thi thut ton CNN ng dng
gii phng trnh o hm ring. T m hnh ny,
c th d dng pht trin cho cc bi ton tnh ton
ng dng khc. Tip theo nhm s pht trin cho
mt s bi ton phc tp hn.

Ti liu tham kho
[1] Chua, L.O.; Yang, L.: Cellular Neural
Networks: Theory. IEEE Trans. Circuits Syst.
Vol.35, 1998.
[2] Ouarit, H.; Lefvre, L.; Georges, L.;
Begovich, O.: A Way to Deal with Nonlinear
[3] Boundary Condition in Open-Channel
Optimal Control Problems. Proceeding of the
42nd IEEE Conference on Decision and
Control Maui, Hawaii USA, 2003.
[4] Georges, D.; Dulhoste, J. F.; Besancon, G.: A
note on feedback Linearizing Control for
Open-Channel Hydraulic System. Conf. on
Control Application Glasgow, Scotland UK,
2002.
[5] Thai, V.D.; Cat, P.T.: Solving Saint Venant
Equation Describing an Open Hydraulic
Channel Employing Cellular Neural Network.
Proceeding of 13th International Conference
on Mechatronics Technology (ICMT2009),
Cebu, Philippines, 2009.
[6] Thai, V.D.; Cat, P.T.: Equivalence and
Stability of Two-layer Cellular Neural
Network Solving Saint Venant 1D Equation.
Proceeding (ISI) of 11
th
International
Conference on Control, Automation, Robotics
and Vision (ICARCV2010), Singapore. Trn
website: http://IEEE.explorer.com.








V c Thi sinh nm
1964, nhn bng C nhn
khoa hc ti HSP H
Ni 1 nm 1987. Nhn
bng K s CNTT ca
trng HBK H Ni nm
2000. Nhn bng Thc s
Khoa hc my tnh nm
2002.

Bt u cng tc ti trng HSP thuc H Thi
Nguyn, nay ang cng tc ti trng i hc Cng
ngh thng tin v Truyn thng-H Thi Nguyn.
ang l NCS ti Vin CNTT-Vin KH&CN Vit
Nam, vi ti nghin cu v cng ngh mng n
ron t bo ng dng trong vic gii phng trnh vi
phn o hm ring.

Bi Vn Tng sinh nm
1984, nhn bng K s
CNTT ca trng i hc
CNTT&TT - i hc Thi
Nguyn nm 2007.
ang cng tc ti khoa
iu khin t ng ha,
trng i hc Cng ngh
thng tin v Truyn thng
thuc i hc Thi Nguyn. L hc vin Cao hc
ti i hc Bch Khoa H Ni.

Pham Thuong Cat is a
Honorary Research
Professor in Computational
Sciences of Computer and
Automation Research
Institute of the Hungarian
Academy of Sciences. He is
the Editor-in-Chief of the
Journal of Computer Science and Cybernetics of
the Vietnamese Academy of Science and
Technology (VAST) and a Senior Researcher of the
Institute of Information Technology of VAST. He
is the representative of the Vietnam NMO at the
International Federation of Automatic Control
(IFAC) and the Vice President of the Vietnamese
Association of Mechatronics. His research interests
include robotics, control theory, cellular neural
networks and embedded control systems. He co-
authored 3 books and published over 140 papers on
national and international journals and conference
proceedings.





H. 10 Hnh nh kt qu tnh ton ca Q


101