EECE 412/612: Digital Integrated Circuits: Dept. of Electrical and Compute Engineering American University of Beirut

EECE 412/612: Digital Integrated Circuits
Mohammad M. Mansour Dept. of Electrical and Compute Engineering American University of Beirut Lecture 14: Power
Prof. M. Mansour
Where Does Power Go in CMOS?

Dynamic or Active or Switching power
Charging/discharging capacitors
Leakage power
Transistors are imperfect switches
Short-circuit power
Both pull-up and pull-down on during transition
Static power (static currents)

Biasing currents, in e.g. analog, memory
Prof. M. Mansour
Why Power Matters

Packaging costs Power supply rail design Chip and system cooling costs Noise immunity and system reliability Battery life (in portable systems) Environmental concerns
Office equipment accounted for 5% of total US commercial energy usage in 1993 Energy Star compliant systems
Prof. M. Mansour
Why worry about power? -- Standby Power

Year Power supply Vdd (V) Threshold VT (V)
2002 1.5 0.4
2005 1.2 0.4
2008 0.9 0.35
2011 0.7 0.3
2014 0.6 0.25
Drain leakage will increase as VT decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption.
50% 40%
8KW 1.7KW 400W 12W 88W
and phones leaky!
Standby Power
30% 20% 10% 0%
Source: Borkar Intel
2000 Prof. M. Mansour
2002
2004
2006
2008 4
Power and Energy Figures of Merit

Power is the rate at which energy is delivered or exchanged Power dissipation is the rate at which energy is taken from the source (Vdd) and converted into heat
Electrical energy is converted into heat energy during operation
Average power consumption in Watts

Determines battery life in hours
Peak power
Determines power-ground wiring designs Sets packaging limits Impacts signal noise margin and reliability analysis
Energy efficiency in Joules

Rate at which power is consumed over time
Energy = power * delay

Joules = Watts * seconds Lower energy number means less power to perform a computation at the same frequency
Also, there is energy-delay product (EDP)

EECE 412/612: Digital Integrated Circuits 5
Prof. M. Mansour
Power versus Energy

Power is height of curve Watts Lower power design could simply be slower Approach 1 Approach 2 Energy is area under curve Two approaches require the same energy Approach 1 Approach 2 time
Prof. M. Mansour EECE 412/612: Digital Integrated Circuits 6
time
Watts
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t +T 1 t +T Pave = p (t )dt = t isupply (t )dt T t T
Prof. M. Mansour
Energy Dissipation: A First-Order RC Network
Energy taken from source:
Energy stored in cap:
Energy dissipated in R ??
I - Dynamic Energy and Power Consumption
Prof. M. Mansour
Dynamic Energy Consumption
Dynamic energy dissipation due to charging and discharging capacitances:

For a 0 1 transition: CLVdd2/2 is stored in CL, and CLVdd2/2 is dissipated in PMOS. (One half of the energy from the supply is consumed in the pull-up network, one half is stored on CL) For a 1 0 transition: CLVdd2/2 is dissipated in NMOS transistor (Energy from CL is dumped during the 10 transition)
Hence, per 0 1 output transition, CLVdd2 is consumed from supply.

EECE 412/612: Digital Integrated Circuits 10
Prof. M. Mansour
Circuits with Reduced Swing
Prof. M. Mansour
11
Dynamic Power Consumption

Dynamic power dissipation due to charging/discharging capacitances with time: Need to take into account how often the device is switched Let f01 denote the frequency of 0 1 transitions Dynamic Power = Energy/transition Transition rate = CLVDD2 f01 = CLVDD2 f P01 = CswitchedVDD2 f Power dissipation is data dependent depends on the switching probability Switched capacitance Cswitched= CL P01 Note that Pdyn is independent of transistor sizes (almost)
Prof. M. Mansour
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Transition Activity and Power

Energy consumed in N cycles, EN:
EN = CL VDD2 n01.
n01: number of 01 transitions in N cycles
P01
Pavg = P01 CL VDD2 f
Prof. M. Mansour
13
Examples
Example: Assume a 0.25 um CMOS chip is clocked at 500 MHz and an average load capacitance of 15 fF/gate, assuming a fan-out of 4. At 2.5V power supply, what is the power consumption assuming the chip contains 1 million gates? Assume that a transition occurs at each clock cycle.
Pdyn = 15 10 15 106 2.52 500 106 = 46.9 Watts
In reality, not all 1 million gates switch every cycle. Example: Capacitive power dissipation of an inverter Consider an inverter whose delay is 32.5ps when driving a 6 fF load. For a supply voltage of 2.5 V, the energy needed to (dis)charge the load is
2 Edyn = C LVdd = 37.5 fJ
Assume the inverter is switched at the maximum possible rate, what is its dynamic power dissipation?
Maximum switching rate f = Pdyn = Edyn f = 580W 1 2 32.5 10 12
Prof. M. Mansour
14
Summary: Dynamic Power Consumption

Vdd
Vin CL
Vout
Energy/transition = CL * VDD * P01

2
f01
Pdyn = Energy/transition * f = CL * VDD2 * P01 * f Pdyn = Cswitched * VDD2 * f where Cswitched = P01 CL
Not a function of transistor sizes! Data dependent - a function of switching activity!

NOR Gate Transition Probabilities

Switching activity is a strong function of the input signal statistics
PA and PB are the probabilities that inputs A and B are one => (1-PA) and (1-PB) are the probabilities that inputs A and B are zero
A B 0 0 0 1 1 0 1 1
F 1 1 1 0
A B A B F CL
0 PA 1 0 PB 1
P0 = PA x PB P1 = (1-PA) x (1-PB) + (1-PA) x PB + PA x (1-PB) = 1 P0 = 1 - PA x PB P01 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)

Prof. M. Mansour
16
Lowering Dynamic Power
Capacitance: Function of fan-out, wire length, transistor sizes
Supply Voltage: Has been dropping with successive generations
Pdyn = CL VDD2 P01 f
Activity factor: How often, on average, do wires switch?
Clock frequency: Increasing
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II - Short Circuit Power Consumption
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Short Circuit Power Consumption

Finite input slope
Vin
Isc CL
Vout
Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.
Short Circuit Currents
Like we did for active power, introduce activity factor
Typically, sc is lumped with 0->1.

Impact of CL on Psc
Isc 0 Vin Vout CL Large capacitive load Output fall time significantly larger than input rise time.
Vin rise time is smaller than Vout fall time As PMOS turns off, |VDS,P| rises slowly. By the time |VDS,P| reaches Vdd, PMOS has turned off
Isc Imax Vin Vout CL Small capacitive load Output fall time substantially smaller than the input rise time.
Vin rise time is greater than Vout fall time As PMOS turns off, |VDS,P| drops quickly. |VDS,P| stays > 0 for a long period of time until PMOS turns off, hence consuming short circuit current
21
Prof. M. Mansour
Ipeak as a Function of CL
When load capacitance is small, Ipeak is large. CL = 20 fF CL = 100 fF CL = 500 fF
4
x 10-4
2.5 2 1.5 1 0.5 0 0 -0.5 2
time (sec) 500 psec input slope
x 10-10
Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.
Prof. M. Mansour
22
Psc as a Function of Rise/Fall Times

When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc
normalized wrt zero input rise-time dissipation

8 7 6 5 4 3 2 1 0 0 2 4
VDD= 3.3 V VDD = 2.5 V VDD = 1.5V tsin/tsout
If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time.
W/Lp = 1.125 m/0.25 m W/Ln = 0.375 m/0.25 m CL = 30 fF

CMOS Energy & Power Equations

Etot = (CL VDD2 + tsc VDD Ipeak ) P01 + VDD Ileakagetoff
f01 = P01 * fclock

Ptot = (CL VDD2 + tscVDD Ipeak ) f01 + VDD Ileakage
(P01 = Probability of 0 to 1 transition)
Dynamic power
Short-circuit power Leakage power
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III - Leakage Power Consumption
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Transistor Leakage
Transistors that are supposed to be off actually leak
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Leakage (Static) Power Consumption

Pleakage= VDD Ileakage Main sources of leakage power
1. Leakage current flowing in reverse biased junction diodes 2. Sub-threshold current in transistors when VGS < VT. 3. Gate leakage current
Vout

Gate leakage
Drain junction leakage
Sub-threshold current
Sub-threshold current is the dominant factor.

All components increase exponentially with temperature!
Prof. M. Mansour
27
Reverse-Biased Diode Leakage

Example:
Leakage current per unit drain area at room temperature is 10-100pA/um2. For a die with 1 million gate, with a drain area of 0.5um2 and Vdd=2.5V, the worst case power consumption due to diode leakage is 0.125W. Not much. However, leakage current increases exponentially with temperature.
GATE
p+
p+ N
Reverse Leakage Current +
V - dd
IDL = JS A
JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS JS doubles for every 9 deg C!
Prof. M. Mansour
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Leakage as a Function of VT
Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation. Downscaling Vdd without scaling Vt will negatively affect performance.
An 90mV/decade VT roll-off - so each 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance)
Prof. M. Mansour
29
Sub-Threshold Conduction (vs. VGS)

Sub-threshold Current:
ID I0 exp q (VGS VT )/ nkT , n = 1 + CD C ox
Inverse sub-threshold slope (S-1):

S 1 = VGS when ID2 / ID1 = 10 kT = n ln(10 ) q
Typical values for S-1 60 .. 100 mV/decade
Prof. M. Mansour
30
Transistor Leakage vs. VDS
Two effects:
Diffusion current (like a bipolar transistor) Exponential increase with VDS (: DIBL)
TSMC Processes Leakage and VT

CL018 G Vdd Tox (effective) Lgate IDSat (n/p) (A/m) Ioff (leakage) (A/m) VTn FET Perf. (GHz) 1.8 V 42 0.16 m 600/260 CL018 LP 1.8 V 42 0.16 m 500/180 CL018 ULP 1.8 V 42 0.18 m 320/130 CL018 HS 2V 42 0.13 m 780/360 CL015 HS 1.5 V 29 0.11 m 860/370 CL013 HS 1.2 V 24 0.08 m 920/400
20
1.60
0.15
300
1,800
13,000
0.42 V 30
0.63 V 22
0.73 V 14
0.40 V 43
0.29 V 52
0.25 V 80
From MPR, 2000
Prof. M. Mansour
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Exponential Increase in Leakage Currents
10000
1000
Ileakage(nA/m)
100
0.25 0.18 0.13 0.1
10
1 30 40 50 60 70 80 90 100 110
From De, 1999 33
Temp(C)
Prof. M. Mansour EECE 412/612: Digital Integrated Circuits
IV - Static Power Consumption
Prof. M. Mansour
34
Static Power Consumption

Vdd
I stat V out CL
V in =5V
Pstat = P(In=1).Vdd . Istat

Wasted energy Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)
Prof. M. Mansour
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Summary: Energy & Power Equations

Etot = (CL VDD2 + tsc VDD Ipeak ) P01 + VDD Ileakagetoff
f01 = P01 * fclock

Ptot = (CL VDD2 + tscVDD Ipeak ) f01 + VDD Ileakage
(P01 = Probability of 0 to 1 transition)
Dynamic power (~60% today and decreasing relatively)
Short-circuit power (~10% today and decreasing absolutely)
Leakage power (~30% today and increasing)
Prof. M. Mansour
36

EECE 412/612: Digital Integrated Circuits: Dept. of Electrical and Compute Engineering American University of Beirut

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