QUESTION BANK

EC010 404: DIGITAL ELECTRONICS

Module I
Part A 1. What are the properties of Gray code? Write all gray codes 2. Convert the following decimal numbers into its equivalent binary 1) 625.05 2) 0.003901 3. Perform subtraction of binary number 10010 from 11001 using ones compliment and twos compliment method. 4. Using ones compliment and twos compliment method subtract 100110 -1101 5. Write the values of the following binary numbers in decimal system by considering it as both signed and unsigned number(use ones compliment for signed number): (1) 111011; (2) 010111 6. Perform binary subtraction using 2s complement and 1s complement methods100110000. 7. Explain how a function containing max. terms can be simplified using K-map. 8. State and explain Demorgans laws. Part B 9. What are signed binary numbers? Explain with examples. 10. Subtract using 1s complement and 2s complement method: 101011-10110. 11. Simplify + + ( + ) 12. Simplify the expression = + + + + + + 13. Express the Boolean expression = + in product of max. Terms. 14. Construct Karnaugh Map and simplify 1) = + + 2) = + + + 15. Prove that ( + )( + )( + ) = ( + )( + ) 16. Using Boolean algebra simplify the expressions 1) + + 2) + + + Part C 17. Find the minimal sop and POS for f=M0,2,4,10,11,13+dc(1,3,6) 18. Implement the following functions using 8:1 MUX 1) f= m(0,3,4,6,8,10,12,13)+dc(2,7) 2) f = M(0,3,5,6,7,10,11,13,14 ) 19. Apply De Morgans theorems to the following expressions and prove that 1) A+B+C=AC+BC 2) A+B+CD=ABC+ABD. 3) ( + ) + + = + +

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20. What are error detecting and correcting codes? Give examples and explain the processes. What are excess three codes? Write the excess-3 codes corresponding to the decimal 1 to 16. 21. Encode the following decimal numbers to BCD code 1) 640 2)372.98 3)20.301. Encode these numbers to Gray code. 22. A stair case light is controlled by two switches one at the top of the stairs and another at the bottom of the stairs 1) make the truth table for the system. 2) Write the logic equation in SOP form. 3) Realize the circuit using AND-OR gates 4) neither realize the circuit using only NOR gates. 23. Explain the even and odd parity schemes bringing out their Merits and demerits. Attach proper even parity bit to the following bytes of Date 1) 10100100 2) 00001001 3) 11111110 4) 10101010 24. Explain the features of excess-3 codes giving examples. What are its uses? Bring out the special features of hamming codes and their applications.

Module II
Part A 25. What do you mean by Positive and negative Logic. 26. Draw the circuit of a TTL NAND gate? 27. Explain briefly a CMOS NOT gate. 28. What do you mean by Active and Passive Pull up? 29. List out Various TTL sub families 30. Why ECL family is able to provide high speed. 31. Define Fan-in and Fan-Out and give typical values for TTL family. Part B 32. Explain wire-AND ing in TTL circuits and its applications. 33. Define noise margin, giving value for TTL. 34. Define Propagation delay of a logic gate. Compare the same for TTL and CMOS. 35. What are the advantages and disadvantages of totem pole Output? 36. Compare the power dissipation of various logic families. 37. Draw and explain the circuit diagram of CMOS NAND gate. 38. Draw and explain tri-state inverter. 39. How the use of Schotkey transistors improves the performance of TTL. 40. Describe the sourcing and sinking characteristics of a gate? Part C 41. Sketch and Explain the circuit diagrams and working of 1) non-inverting CMOS tristate driver with active high control and inverting CMOS tri-state driver with active low control. What are its applications? 42. Draw the circuit diagram of a 2-input NAND gate in TTL family and explain the working with the help of its truth table.
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43. Giving typical values, define and explain the following standard TTL NAND gate(i) Fan-in(ii)Fan-out(iii)noise margin(iv)Propagation delay(v)VoH(vi)VIH 44. Draw the circuit of an open collector AND gate and explain. What are its applications? 45. Draw the circuit of a CMOS NOR gate and explain its working. Compare CMOS and TTL gates 46. With a neat circuit diagram, Explain the working of a two input OR gate of CMOS logic family. 47. Discuss the various TTL sub families in Detail. 48. With the help of a neat diagram explain the working of an ECL NOT gate. 49. Compare any four properties of TTL and CMOS logic families. Explain a CMOS NAND gate. 50. Explain an ECL NOR/OR gate with help of a neat diagram. 51. Explain TTL Tristate inverter in detail.

Module III
Part A 52. Draw the symbol and truth table of NOR gate. 53. Design and draw a half adder using NAND gates only. 54. Explain the differences between a Latch and a flip-flop? 55. What is the principle of edge triggering? Why is it used? 56. Using 4:1 MUX, realize AND and OR functions. 57. Realize a Half adder using minimum number of NOR gates. 58. Why negative edge triggering is used in flip-flops? 59. Which are the universal gates? Why they are called so? 60. Realise a NAND gate using a 4:1 multiplexer. 61. Draw a full adder using half adders. Explain the working using truth tables. Part B 62. Explain what a level triggered flip flop is and for what purposes can it be used. Compare their operations with the edge triggered flip flops. 63. Distinguish between truth table and excitation table with reference to the JK flip flop. What are their uses? 64. State and explain any two practical applications of XOR gate. 65. Draw a NOR and OR gate functions using only NAND gates. 66. Draw the block diagram of a de-multiplexer and explain. What are its applications? 67. Draw the circuit of a half adder using NAND gates only. 68. Clearly explain race around problem. 69. Draw the excitation table of JK flip flop and explain the same. 70. What are the applications of XOR gates? 71. What are D-latches? What are its applications 72. Convert a RS flip flop to a T flip-flop
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73. With logic diagrams show how a JK flip-flop can be converted into (i) D flip-flop (ii) T flip-flop? Part C 74. Draw the truth table for a full adder. Design the minimal circuit using NAND gates only. 75. Draw the circuit diagram of a clocked master slave JK flip flop with preset and clear inputs and explain its working. 76. With logic diagram and table explain the working of an 8:1 multiplier. Distinguish between a multiplexer and encoder. 77. Sketch and explain the complete circuit of a negative edge triggered master slave JK flip flop with synchronous, asynchronous inputs. Use only fundamental logic gates. 78. Explain encoders and decoders with examples. What are their applications? 79. Draw the circuit of a parallel binary adder cum subtractor and explain its working. 80. Draw the circuit of a twos compliment adder cum subtractor and explain its working. 81. Draw the truth table of an MS JK flip-flop using NOR gates only and explain. Explain how racing can be avoided by MSJK. 82. What is a multiplexer? Explain 4 to 1 MUX with neat diagram. Implement the following function using 4 to 1 MUX = (0,1,3,5,8,9,12,14,15) 83. Design a full subtractor circuit using NAND gates only. Realise the above using a decoder. 84. With neat circuit diagram, explain the working of a carry propagation adder. Mention its merits and disadvantages. 85. Draw the truth table for a positive edge triggered JK flip-flop with waveforms and explain. Compare with RS flip flop.

Module IV
Part A 86. Compare and contrast Synchronous and Asynchronous counters. 87. Explain a 4-bit serial shift register. 88. What is a ring counter? What are its practical applications? 89. Explain any two distinct applications of shift registers. 90. Bring out the advantages and disadvantages of ripple counter compared to a synchronous counter. 91. Explain the principle and applications buffer registers. Part B 92. Explain how JK flip-flop act as bounce elimination switch. 93. Distinguish between latches and flip flops.

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94. Draw the circuit diagram, output sequence and timing diagram of a four bit Johnson counter. 95. Draw and explain the application of the ring counter with its timing diagram. 96. What are the differences between shift register and counter? Give one application each. 97. Explain a for bit serial shift register. Part C 98. Design a counter with irregular binary count sequence 1,4,3,2,5,0,6,1. Use T flip flops draw the wave forms. 99. Explain with diagrams 1) 4-bit bidirectional shift register and 2)4-bit ring counter. 100.Using T-flip flops, Design a counter with the following repeated binary sequence 0, 1, 3,7,6,4. 101. Draw the circuit of a ring counter and explain the working with the help of timing diagram. Show how you can make a four stage ring counter work as a divide by two counters and divide by four pulse divider. 102. What is a shift register? Write a neat circuit explain a 4 bit parallel in serial out , parallel out shift registers for different combination of inputs. 103. Design a mod-16 up counter using positive edge triggered JK flip-flops with minimal combinational logic circuits. Explain the circuit diagram with help of its timing diagrams. 104. Draw the circuit of a 4 bit shift-left and shift right register with mode control and explain its working. 105. With a neat circuit diagram, explain the working of a 4 bit universal shift register. 106. Design and develop a decade counter using JK master slave flip flops? What are the merits and demerits of a ripple counter over a synchronous counter? 107. Draw the circuit of a mod controlled up-down counter of a 4 bit using JK flip flops. Draw the timing diagrams and explain.

Module V
Part A 108. Distinguish between PLA and PAL. 109. What is meant by static hazards? Draw the circuit with a static 1 hazard and static1 hazard free circuit. 110. Write a note on VHDL. 111. Explain how hazards can occur in Logic gates. Part B 112. 113. 114. 115. Write a brief note on FPGA. Explain static and dynamic hazards Discuss about ASIC Write brief note on Programmable Logic devices
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116. Explain Dynamic and Essential Hazard. 117. What are registered and configurable PAL Part C 118.With the help of neat diagrams, explain the working of 1) FPGA and 2) CPLD. 119.Discuss various hazards in digital circuits. And what do you mean by hazard free combinational circuits. 120.Explain with neat diagrams , the architecture of GAL 121.Discuss PLAs and PAL. 122.Discuss how a logic function can be implemented using PLAs with an example. 123.Design an XS-3 to BCD converter using PLA and PAL. 124.Implement the following Boolean functions using PLA 1) (, , ) = (0,1,3,5) 2) (, , ) = (0,3,5,7) 125.Implement a full adder using PLA.

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