PE 926 Manualnew

Sethu institute of technology, Pulloor, Kariapatti
PE 926 Power Electronics & Drives Lab
PE926- POWER ELECTRONICS AND DRIVES LAB
Sl.No.
LIST OF EXPERIMENTS
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
Micro controller based speed control of Chopper fed DC motor. Micro controller based speed control of VSI fed three-phase induction motor. Micro controller based speed control of Stepper motor. Simulation of logic gates using VHDL and VERILOG HDL Programming Simulation of 4-1 Multiplexer using VHDL and VERILOG HDL Programming Simulation of ADDER using VHDL and VERILOG HDL Programming Simulation of FLIP-FLOP using VHDL and VERILOG HDL Programming Simulation Of Volts/ Hz control of 3-phase Induction Motor Simulation Of Chopper fed speed control of DC Motor Simulation Of Converter fed speed control of DC Motor
CIRCUIT DIAGRAM
MODEL GRAPH
S P E E D
DUTY CYCLE
EX.NO: 1
Micro controller based speed control of Chopper fed DC motor. AIM:

To study the operation of Micro controller based speed control of Chopper fed DC motor.
APPARATUS REQUIRED
SL.NO ITEMS 1. Micro controller based IGBT Chopper 2. 3. 4. 5. kit DC Motor Patch chords Digital Tachometer RPS RANGE
HP 30 V, 2 Amps
CONNECTION PROCEDURE
1. Connections are given as per the circuit diagram. 2. Switch ON the main supply to the controller unit. 3. In the PWM chopper select FWD/REV direction (duty cycle). 4. Now use Increment/ Decrement keys to increase or decrease the duty cycle from 0 to 100%. 5. After setting duty cycle press RUN\ STOP key. Now the driver output pulses are available at outputs H1, L1, H2, and L2. 6. Check the driver outputs for forward and reverse direction with regenerative braking. 7. Connect DC supply from RPS unit and Connect HP DC motor at load terminals.
FORWARD MOTORING:
SNO DUTY CYCLE() % SPEED (rpm)
REVERSE MOTORING
SNO DUTY CYCLE() % SPEED (rpm)
8. Switch ON the DC supply and driver outputs and observe the output voltage across the load. 9. Check the outputs for forward and reverse direction and also observe the speed variation as we vary the duty cycle. Also observe the change of direction of rotation when we change the direction.
RESULT:
Thus the operation of Micro controller based speed control of Chopper fed DC motor was studied and necessary graphs were plotted.
EX.NO:2
Micro controller based speed control of VSI fed Three phase induction motor.
AIM:
To control the speed of the 3 phase induction motor using IGBT power module(PEC 16HV2A) and digital inverter controller module (PEC16HV2B).
APPARATUS REQUIRED
SL.NO 1. 2. 3. 4. 5. 6. 7. 8. ITEMS PEC16HV2A Module PEC16HV2B Module 3 phase induction Motor 9 TO 15 Pin D cable Patch chords CRO Isolation Transformer AC Variac RANGE
0-230V
CONNECTION PROCEDURE
1. Connect the IGBT power module and controller module to the supply mains using power chords. 2. Connect 1 AC input source to the power module through a variac and isolation transformer(AC input terminals are provided in the back panel). 3. Connect DC source across the + ive and ive terminals provided at the front panel. 4. Interface PWM output from inverter controller to the power module using the 9-15 pin D cable. 5. Connect motor across 3 phase output terminals of the power module. 6. Connect sensor cable from the motor to the motor feedback input of the controller.
MODEL GRAPH
7
A C T U A L S P E E D
MODULATION INDEX
CONTROL VOLTAGE=
SNO PWM Toff (s) Ton (s)
EXPERIMENTAL PROCEDURE
1. Switch ON the power ON\OFF switch of the power module and the controller module. 2. If OC LED glows press reset switch in power module and then the controller module, now O.C LED gets Off. 3. Switch on the pulse ON\Off switch of controller module. 4. View the test point waveforms through CRO. 5. From the display select INVERTER MODE. 6. Select MULTIPLE PULSE. 7. Select SINE PWM. 8. Select V\F MODE. 9. Select OPEN LOOP\ CLOSED LOOP
OPEN LOOP CONTROL

1. 2. 3. 4. 5. Select OPEN LOOP control. Switch ON AC supply and by using variac set the voltage at 230V. Then using Increment/ Decrement keys set the frequency as well as the The motor will run in open loop at speed corresponds the set frequency. The actual speed of the motor will be displayed in the LCD.
modulation Index.
CLOSED LOOP CONTROL

1. 2. 3. In order to run the motor in closed loop reduce the speed to zero and reset If closed loop is selected in step.9 and the display is Kp= 0.10, Ki= 0.02 then Set the speed of the motor Increment/ Decrement keys. the module and follow the procedure. set speed and actual speed of sine PWM will be displayed.
OPEN LOOP SYSTEM:
SNO
ACTUAL
SET
MODULATION INDEX
SPEED(RPM) FREQUENCY(Hz)
CLOSED LOOP SYSTEM

SNO ACTUAL SET MODULATION INDEX
SPEED(RPM) FREQUENCY(Hz)
10
RESULT:
Thus the sine PWM inverter operation was studied using IGBT power module (PEC 16HV2A) and digital inverter controller module (PEC16HV2B) and necessary graphs were plotted.
11
EX.NO:3
12
Micro controller based speed control of Stepper motor.

AIM:
To interface stepper motor with 8051 microcontroller and control its speed.
APPARATUS REQUIRED
SL.NO 1. 2. ITEMS MICROCONTROLLER 8051 STEPPER MOTOR RANGE
ALGORITHM
1. 2. 3. 4. 5. Initialize the data for the motor rotation. Output the data. Initialize the delay for rotation. Decrement the count. Go to the starting address so that the program does not get terminated.
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PROGRAM
LABE L ADDRE SS 8200 8201 8202 8203 MNEMONICS MOV DPTR, #0A003H MOV A,#82 OP CODE 90 A0 03 74 14 COMMENTS CONTROL WORD REGISTER SET PORT A OUTPUT & PORT-B
8204 MOVX @ DPTR, A 8205 8206 8207 8208 L1 8209 820A MOVX @ DPTR, A 820B 820C 820D 820E 820F 8210 8211 8212 8213 8214 8215 8216 ACALL DELAY MOV A,#05H MOVX @ DPTR, A ACALL DELAY MOV A,#06H MOVX @ DPTR, A ACALL DELAY MOV DPTR, #0A000H MOV A,#90H
82 F0 90 A0 00 74 09 F0 51 1F 74 05 F0 51 1F 74 06 F0 51
INPUT MOVE CONTENT OF ACCUMULATOR TO DPTR SET PORT-A MOVE 09H TO ACCUMULATOR
MOVE ACCUMULATOR CONTENT TO DPTR CALL DELAY MOVE 05H TO ACCUMULATOR MOVE CONTENT OF ACCUMULATOR TO DPTR CALL DELAY MOVE 06H TO ACCUMULATOR MOVE ACCUMULATOR CONTENT TO DPTR CALL DELAY
15
8217 8218 8219 821A 821B 821C 821D 821E 821F 8220 8221 8222 8223 8224 8225 8226
MOV A,#0AH MOVX @ DPTR, A ACALL DELAY SJMP L1 MOV R1, #10H MOV R0, #FFH DJNZ R0,L2 DJNZ R0,L3
1F 74 0A F0 51 1F 80 EA 79 10 78 FF D8 FE D9 FA 16
MOVE 0AH TO ACCUMULATOR MOVE ACCUMULATOR CONTENT TO DPTR CALL DELAY SHORT JUMP TO 8209 MOVE 10H TO R1 REGISTER MOVE FFH TO R0 REGISTER DECREMENT AND JUMP ON NO ZERO TO L2 DECREMENT AND JUMP ON NO
DELAY L3 L2
8227
RET
22
ZERO TO L3 RETURN TO CALLING FUNCTION
FULL STEP SEQUENCE

STEP 1 2 3 4 1 SW1 OFF OFF ON ON OFF SW2 ON ON OFF OFF ON SW3 OFF ON ON OFF OFF SW4 ON OFF OFF ON ON
RESULT
Thus the stepper motor is interfaced with 8051 microcontroller and it is run in full step sequence.
AND GATE (7408) TRUTH TABLE A 0 0 1 1 TRUTH TABLE A 0 0 1 1 B 0 1 0 1 OUT 0 1 1 1 B 0 1 0 1 OUT 0 0 0 1
A out B
OR GATE (7432):
A B
o ut
NAND (= NOT AND) GATE (7400)
TRUTH TABLE A 0 0 1 1 B 0 1 0 1 OUT 1 1 1 0
A out B
NOR GATE (7402)
TRUTH TABLE
17
A B
out
A 0 0 1 1
B 0 1 0 1
OUT 1 0 0 0
XNOR (EXCLUSIVE NOR)
TRUTH TABLE A 0 0 1 1 B 0 1 0 1 OUT 1 0 0 1
A B
out
EX.NO: 4
Simulation of logical gates using VHDL and Verilog Programming

OBJECTIVE: 1.To simulate logical gates using xilinx. REQUIREMENT 1. Verilog HDL and VHDL software with both front-end and backend (Design entry, simulation) and programming. PROCEDURE
18
1. Click on the Project navigator icon on the desktop of your PC. Write the verilog HDL code, check syntax, and perform the functional simulation using Xilinx ISE Simulator 2. Create programming file. 3. Verify the result. PROGRAM (VERILOG) module vl2(c,d,e,g,h,a,b); input a,b; output c,d,e,g,h; and a1(c,a,b); or a2(d,a,b); nand a3(e,a,b); nor a4(g,a,b); xnor a5(h,a,b); endmodule PROGRAM (VHDL) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
SIMULATION RESULTS: VHDL:
VERILOG:
19
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity logu1 is port ( a,b : in STD_LOGIC; c,d,e,g,h : out STD_LOGIC); end logu1; architecture Behavioral of logu1 is begin c<= a and b; d<= a or b; e<= a nand b; g<= a nor b; h<= a xnor b; end Behavioral;
20
RESULT: Thus the logic gates are simulated using Xilinx and results were verified.
4 to 1 line Multiplexer
21
A 0 0 1 1
B 0 1 0 1
X X0 X1 X2 X3
1 to 4 line De-Multiplexer
A 0 0 1 1
B 0 1 0 1
OUT0 IN 0 0 0
OUT1 0 IN 0 0
OUT2 0 0 IN 0
OUT3 0 0 0 IN
EX.NO:5
Simulation of multiplexer and demultiplexer using Verilog HDL Programming

OBJECTIVE:
22
1.To simulate 4-1 multiplexer and demultiplexer using xilinx REQUIREMENT 1. Verilog HDL software with both front-end and backend (Design entry, simulation) and programming. PROCEDURE 1. Click on the Project navigator icon on the desktop of your PC. Write the verilog HDL code, check syntax, and perform the functional simulation using Xilinx ISE Simulator 2. Create programming file. 3. Verify the result. PROGRAM 4-1 MULTIPLEXER
module mux(y,d0,d1,d2,d3,s0,s1); input d0,d1,d2,d3,s0,s1; output y; reg y; always @ (d0 or d1 or d2 or d3 or s0 or s1) begin if( s0==0 && s1==0) y=d0; else if(s0==0 && s1==1) y=d1; else if( s0==1 && s1==0) y=d2; else y=d3; end endmodule
1-4 DEMULTIPLEXER
module demux1(y0,y1,y2,y3,d,s0,s1); input d,s0,s1; output y0,y1,y2,y3;
SIMULATION RESULTS:
23
4-1 MULTIPLEXER
1-4 DEMULTIPLEXER
reg y0,y1,y2,y3; always @ (d or s0 or s1 )
24
begin if( s0==0 && s1==0) y0=d; else if (s0==0 && s1==1) y1=d; else if ( s0==1 && s1==0) y2=d; else y3=d; end endmodule
RESULT: Thus the multiplexer and demultiplexer are simulated using Xilinx and results were verified.
D-FLIP FLOP
25
Clock clk clk clk
Input D X 0 1
Output Q No change 0 1
JK FLIP FLOP:
J 0 0 1 1
K 0 1 0 1
Q No Change 0 1 1
__ Q No Change 1 0 Toggle
Operation Hold (no change) Reset Set Toggle
EX.NO:6
Simulation of FLIPFLOP using Verilog HDL Programming
26
OBJECTIVE: To simulate J-K,D- FlipFlop using xilinx REQUIREMENT 1. Verilog HDL software with both front-end and backend (Design entry, simulation) and programming. PROCEDURE 1. Click on the Project navigator icon on the desktop of your PC. Write the verilog HDL code, check syntax, and perform the functional simulation using Xilinx ISE Simulator 2. Create programming file. 3. Verify the result. PROGRAM JK FLIP FLOP module dwd(clk,rst,j,k,q,qb); input clk,rst,j,k; output q,qb; reg q,qb; always @ (posedge(clk)or posedge(rst)) if(rst==1) begin q=0;qb=1; end else if(j==0&&k==0) begin q=q; qb=qb; end else if(j==0&&k==1) begin q=0; SIMULATION RESULTS: JK FLIP FLOP
27
D FLIP FLOP
qb=1; end
28
else if(j==1&&k==0) begin q=1; qb=0; end else begin q=qb; qb=q; end endmodule D FLIP FLOP module sdgg(clk,rst,din, dout); input clk,rst,din; output dout; reg dout; always @ (posedge(clk)or posedge(rst)) if(rst==1) dout=0; else dout=din; endmodule
RESULT: Thus the JK Flip Flop and D Flip Flop were simulated using Xilinx and results were verified.
HALF ADDER:
29

X

Sum
Y C a rry
TRUTH TABLE:
X Y 0 0 0 1 1 0 1 1
X Y Cin
SUM 0 1 1 0
U 1 1 A 3 2 7 4 8
CARRY 0 0 0 1
U 4 1 B 6 6 5 7 4 8 6
Sum
U 1 2 U 4 5 U 9 1 0
A 3
B7
U 4 0 8 6 1 2 8 9
3 A
Carry
1 4 0 7 5
C7
4 0 8 8
4 0 8
FULL ADDER
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
CIN 0 1 0 1 0 1 0 1
SUM 0 1 1 0 1 0 0 1
COUT 0 0 0 1 0 1 1 1
EX.NO:7
Simulation of ADDER using VHDL and Verilog HDL Programming

30
OBJECTIVE: To simulate ADDER using xilinx REQUIREMENT 1. Verilog HDL AND VHDL software with both front-end and backend (Design entry, simulation) and programming. PROCEDURE 1. Click on the Project navigator icon on the desktop of your PC. Write the verilog HDL code, check syntax, and perform the functional simulation using Xilinx ISE Simulator 2. Create programming file. 3. Verify the result. PROGRAM VERILOG HDL Full Adder:
module Fulladd(a,b,cin,s,cout); input a,b,cin; output s,cout; wire s1,t1,t2,t3; xor x1(s1,a,b), x2(s,s1,cin); and a1(t3,a,b), a2(t2,b,cin), a3(t1,a,cin); or b1(cout,t1,t2,t3); endmodule
HALF ADDER:
module Halfadd(a,b,s,c); input a,b; output s,c; xor x1(s,a,b); and a1(c,a,b); endmodule
SIMULATION RESULTS: FULL ADDER:

31
HALF ADDER:
VHDL
32
FULL ADDER:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fff1 is port(a,b,cin: in std_logic; s,cout: out std_logic); end fff1; architecture Behavioral of fff1 is begin s<= a xor b xor cin; cout<= (a and b) or(b and cin) or (cin and a); end Behavioral;
HALF ADDER:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hf1 is port( a,b:in std_logic; s,c:out std_logic); end hf1; architecture Behavioral of hf1 is begin s<= a xor b; c<= a and b; end Behavioral;
RESULT: Thus the ADDER circuit was simulated using VHDL and Verilog HDL Programming and the results were verified.
33
SIMULATION OF CLOSED LOOP VOLTS/ HZ CONTROL OF 3PHASE INDUCTION MOTOR
34
EX.NO: 8
Simulation Of Closed loop Volts/ Hz control of 3phase Induction Motor
OBJECTIVE: To simulate closed loop Volts/ Hz control of 3-phase Induction Motor using MATLAB. KNOWLEDGE REQUIRED 1. Operation of inverter fed Induction motor and its torque speed relationship. 2. MATLAB Software.
35
36
37
RESULT: Thus the closed loop Volts/ Hz control of 3-phase Induction Motor was simulated using MATLAB and the results were verified.
SIMULATION OF CLOSED LOOP SPEED CONTROL OF CHOPPER FED DC MOTOR
38
39
EX.NO: 9
Simulation Of Closed loop Speed control Of Chopper Fed DC Motor

OBJECTIVE: To simulate closed loop speed control of Chopper Fed DC Motor using MATLAB. KNOWLEDGE REQUIRED
40
1. Operation of chopper fed DC motor and its torque speed relationship. 2. MATLAB Software.
SIMULATION RESULTS: SPEED OUTPUT, TORQUE OUTPUT, ARMATURE CURRENT,
41
FIELD CURRENT
42
RESULT: Thus the closed loop speed control of Chopper Fed DC Motor was simulated using MATLAB and the results were verified.
SIMULATION OF CONVERTER FED SPEED CONTROL OF DC MOTOR
43
EX.NO:
10
Simulation Of Closed loop Speed control of Converter Fed DC Motor

44
OBJECTIVE: To simulate closed loop speed control of Convereter Fed DC Motor using MATLAB. KNOWLEDGE REQUIRED 1. Operation of converter fed DC motor and its torque speed relationship. 2. MATLAB Software.
SIMULATION RESULTS:
45
46
RESULT: Thus the closed loop speed control of Converter Fed DC Motor was simulated using MATLAB and the results were verified.
47

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Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

PE926- POWER ELECTRONICS AND DRIVES LAB

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Micro controller based speed control of Chopper fed DC motor. AIM:

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

SNO DUTY CYCLE() % SPEED (rpm)

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

SNO PWM Toff (s) Ton (s)

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

OPEN LOOP CONTROL

CLOSED LOOP CONTROL

OPEN LOOP SYSTEM:

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

CLOSED LOOP SYSTEM

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Micro controller based speed control of Stepper motor.

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

ZERO TO L3 RETURN TO CALLING FUNCTION

FULL STEP SEQUENCE

NAND (= NOT AND) GATE (7400)

TRUTH TABLE A 0 0 1 1 B 0 1 0 1 OUT 1 1 1 0

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

XNOR (EXCLUSIVE NOR)

TRUTH TABLE A 0 0 1 1 B 0 1 0 1 OUT 1 0 0 1

Simulation of logical gates using VHDL and Verilog Programming

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

SIMULATION RESULTS: VHDL:

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Sethu institute of technology, Pulloor, Kariapatti

PE 926 Power Electronics & Drives Lab

Simulation of multiplexer and demultiplexer using Verilog HDL Programming