A High-Level Simulink-Based Tool for FPAA Configuration.

***matlab
ABSTRACT
With the rapid increase in size and complexity of analog systems being implemented on field-programmable analogarrays (FPAAs), the need for synthesis tools is becoming a necessity. In this paper, we present Sim2spice, a tool that automatically converts analog signal-processing systems from Simulink designs to a SPICE netlist. This tool is the top level of a complete chain of automation tools. It allows signal-processing engineers to design analogsystems at the block level and then implement those systems on a reconfigurable-analog hardware platform in a matter of minutes. We will provide detailed descriptions of each stage of the design process, elaborate on a custom library of analog signal-processing blocks, and demonstrate several examples of systems automatically compiled from Simulink blocks to analog hardware. Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link.

ABSTRACT
Differential signaling has been widely used in high-speed interconnects. Signal integrity issues, such as inter-symbol interference (ISI) and crosstalk between the differential pair, however, still cause significant timing jitter and amplitude noise and heavily limit the performance of the differential link. The pre-emphasis filter is commonly used to reduce ISI but may potentially change the crosstalk behavior. In this paper, we first propose formulabased jitter and noise models considering the combined effect of ISI, crosstalk, and preemphasis filter. With the same set of input patterns, experiment shows our models achieve within 5% difference compared with SPICE simulation. By utilizing these formula-based models, we then develop algorithms to directly find out the input patterns for worst-case jitter and worst-case amplitude noise through pseudo-Boolean optimization (PBO) and mathematical programming. In addition, a heuristic algorithm is proposed to further reduce runtime. Experiments show our algorithms obtain more reliable worst-case jitter and noise compared with pseudorandom bit sequences simulation and, meanwhile, reduce runtime by 25 when using a general PBO solver and by 150 when using our proposed heuristic algorithm.

Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection ***********

ABSTRACT
The paper discusses a technique to perform efficient circuit reliability analysis of large analog and mixed-signal systems. The proposed method includes the impact of both process variations and transistor aging effects. The complexity of large systems is dealt with by partitioning the system into manageable subblocks that are modeled separately. These models are then evaluated to obtain the system specifications. However, highly expensive reliability simulations, combined with nonlinear output behavior and the high dimensionality of the problem is still a very challenging task. Therefore the use of fast function extraction symbolic regression (FFX) is proposed. This allows to capture the high-dimensional nonlinear problem with good accuracy. Also, an active learning sample selection algorithm is introduced to minimize the amount of expensive aging simulations. The algorithm trades of space exploration with function nonlinearity detection and model uncertainty reduction to select optimal model training samples. The simulation method is demonstrated on a 6 bit Flash ADC, designed in a 32nm CMOS technology. Experimental results show a speedup of 360 over existing aging simulators to evaluate 100 Monte-Carlo samples with good accuracy.

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits ABSTRACT
Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speedspecifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. An in-depth analysis of the body-bias-driven design theory is provided. It is complemented by an algorithm that enables fast reconstruction of the area-clock period tradeoff curve of the design. We validated these new concepts through industrial processor designs in 90-nm low-power CMOS. For standard- Vthimplementations, we observed performance-per-area improvements up to 40%, area and leakage reductions up to 30%, and dynamic power savings of up to 10% without performance penalties as a benefit from our proposed body-bias-driven design strategy. The benefits are larger for highVth implementations. In this case, we observed performance-per-area improvements up to 90%, area and leakage reductions up to 40%, and dynamic power savings of up to 25% without performance penalties.

Multi-DSP and -FPGA Based Fully-Digital Control System for Cascaded Multilevel Converters used in FACTS Applications*****

ABSTRACT
In this paper, a fully-digital controller based on multiple Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) Boards has been proposed for parallel-operated Cascaded Multilevel Converters (CMC) used in Flexible AC Transmission System (FACTS) applications. The proposed system is composed of a DSP based master controller in combination with a multiple number of Slave DSP Boards, FPGA Boards, microcontrollers, a Programmable Logic Controller (PLC), an industrial computer and their peripherals in interaction. Intercommunication of these digital controllers is achieved mainly through fiberoptic links, via synchronous serial data link wherever a high-speed, full duplex communication is needed, and via asynchronous serial communication interface wherever relatively slow communication speed is required. The proposed fully-digital control system has been implemented on a sample 11-level CMC based 154kV, +/-50 MVAr Transmission type Static Synchronous Compensator (T-STATCOM). Field test results have shown that the proposed fully-digital control system provides good transient response and steady-state characteristics for the overall system including protection and monitoring functions.

Embedded Analog Nonvolatile Memory With Bidirectional and Linear Programmability

ABSTRACT
Nonvolatile storage of analog values with floating-gate transistors has been useful for many applications. While most proposed analog nonvolatile memory devices employ electron tunneling to modify floating-gate charges, this brief presents an embedded analog nonvolatile memory device that employs only hot-carrier injections to achieve bidirectional programmability. Without using electron tunneling, the proposed circuit not only avoids multiplexing high-voltage signals but also facilitates direct storage of new data. In addition, each memory cell incorporates a simple inverter to make the programming process nearly linear, facilitating bidirectional and linear adaptability for neuromorphic systems. A prototype array of the analog memory has been fabricated with the standard CMOS 0.35- technology. The chip includes a simple on-chip comparator to program the analog memory accurately and automatically by negative feedback. The effective resolution is more than 8 bits over a dynamic range of 1.4 V. The intercell disturbance during programming and the data retention ability are also examined.

Robust VLSI circuit design & systems for sustainable society

ABSTRACT
In scaled VLSIs, a reliable robust circuit system is essential for the sustainable secure society. The threat to the VLSI system is caused by device, circuit or system issues. This forum provides an overview of the technical challenges as well as recent advances in circuit and system-level reliable VLSI technologies. The forum starts with the overview on the robustness and fault tolerance requirements for microcontrollers in automotive applications. The e-mobility and the new safety norm ISO 26262 affect future requirements on semiconductors. The second talk reviews recent trend of CMOS variability, followed by measured examples on static variations (process) as well as temporal variations (RTN, NBTI). Methods for variability characterization, minimization, and mitigation is also covered. The forum also has three presentations about reliable memory circuits. To enablehighdensity and low-power SRAMs with robust reliability and fault-tolerance, a variety of energy-efficient, variation-tolerant, and adaptive circuits are reviewed. Embedded nonvolatile memory (eNVM) has greatly contributed to the recent growth of MCU market. The current eNVM technologies for highly reliable applications and future directions such as STTMRAM and ReRAM are presented. The increase of SSD storage capacity drastically increases the total amount of circuits in memory chips inside SSDs. High relaiable SSD controller technologies such as the block device (sector unit Read/Write device) management and the error correcting code are presented. Then, the robust system design is presented. New approaches to thorough test and validation that scale with tremendous growth in complexity and cost-effective tolerance and prediction of failures in hardware during system operation are discussed. The sevnth talk overviews the reliability measures and CMOS failure mechanisms for analog circuits. Simulation techniques to predict performance degradation or device failure is also presented. This forum also - ighlights the channel coding system which is essential for information transmission and storage. Complex systems for wireless communications require elaborate techniques like iterative (turbo) decoding or advanced algebraic code constructions and decoding algorithms. Finally, the robust energy management is presented for sensor systems and data servers. As a component of energy management, voltage regulators are providing utility beyond power conversion. How voltage regulators play an import role in energy efficient conversion as well as providing information that will help systems manage themselves for maximum utility is discussed.

A Very Linear Low-Pass Filter with Automatic Frequency Tuning-----ABSTRACT

A Gm-C third-order Chebyshev low-pass filter with a novel switched capacitor frequency tuning technique for a zero-IF Bluetooth receiver has been designed. The frequency tuning scheme is simpler and has more relaxed specifications than conventional ones. Furthermore, a highly linear pseudo-differential transconductor with a compact feedback loop able to operate with low supply voltage has been used. This control loop holds the input transistors in triode region and provides high output resistance, keeping high linearity in a wide range of transconductance. The filter bandwidth is 0.5 MHz and the overall scheme consumes 1.1 mA from a 1.8-V supply. The measured third-order intermodulation (IM3) distortion of the filter for a 1 Vpp two-tone signal centered at 300 kHz is $-$65 dB.

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65nm CMOS Technology
ABSTRACT
This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm$^{2}$ it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.

Testable Path Selection and Grouping for Faster Than At-Speed Testing
ABSTRACT
Faster than at-speed testing provides an efficient way for testing of small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is managed to be applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing based on path delay fault (PDF) model and single path sensitization criterion. An effective testable path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

Constant Delay Logic Style

ABSTRACT
A constant delay (CD) logic style is proposed in this paper, targeting at full-custom highspeed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speedup of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64% (22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry lookahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.

A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects*****

ABSTRACT
Current-mode signaling (CMS) with dynamic overdriving is one of the most promising scheme for high-speed low-power communication over long on-chip interconnects. However, they are sensitive to parameter variations due to reduced voltage swings on the line. In this paper, we propose a variation tolerant dynamic overdriving CMS scheme. The proposed CMS scheme and a competing CMS scheme (CMS-Fb) are fabricated in 180-nm CMOS technology. Measurement results show that the proposed scheme offers 34% reduction in energy/bit and 42% reduction in energy-delay-product over CMS-Fb scheme for a 10 mm line operating at 0.64 Gbps of data rate. Simulations indicate that the proposed CMS scheme consumes 0.297 pJ/bit for data transfer over the 10 mm line at 2.63 Gb/s. Measurements indicate that the delay of CMS-Fb becomes 2.5 times its nominal value in the presence of intra-die variations whereas the delay of the proposed scheme changes by only 5% for the same amount of intra-die variations. Measurement and simulation results show that both the schemes are robust against inter-die variations. Experiments and simulations also indicate that the proposed CMS scheme is more robust against practical variations in supply and temperature as compared to CMS-Fb scheme.

A technique for low power testing of VLSI chips// ABSTRACT

Power consumption of a circuit is more in test mode than normal mode. The increased heat due to excess power dissipation can open up reliability issue due to electro-migration. In extreme conditions excess power consumption might even result in chip burn outs also. In this paper, we propose a scan flip-flop which helps to reduce the power consumption during test mode without affecting the functional mode requirements. The proposed scan flip-flop use the single latch double edge triggered flip-flop to perform the scanning during test by halving of number of cycles in the clock frequency. The proposed design of clock driving circuit for the scan flip-flop helps to use the same flip-flop during the normal mode for the specified clock frequency. This avoids the redesign of the circuit for normal mode while using the high speed proposed scan flip-flop. The usage of the proposed scan flip-flop reduces the silicon area by 30% 45% and the power dissipation by 25% 35%.

Reconsidering High-Speed Design Criteria for Transmission-GateBased MasterSlave Flip-Flops

ABSTRACT
In this paper we show that, when dealing with transmission-gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance inhigh-speed designs. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path. Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in thehigh-speed region.

Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management ABSTRACT
Level shifter circuits are used to interface multiple voltage islands in many modern ICs or Systems-on-Chip (SoCs). Single-supply level shifters are being used to reduce the power routing resources and minimize the routing congestion at the chip level. A single-supply bidirectional level shifter aimed at low voltage which offers a wide voltage range (SSWVRLS) is designed using standard commercial 90nm CMOS process. The proposed level shifter uses analog and digital circuit techniques to provide full voltage shifting range for any combination of supply voltages (VDDIN = VDD,VDDIN <; VDD or VDDIN >; VDD) in any step size (paper shows 25mv step) with no requirement for special low-V or highV devices, thus reducing the process cost. Post layout SPICE simulation comparison results show that proposed circuit is functional for full core supply voltage range (0.6V - 1.32V) compared to other published level shifters. The circuit was tested for robustness under process mismatch conditions by 1000 point global and local Monte Carlo simulations.

Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic Tuning ABSTRACT

This paper presents the design, analysis, and experimental verification of a self-calibrating current-reused 2.4-GHz direct-modulation transmitter for short-range wireless applications. The key contributions are the design/analysis of a stacked power amplifier (PA)/voltagecontrolled oscillator (VCO) architecture, the nonlinear frequency-dependent analysis of a Gilbert-cell-based root-mean-square detector, and an on-chip LC-tank calibration circuit that needs no analog-to-digital convertor (ADC)/digital signal processor. The stacked architecture reduces the number of required regulators, utilizes supply headroom effectively, and allows for an ``ADC-less'' calibration loop that can dynamically tune the PA center frequency by sensing the transmitted signal. The very nature of direct-modulation architecture obviates additional high-purity signal generators, reducing complexity and allowing online calibration. The system was implemented in TSMC 0.18 m CMOS, occupies 0.7 mm2 (TX) + 0.1 mm2 (self-tuning), and was measured in a QFN48 package on an FR4 PCB. Automatically correcting PA/VCO tank misalignment in this case yielded >4 dB increase in output power. With the automatic tuning active, the transmitter delivers a measured output power >0dBm to a 100- differential load, and the system consumes 22.9 mA from a 1.8-V core-circuit supply.

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures***** ABSTRACT

Dual supply voltage design is widely accepted as an effective way to reduce the power consumption of CMOScircuits. In this paper, we propose a comprehensive design framework that includes dual- scheduling, dual- allocation, controller synthesis as well as layout generation. In particular, we address a problem of high-level synthesis with objective of minimizing power consumption of storage units and multiplexers using dual- ; this is made possible by utilizing timing slack that is left in the data-path after operation scheduling. We use integer linear programming (ILP) and also provide heuristic algorithms to solve the dualregister and connection allocation. The physical layout of dual-circuits has to separate power rails of and cells from each other. We propose a voltage island based placement algorithm to relieve this restriction and allow more flexibility of placement. In experiments on benchmark designs implemented in 1.08 V (with Vddl of 0.8 V) 65-nm CMOStechnology, both switching and leakage power are reduced by 20% on average, respectively, compared to data-path with dualVdd applied to functional units alone. Detailed analysis of area and wirelength is performed to assess feasibility of the proposed method.

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures.**** ABSTRACT
Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimized RNGs, so they are not commonly used in real-world designs. This paper describes a type of FPGA RNG called a LUT-SR RNG, which takes advantage of bitwise XOR operations and the ability to turn lookup tables (LUTs) into shift registers of varying lengths. This provides a good resource-quality balance compared to previous FPGA-optimized generators, between the previous high-resource high-period LUT-FIFO RNGs and lowresource low-quality LUT-OPT RNGs, with quality comparable to the best software generators. The LUT-SR generators can also be expressed using a simple C++ algorithm contained within this paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in this paper, backed up by an online set of very high speed integrated circuit hardware description language (VHDL) generators and test benches.

Eliminating Performance Penalty of Scan

ABSTRACT
Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flipflop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.

NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias

ABSTRACT
Reliability and variability have become big design challenges facing submicron high speed applications and microprocessors designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for NBTI aging and process variations to improve the system reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on-chip analog controller. Post layout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be Silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on a circuit block case study, extracted from a real microprocessor critical path. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB improves the timing yield from 74.4% to 99.7% at zero aging time and from 36.6% to 97.1% at 10 years aging time. In addition, the proposed ABB increases the total yield from 67% to 99.5% at zero aging time and from 35.9% to 97.1% at 10 years aging time. Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process
ABSTRACT

For future scaling to the end of the ITRS roadmap, novel structures like FinFETs are required to improve electrostatic integrity of MOSFETs with gate lengths shorter than 35 nm [1-4]. Classic fully-depleted FinFETs with a high aspect ratio are not compatible with existing planar process flows. A Tri-Gate transistor has the advantage of being more compatible. It is even possible to produce low-profile Tri-Gates in parallel to planar MOSFETs [5], with shared Tri-Gate and planar implants and common-use of source/drain epi and dual band-edge metal gate workfunctions. This maintains the design flow, saves mask count, allows reuse of analog and high-voltage I/O designs, while exploiting Tri-Gates in high speed logic and low minimum voltage.

Ultra-low-power analog and digital circuits and microsystems using disruptive ultra-low-leakage design techniques
ABSTRACT

In this paper, we describe circuits and microsystems applications of a disruptive ultra-lowleakage designtechnique for drastically reducing the off current in CMOS analog and digital functions without reducing the functional performance. The technique uses a pair of sourceconnected n- and p-MOSFETs, implementing an auto-bias of the stand-by gate-to-source voltage of the nMOS transistor at a negative voltage and that of the p-device at a positive level, thereby reducing the off current towards its physical limits. Changing the gate and drain connections, we propose a series of ultra-low-power basic blocks : a 2-terminal diode, a 3-terminal transistor and a voltage follower. These blocks can be combined to yield a 7transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still highspeed performance, as well as high-efficiency power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.

Adaptive EPFL-EKV long and short channel MOS device models for Qucs, SPICE and modelica circuit simulation ABSTRACT
Equation-defined non-linear functional elements are important building blocks in the development of compact semiconductor device models. Current trends in compact device modeling suggest widespread acceptance among the modeling community of Verilog-A, for semiconductor device specification, model exchange and circuitsimulation. This paper outlines techniques for the development of adaptive EPFLEKV long and short channel MOSmodels which stress user selectable model features and diagnostic capabilities. Adaptive EPFLEKV nMOS modelsbased on Verilog-A and Modelica are introduced and their performance compared with simulation data obtained using the Quite universal circuit simulator (Qucs), SPICE and the Modelica simulation environment.

Analog design trends and challenges in 28 and 20nm CMOS technology** ABSTRACT
Market trends for Multimedia Application Processor go on pushing CMOS technology in nanometer range. This puts analog design community in a strange paradox with simultaneously big challenges and tremendous opportunities. Analog is more than ever a key ingredient of advanced SoC with high performances PLL, giga samples high speed serial links and embedded power management. Challenge appears while achieving very highlevel of analog performances in a non analog-optimized and moving environment, inducing design architecture change and development of new design methodology. Opportunities come when analyzing nanometer MOS device performances which are going beyond analog designer dreams. These tremendous performances open the door for new sets of applications such as embedded mmW, digitally boosted analog functions with new market opportunities. The talk will highlight this new analog era coming with nanometer technologies.

A high-performance configurable VLSI architecture for integer motion estimation in H.264********

ABSTRACT

A high-performance configurable integer motion estimation VLSI architecture based on parallelogram data matching pattern for H.264 is proposed in this paper. Through rational design for the data flow and processing module array, the memory traffic is reduced; data reusability in vertical direction is improved. Furthermore, the number of processing element is configured according to the area-speed requirement, data reusability in horizontal direction is controlled, and fast matching in large searching window is realized. The design is described with Verilog HDL, and is logic synthesized with Synopsys DC under SMIC 0.13nm process. With 300MHz clock frequency, when the PE number is the configured to 5, the search window size is 6565, the speed can reach 36 fps, which can meet the speed requirements of real-time high-definition video encoding (19201088@30fps).

Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications ABSTRACT

In this paper, the analog performance is reported for the first time for a double-gate (DG) n-type tunnel field-effect transistor (n-TFET) with a relatively small body thickness (10 nm), which shows good drain current saturation. The device parameters for analog applications,

such as transconductance gm, transconductance-to-drive current ratio gm/ID, drain resistance RO, intrinsic gain, and unity-gain cutoff frequency fT, are studied for DG n-TFET, with the help of a device simulator, and compared with that for a similar DG n-MOSFET. Although gmis lower, gm/ID is found to be higher in TFET, except for small values of the gate overdrive voltage, indicating that a TFET can produce higher gain at the same power level than a MOSFET. An extremely high RO and, hence, a high intrinsic gain are also observed for a TFET as compared with that for a MOSFET. A complementary TFET amplifier is found to have more than one order of magnitude higher voltage gain than its MOS counterpart. It is also demonstrated that the drain resistance and, hence, the device gain significantly degrade for increasing body thickness of a TFET.

High-performance implementation of a new hash function on FPGA

ABSTRACT
Skein has the advantages of higher security (resisting against traditional attacks), faster speed and selectable parameters. Therefore, it becomes a strong competitor for next generation secure hash algorithm standard (SHA-3) which will be used widely in communication and security for substitution of SHA-2. The problems of existing works lie in implementation for only one structure and lack detailed comparison of different structures. Based on analysis of the algorithm, we accomplished three structures (iterative, 4-unrolled and 8-unrolled) of Skein and ported the designs to FPGA respectively. Finally detailed analysis and comparison with our different structures and other implementations are provided from aspects of hardware resource and performance. The results show that our implementation has better performance and takes up less hardware resources than existing works under the same structure. Our implementation can meet the requirement of real-time and highperformance field.

At-speed Testing of Asynchronous Reset De-assertion Faults

ABSTRACT
In sub-threshold technology nodes, device failure due to timing related defects (setup & hold timing) is on rise due to extreme process variability and increasing use of voltage scaling techniques for achieving required performance. High coverage using stuck-at fault patterns, which can effectively screen static defects is no longer sufficient to control DPPM (Defective parts per million). High test coverage of timing defects that is induced by process variation is required for controlling DPPM. Lot of work has been done to find the ways to increase the delay test coverage of industrial circuits including the various methods to cover inter-domain clock faults but very little or no work is done on the ways to effectively cover the asynchronous reset paths to the memory registers for timing defects. In this paper we propose a novel methodology that allows us to effectively detect the failures induced by

timing defects on asynchronous reset path of the registers. This problem is further complicated by the fact that commercially available ATPG tools are not capable of generating test patterns due to modeling limitations. Results from 45nm industrial multimillion gates design is presented to illustrate the effectiveness of the proposed methodology.

0.5-V high-speed circuit designs for nanoscale SoCs Challenges and solutions
ABSTRACT
Some solutions are proposed and evaluated by simulation after the challenges facing the creation of 0.5-V nanoscale SoCs are clarified. First, the repair techniques and nanoscale FD-MOSFETs are discussed in terms of their Vt-variation. Second, 0.5-V dual-VDD dualVt logic circuits with gate-source reverse-biasing schemes are proposed. Third, a boosted word-voltage six-transistor (6-T) SRAM cell is evaluated with a 25-nm planar FD-SOI MOSFET and then a FinFET, revealing that the FinFET drastically improves the voltage margin and speed of the 6-T cell. Finally, the feasibility of a 0.5-V 25-nm SoC comprising a 1-Gb SRAM and 160-Mgate logic block is studied. We conclude that an SoC like this with a competitive speed while reducing the power to about one-tenth that of a conventional 1-V 32-nm CMOS LSI is possible, if the above-described devices and circuits are used and the within-wafer Vt-variations are stringently controlled and/or compensated for.