Thermal Oxidation Process Basics

Diffusion Process - Basic
AMK Site Training
Purpose
Equips new Diffusion engineers (< 1 year in STM) with basic process knowledge in diffusion. Equips non-diffusion dept experienced engineers with cross-functional knowledge.
AMK Site Training
Front-End Technology & Manufacturing
AMK Site Training

Page: 2
Objective
At the end of the course, participants should be able to: Explain the concepts of diffusion, oxidation and RTP processes Differentiate the differences among diffusion, oxidation and RTP processes. Explain some common defects in Diffusion List down some of the common metrology equipment used in Diffusion
AMK Site Training
AMK Site Training

Page: 3
Table of Contents
Topic 1: Basic Thermal processes Describe the thermal process overview Topic 2: Thermal oxidation Explain thermal oxidation of silicon & oxide thickness range Describe the growth mechanism of oxide Describe the function & application of oxide Explain the factors affect oxidation growth rate Describe furnace equipment and oxidation system Topic 3: Thermal Diffusion Explain diffusion concepts Understand thermal diffusion cycle Explain two major steps of diffusion Describe the Laws of diffusion Analyze the data curve on Solid solubility of impurity in silicon
AMK Site Training
AMK Site Training

Page: 4
Table of Contents
(Cont.)
Topic 4: POCL3 Deposition Explain N type doping & N type dopants Describe the liquid source doping system Describe the solid source doping system Topic 5: Boron Deposition Explain P type doping & P type dopants Describe the type of solid source boron process Describe the solid source doping system Topic 6: Rapid Thermal Processing (RTP) Understand the overview of RTP Understand the RTP thermal cycle Explain the RTP System Describe the RTP application
AMK Site Training
AMK Site Training

Page: 5
Table of Contents
(Cont.)
Topic 7: Common Diffusion Defects Oxidation Defects POCL3 Defects Boron Defects Topic 8: Metrology Tool in Diffusion Explain the thermal process & quality parameters Familiarize the film thickness measurement tool and concept Understand the Surface Photo Voltage (SPV) tool and concept Understand the capacitance voltage (C-V) measurement and concept Understand sheet resistance and concept Describe Spreading Resistance Probe Analyze the SRP Profile
AMK Site Training
AMK Site Training

Page: 6
Course Agenda Outline

Topic Pre-Quiz/ Ice Breaker 1 2 3 4 5 6 7 8 9 Basic Thermal Processes Thermal oxidation - BREAK Thermal Diffusion POCL3 Deposition Boron Deposition Rapid Thermal Processing BREAK Common Diffusion Defects Metrology Tool in Diffusion Wrap-Up: Q&A, Evaluation, Post-Quiz Total Time: Content Duration (mins) 10 20 60 20 20 20 20 15 5 10 20 20 240 mins = 4 hrs
AMK Site Training
AMK Site Training

Page: 7
Topic 1: Basic Thermal Processes
AMK Site Training
AMK Site Training

Page: 8
Thermal Process Overview

Silicon wafer is subjected to heat treatment at elevated temperatures (350 ~ 1260 under various types o f C C) ambient and conditions. This treatment is called Thermal process. It is usually carried out in either the furnace (horizontal or vertical) with atmospheric or low pressure, or the Rapid Thermal Processor (RTP). The ambient typically is Nitrogen, Oxygen, Hydrogen. Sometimes, it may add chlorine for specific purpose of metallic gettering process.
AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic AMK Site Training
Page: 9

Process Oxidation Diffusion Impurity Dopant Deposition CVD Poly, LTO, Nitride, TEOS, O-N-O Reflow / Glass Flow Objectives Grow a layer of oxide film to protect underneath layers Drive in the dopants into silicon to form conductive diffused zone (N or P) Convert liquid phase chemicals and deposit doped glass (P2O5) on silicon surface Deposit a dielectric film (SiO2,Si3N4), PolySi film through low pressure Doped oxide (PSG) is subjected to mediumhigh temperature process causes the glass to soften and flow to have a better conformal step coverage A high temperature operation to allow silicon or polysilicon reacts with a metal to form a silicide compound (TiSi2). To reduce contact resistance@metal-Si interface. To repair lattice damage after the implant damage Op. Temp C 750 ~ 1200 800 ~ 1250 750 ~ 1100 400 ~ 1000 850 ~ 1100
(Cont.)
Tools
Furnace / RTP Furnace Furnace Furnace Furnace
Silicide
400 ~ 850
RTP
Post Implant Anneal
600 ~ 1200
Furnace / RTP
AMK Site Training
AMK Site Training

Page: 10

Process Gettering Objectives A controlled modification of the silicon crystal to draw impurities to the bulk, or to the back surface of the wafer, so that immobilize impurities at locations away from the region of the active zone. Densify the dielectric oxide without changing its amorphous phase structures but increases the density of the film Op. Temp C 600 ~ 1200
(Cont.)
Tools Furnace
Densification
900 ~ 1100
Furnace
AMK Site Training
AMK Site Training

Page: 11
Topic 2: Thermal Oxidation
AMK Site Training
AMK Site Training

Page: 12
Thermal Oxidation
Definition: Thermal Oxidation is defined as the formation of oxide on Silicon (SiO2) on a silicon surface. 2 Main Type of Oxidation Process : Dry Oxidation Si (Solid) + O2(vapor) SiO2 (Solid) Slow growth rate & controllable Very dense & clean Use for gate oxide in MOS device Wet Oxidation Si (Solid) + 2H2O(vapor) SiO2 (Solid) + 2H2 faster growth rate less dense than dry oxide Use for field oxide or mask oxide
Page: 13
Oxide Thickness Range (20 to 10,000)

MOS gate oxide 20-500 EPROM tunnel oxide 60-100 Sacrificial (screen) Oxide 100-400 Pad oxide 100-500 Masking oxide 2,000-5,000 Field oxide 3,000-10,000
AMK Site Training
AMK Site Training

Page: 14
Growth Mechanism
Oxygen (or steam) must come into direct contact with silicon As oxide grows, the silicon is consumed (45%) of the final oxide thickness (Toxide). After initial oxide layer is formed, oxygen must diffuse through the layer to reach the silicon (reaction is slowed)
Si consumed = 0 .45 x T oxide

Silicon consumed
AMK Site Training
AMK Site Training

Page: 15
Growth Mechanism
Native Oxide: First 0 - 20 Nearly instantaneous growth from ambient Inhibit oxidation of silicon Linear Growth: 20 - 1000 ->Initial growth stage Growth rate is relatively fast Thickness, x = C1 x time(t) C1 is a constant that is dependent on temperature (Angstroms/min).
x ()
(Cont.)
Linear
xt
Time
AMK Site Training
AMK Site Training

Page: 16
Growth Mechanism
Parabolic Growth: >1000 Growth rate becomes slow Thickness, x = C2 X time(t)
x ()
Linear
(Cont.)
Parabolic
x t
C2 is a constant that is dependent on temperature
Time
Example: An wet oxidation process at 1000OC, has C2 =180 Angstroms/minute where C2 obtain from oxide data curve (Pg 27) Growth for 90 minutes: Thickness = (180 /min) X SQRT (90min) = 1707
AMK Site Training
AMK Site Training

Page: 17
Function of Oxide
Device scratch protection Device isolation e.g. Field oxide in MOS Dielectric material (Electrical insulator) in the gate oxide (MOS) or memory cell structures Impurity-mask barrier during doping or implant Dielectric layer between metal conductor layers i.e.Capacitor
AMK Site Training
AMK Site Training

Page: 18
Application of Oxide
Field Oxide in MOS
Substrate
Field oxide and Shallow Trench Isolation (STI) barrier oxide services as an isolation barrier between individual transistors to isolate them from each other.
Shallow Trench Isolation (STI) in DRAM
Substrate
AMK Site Training
AMK Site Training

Page: 19
Gate Gate Oxide Source Drain
(Cont.)
Substrate
MOS Device
Gate Oxide Gate Oxide
Gate oxide serves as a dielectric between the gate and source-drain parts of MOS transistor
N-well
P-well
Substrate
Twin well MOS Device
AMK Site Training
AMK Site Training

Page: 20
Dopant
Dopant Barrier Oxide
Emitter
(Cont.)
Base
Oxide serves as masking material for depositing or implanting dopants into silicon. Selective diffusion by dopants only happens on opening or unprotected areas. Dopants have a slow rate of movement through oxide when compared to silicon.
Substrate
Bipolar Junction Transistor
Screen oxide
Dopant barrier spacer oxide
Implantation
Source
Drain Spacer oxide protects narrow channel from high energy implant
Substrate
AMK Site Training
AMK Site Training

Page: 21
Nitride Pad Oxide
(Cont.)
Substrate
Pad oxide Bonding Pad Metal Passivation Nitride Metal Barrier Oxide
Pad oxide provides stress reduction (cushion) for nitride and silicon. In short, stress relief oxide.
Barrier oxide protects active devices and silicon from follow-on processing
Barrier oxide
AMK Site Training
AMK Site Training

Page: 22
Ion implantation Thin Screen oxide
(Cont.)
Substrate
(Without screen oxide) High damage to upper Si surface plus more channeling (Ion B) (With screen oxide) Low damage to upper Si surface plus less channeling (Ion A)
AMK Site Training Front-End Technology & Manufacturing
A thin thermally grown implant screen oxide serves to reduce damage to the silicon surface and obtain better control over the depth that the dopant is implanted into silicon by reducing channeling effect.
Channeling Si atom Ion A Ion B Lattice imperfection
AMK Site Training

Page: 23
Factors Affect Oxidation Growth Rate

Silicon Crystal Lattice Orientation i.e. <111> or <100> Dopant Effects Chlorine Dependence Pressure Effects
AMK Site Training
AMK Site Training

Page: 24
Oxidation Growth Rates: Crystal Orientation Effects

Oxygen Silicon surface <100> Silicon Oxygen Silicon surface <111> Silicon
Silicon with crystal orientation of <111> will tend to oxidize faster than <100> The <111> silicon permits a greater number of atoms to be exposed to the diffusing oxygen molecules. Thus, an increase in oxidation rate is seen. Density surface atoms of Silicon:
<111> - 7.83 X 1014 cm-2 <100> - 6.78 X 1014 cm-2
AMK Site Training
AMK Site Training

Page: 25
Oxide Growth Rate Data Curve
<111> Si 0.021um <100> Si 0.015um
Oxide growth rate in silicon for DRY oxidation

Page: 26
Oxide Growth Rate Data Curve

(Cont.)
<111> Si 0.03um 0.021um <100> Si 0.018um 0.15um
Oxide growth rate in silicon for wet oxidation

Page: 27
Oxidation Growth Rates: Dopants Effect

Common dopants like Boron & phosphorous enhanced oxidation rate in silicon as shown below:
SiO2 in Phosphorous Doped Silicon

AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic
SiO2 in Boron Doped Silicon

AMK Site Training
Page: 28
Oxidation Growth Rates: Chlorine Effects

Presence of chlorine in oxidation ambient increase oxidation growth on silicon. Note: C2H2Cl2 [DCE] + 2O2 2HCl + 2CO2
Oxidation rate of <100> silicon in chlorine ambient

Page: 29
Oxidation Growth Rates: Pressure Effects

Increase in pressure increase oxide growth (1atm=760 Torr)
Thickness increase with pressure
Oxidation rate of <111> & <100> silicon in wet ambient

Page: 30
Furnace Equipment Systems

Furnace system (horizontal or vertical) consists of a number of subsystems Tube Quartz or silicon carbide Wafer boats quartz, silicon carbide Heating elements capable to heat up to 1300 C Thermocouples Temperature controller for the dopants
AMK Site Training
AMK Site Training

Page: 31
Furnace Equipment Horizontal System

Heating Element Coil Heater
Zone 2 Center
Zone 3 Source
Zone 1 Handle
Quartz Tube
Si Wafers & Dopant source
AMK Site Training

Page: 32
Furnace Equipment Horizontal System

Horizontal Furnace Loading Station
(Cont.) Tube Computer
Computer Console Station(MUX)

Page: 33
Furnace Equipment System

Horizontal Furnace
Inlet process gases Cantilever or paddle
Quartz Tube
Wafers Inner Atmoscan tube Nitrogen gas inlet
Atmoscan Furnace
Thermocouple
AMK Site Training

Page: 34
Pyrogenic Oxidation Source Furnace
AMK Site Training
AMK Site Training

Page: 35
Source Cabinet Horizontal Furnace

Gas Jungle & Bubbler Controller
er ilt F
as G
MFC
POCL3 25oC
LE AV V
BUBBLER
AMK Site Training
AMK Site Training

Page: 36
Furnace Equipment (Vertical) System

Process gases Thermocouples Quartz wares
Heating elements
Vertical furnace system

To Exhaust AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic AMK Site Training
Page: 37
Pyrogenic Oxidation System

H2 SF Heater Furnace Inlet gases, H2, O2, N2, Cl2 Heating Element
Safety Ratio H2 : O2 <1.88
N2 O2 Carrier gas N2 DCE (Chlorinated agent, liquid) Temperature control bath(20oC)

Pyrogenic flame H2 + O2 To vent Si + O2 SiO2
Chemical reaction for Oxidation System Dry oxidation Dry + Gettering Wet oxidation Wet + Gettering DCE oxidation
Si + 2O2 + 4HCl SiO2 + 2H2O + 2Cl2 Si + 2H2O SiO2 + 2H2 Si + 2H2O +2HCl SiO2 + 3H2 + Cl2 C2H2Cl2 [DCE] + 2O2 2HCl + 2CO2
AMK Site Training

Page: 38
Topic 3: Thermal Diffusion
AMK Site Training
AMK Site Training

Page: 39
Diffusion Concepts
Migration of a substance from a higher concentration to a lower concentration. Examples: perfume in air (gas state), ink in water (liquid state) Diffusion is accelerated by putting energy (heat) into the system.
Ink in water (Liquid Diffusion)

Perfume in Air (Gas Diffusion)

AMK Site Training
Page: 40
Diffusion Concepts
(Cont.)
A high temperature process whereby selected chemical dopants (N or P Type) which entered the silicon to change its electrical characteristics at desired location.
xj = 0
xj
N Dope Region
Silicon xj = Final Depth AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic Diffusion Model
AMK Site Training

Page: 41
Predeposition Thermal Cycle

Predeposition Time-temperature dependent chart Boat in of wafers Temperature ramp up from standby@700oC to process temperature@900oC Process time Rampdown of process temperature to standby temperature Boat out of wafers
lower temperature
Ramp rate
900oC Process time
10oC/min
30min with O2
5oC/min
700oC Boat in AMK Site Training Front-End Technology & Manufacturing 20 min Diffusion Process - Basic 40 min Boat out
700oC
AMK Site Training

Page: 42
Drive in Thermal Cycle

Drive-in Time-temperature dependent chart@ Boat in of wafers Temperature ramp up from standby@700oC to process temperature@1000oC (High temperature) Process time Ramp down of process temperature to standby temperature Boat out of wafers
Higher temperature 1000oC Process time
10oC/min
Dry O2 30min +Wet 40min
5oC/min
700oC Boat in AMK Site Training Front-End Technology & Manufacturing 30 min Diffusion Process - Basic 60 min Boat out
700oC
AMK Site Training

Page: 43
Two Step Diffusion

Two Major Steps in Diffusion: Pre-Deposition : Dopants are deposited on the surface of the wafer
Drive-In : redistribution of dopants atoms introduced from the predeposition step to the desired depth in wafer.
AMK Site Training
AMK Site Training

Page: 44
Laws of Diffusion
Ficks 1st Law When an impurity is dissolved in silicon and the impurity has a non-uniform concentration, the first law of diffusion describes that the impurity will tend to spread out until the concentration is reached its equilibrium state.
N J = D x
Where J is the flux density; D is diffusion coefficient; N is the impurity concentration.
AMK Site Training
AMK Site Training

Page: 45
Laws of Diffusion Ficks 1st Law
(Cont.)
It States that particle flow is proportional to the concentration gradient
X1
X2
X1
X2
N J = D x
Negative Sign Decreasing concentration gradient
Impurity concentration gradient
Diffusion Coefficient of impurity (N or P Type)
AMK Site Training
AMK Site Training

Page: 46
Laws of Diffusion
Diffusion Coefficient
(Cont.)
Solid-state diffusion occurs as a result of the random motion of impurities in silicon and these are always thermally activated. The diffusion coefficient is therefore a very strong function of temperature, T and a relation of the form: Where
Q D = D0 exp k T B
D0 Q kB T
is frequency factor; is the activation energy; is the Boltzmann constant;8.62X10-5eV/K is in degrees Kelvin.
AMK Site Training

Page: 47
Solid Solubilities of Impurity Elements in Silicon

Solid Solubility of impurities in Silicon data Cure
Solid solubility defines the maximum concentration of a dopant that can be absorb in a substrate at any specific temperature. Example Common dopant:
Phosphorous = 1.3X1021 atoms/cc@1200oC
AMK Site Training
AMK Site Training

Page: 48
Topic 4: POCL3 Deposition
AMK Site Training
AMK Site Training

Page: 49
N Type Doping
POCL3(Phosphorous oxychloride) is N type impurity N Type Doping is to introduce impurity(electrons) on the silicon to form collector and emitter in bipolar NPN transistor, and source/drain in NMOS. Electrons are the primary current carrier.
Collector (N type) Drain (N type)
Base
Gate
Emitter (N type) NPN Transistor AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic
Source (N type) NMOS AMK Site Training

Page: 50
N Type Dopants
Dopants Phosphorus, P Dopant type n Source Source Phase Gas Planar Gas Solid Liquid System Furnace Furnace / Implanter Furnace Implanter Furnace / Implanter Implanter Phosphorus Oxychloride, POC3 Liquid Phosphine, PH3 Solid Wafer SiP2O7 Arsenic, As Antimony, Sb n n Arsine, AsH3 Di-Antimony Tri-oxide, Sb2O3 Tri-Methylantimony, Sb(CH3)3
AMK Site Training
AMK Site Training

Page: 51
POCL3 Doping
Heat + Dopant
Silicon Wafer
Masking oxide
Phosphorus doped glass Masking oxide
Predeposition
Phosphorus doped zone in Silicon Phosphorus dope SiO2

SiO2
Masking oxide
Diffusion
Phosphorus diffused zone in Silicon AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic AMK Site Training
Page: 52
Liquid Source Doping System

O2 Inlet doping gases Furnace (Atm or LP)
Gaseous phase POCl3 Heating Element
To vent N2 Liquid source POCl3 Temperature control bath(25oC)

Chemical reaction for POCL3 Reaction Deposition
4POCl3 + 3O2 2P2O5 +6Cl2 2P2O5 + 5Si 5SiO2 + 4P
Collaborated with Pyrogenic system 2H2O + 2Cl2 4HCl + O2 Recomposition
Si + 2H2O + 2HCl SiO2 + 3H2 + Cl2 Oxidation + Gettering

Diffusion Process - Basic AMK Site Training
Page: 53
Liquid Source Doping System Atmospheric Furnace
Cantilever /Twin Rod Cantilever Low Rs range 1 to 4 /sq
Paddle Paddle High Rs range 5 to 20 /sq
AMK Site Training
AMK Site Training

Page: 54
Liquid Source Doping System LYDOP

LYDOP denotes Low Pressure Phosphorus Oxychloride Doping Reduce low pressure give better doping uniformity with reduced maintenance compared to atmospheric doping process. High Throughput 200 wafers per run
LYDOP System
Page: 55
LYDOP Concept
Gas molecules Air molecules
(Cont.)
Gas molecules
End
End
Longer mean free path of gas species
Start
Atmospheric Pressure
Start
Low Pressure
Note : Mean Free Path

Distance Particle travel before collision

AMK Site Training

Page: 56
Solid Source System

Wafer Back side P2O5 Front Patterned Solid sources, PH1000 wafer side
Quartz Rack
AMK Site Training

Page: 57
Solid Source Doping System

N2 O2 Inlet doping gases Heater Chemical reaction for PH1000, SiP2O7 SiP2O7 + (Heat & N2) P2O5 + SiO2 H2 2P2O5 + 5Si 5SiO2 + 4P Activation Deposition Furnace
N2
AMK Site Training
AMK Site Training

Page: 58
Topic 5: Boron Deposition
AMK Site Training
AMK Site Training

Page: 59
P-Type Doping
Boron Nitride(BN) is P type impurity P Type Doping is to introduce impurity(holes) on the on the silicon to form isolation and base structure in bipolar NPN transistor, and source/drain in PMOS. Holes are the primary current carrier.
Collector Source (P type)
Gate Base (P type) Emitter NPN Transistor Drain (P type) PMOS
AMK Site Training
AMK Site Training

Page: 60
P Type Dopants
Dopants Boron, B Dopant type p Source Boron Nitride, BN Boron Tribromide, BBr3 Diborane, B2H6 Boron Tri-fluride, BF3 Indium, In Aluminum, Al p p Indium Tri-chloride, InC3 Aluminum Oxide, A2O3 Source Phase Planar Liquid Gas Gas Solid Solid System Furnace Furnace Implanter Implanter Implanter Implanter
AMK Site Training
AMK Site Training

Page: 61
Planar Doping
Heat + Dopant Silicon Wafer
SiO2
Masking oxide
Boron Glass Masking oxide Predeposition

Boron doped zone in Silicon
Boron dope SiO2

SiO2
Masking oxide
Diffusion or Drive in
Boron diffused zone in Silicon AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic AMK Site Training
Page: 62
Solid Source Boron Process

There are 2 type of Boron deposition process:
Dry process with O2 Wet process with H2O known as Hydrogen injection process
AMK Site Training
AMK Site Training

Page: 63
Solid Source System

Wafer Back side B2O3 Front Patterned Solid sources, BN975 wafer side
Quartz Rack
AMK Site Training

Page: 64
Solid Source Doping System

N2 O2 Inlet doping gases Heater Chemical reaction Boron Nitride Dry Process 4BN + 3O2 2B2O3 + 2N2 H2 3Si + 2B2O3 3SiO2 + 4B Wet Process B2O3 + H2O 2HBO2 (Metaboric acid) 2Si + 2HBO2 2SiO2 + 2B + H2
Furnace
N2
Activation Deposition
H2 injection Deposition
AMK Site Training

Page: 65
Topic 6: Rapid Thermal Processing (RTP)
AMK Site Training
AMK Site Training

Page: 66
Rapid Thermal Processing Overview

The RTP is a method of heating a single wafer to a temperature range of 400 to 1300 in a very short time.(eg. F ast C ramprate@50oC/s) The main advantages over a conventional furnace: Reduced thermal budget Minimized dopant movement in the silicon Cleaner ambient because of the smaller chamber volume Reduced contamination due to cold wall heating (wafer is heated chamber wall, ambient not heated) Useful for ion implantation damage annealing (RTA).
AMK Site Training
AMK Site Training

Page: 67
Rapid Thermal Processing Overview

(Cont.)
The Disadvantages of RTP are : Single-wafer processing Rapid heating of wafer can result is warpage, slip defects & thermal stress Relatively poor process uniformity
AMK Site Training
AMK Site Training

Page: 68
RTP Thermal Cycle

RTP Time-temperature dependent chart Wafer at standby room temperature@25oC Load wafer to heating chamber with idle temperature@100oC Fast ramp up rate from 25oC/sec to 75oC/sec Process time < 60sec Fast ramp down rate from 25oC/sec to 75oC/sec Unload wafer to cooling station
30 sec
Fast Ramp rate
1000oC
50oC/sec
50oC/sec
Idle temp=100oC 18 sec AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic 18 sec
100oC
AMK Site Training

Page: 69
RTP System
Slip-Free Ring
Tungsten Halogen Lamps (Crosswise)
Wafer
The hardware used for RTP is typically a single wafer chamber equipped with a radiant heat source. The heat source is an IR radiator at wavelengths that are efficiently absorbed by the silicon wafer. This allows very rapid and uniform heating. Temperature is controlled using an optical pyrometer in a closed loop control system.
Thermocouple Pyrometers Ceramic Shield Tungsten Halogen Lamps (Lengthwise)
AMK Site Training
AMK Site Training

Page: 70
Chamber of RTP System
Wafer chuck
AMK Site Training
AMK Site Training

Page: 71
RTP Application
Temperature, C
1200
Ultrashallow Junction (USJ) formation Implant anneal BPSG / PSG densification
1000
800
TiSi anneal Barrier metal anneal TiSi formation
600
CoSi formation
CoSi anneal High-k anneal
NiSi formation / anneal
400
Cu anneal
200
Process Time
Page: 72
RTP Application
Titanium Silicide (TiSi2) Formation :
(Cont.)
Silicides are used to reduce contact resistance at metal-silicon interface. TiSi2 becoming an issue for ultrashallow junctions. Current technology is Cobalt Silicide forms at lower temperatures with comparable resistance. Future technologies (sub-100nm) with even shallower junctions are considering Nickel Silicide.
AMK Site Training
AMK Site Training

Page: 73
Topic 7: Common Diffusion Defects
AMK Site Training
AMK Site Training

Page: 74
Type of Defects
Oxidation Defects OISF ESF Oxide Induced Stacking Faults Epitaxial Stacking faults
Oxide Induced charges POCL3 Defects POCL3 stain Boron Defects Boron skin
AMK Site Training
AMK Site Training

Page: 75
Oxide Defects in Diffusion
AMK Site Training
AMK Site Training

Page: 76
Oxide Induced Stacking Faults

Stacking faults are frequently generated in the surface region of silicon wafer during thermal oxidation process at a typical temperature range between 900 and 1200 These fa ults are C. commonly called oxidation-induced stacking faults (OSF or OISF). Degrade the performance and affect the reliability of semiconductor devices.
AMK Site Training
AMK Site Training

Page: 77

OSFs are predominantly nucleated at certain mechanical damages on the wafer surface; they include contamination with Na or metallic impurities, and surface pitted by HF acid. Moreover, oxygen precipitates can also be nucleated sites for OSF. OSFs are caused by Fe metallic contaminations on ptype dopant diffusion zone
AMK Site Training

Page: 78

Stacking faults are also observed in silicon epitaxial films grown on silicon substrates. They differ from OSFs both in structure and in the mechanisms of formation. These faults nucleate dominantly at the interface ions on the surface or in the substrate region, and grow into the epitaxial film.
Epitaxial Layer
Stacking fault
Epitaxy Stacking Fault grown on <111> surface

Page: 79
Oxidation Induced Defects

Oxide Charge Interface Trapped Qit Fixed Qf Mobile Qm Oxide Trapped Qot
Oxide layer Origin at the gate /SiO2 interface and enter oxide layer
Origin in silicon
Silicon-silicon oxide interface
Cause
Silicon orientation <111> or <100> Oxidation temperature Oxidising ambient (H2O or O2) Furnace Rampdown rate Wafer handling Photoresist, developer Furnace cleanliness Impurities & broken bonds(Si-O)
30 to 50 of the silicon interface
QTotal = Qinterface
AMK Site Training
trap
+ Q fixed + Qmobile + Qoxide trap

Diffusion Process - Basic AMK Site Training
Page: 80
MOS Structure
Metal
Mobile charge Qm
Na+
Oxide trapped charge(Qot) Fixed charge (Qf)
Oxide
Interface trapped charge (Qit)
Semiconductor
AMK Site Training
AMK Site Training

Page: 81
POCL3 Defects in Diffusion
AMK Site Training
AMK Site Training

Page: 82
Name of Defect : POCL3 STAIN

Good wafer Bad wafer
POCL3 Defect
Cause Reaction of the POCL3 and moisture will result in phosphoric acid and small amount of Hydrochloric acid which attack the silicon. If the tube and boat is highly doped Autodoping (atoms that outgas from tube or boat and then redope into process ambient and wafer)
Page: 83
Boron Defects in Diffusion
AMK Site Training
AMK Site Training

Page: 84
Boron Defect
Name of Defect: Boron Stacking Fault
Cause When B2O3 reacts with silicon, it forms a glassy structure with silicon. During diffusion, the rate of expansion on the doped Si surface is different with that of pure Si structure, hence causing dislocations on the wafer. The dislocation propagates with temperature and forms stacking faults.
Page: 85
Boron Defect (Cont.)

Name of Defect : Boron Skin
Cause: Water vapour on the B2O3 layer of the wafer surface. The water vapour will react with hot boron glass (B2O3) to form metaboric acid. H2O + B2O3 2 HBO2 The metaboric acid will etch into the wafer on temperature above 400 oC.
Page: 86
Topic 8: Metrology Tool in Diffusion
AMK Site Training
AMK Site Training

Page: 87
Metrology Tools
Common Diffusion Process Parameters Films thickness Ellipsometer, Optiprobe, UV1280 Doped sheet resistivity Four-point probe, Rs machine Doping concentration profile Spreading Resistance Probe
AMK Site Training
AMK Site Training

Page: 88
Metrology Tools
Quality parameters for contamination control
(Cont.)
Defectivity Inspection Scopes Wafer Defects control Surface Photo-Voltage (SPV) Measurement Iron contamination control Capacitance Voltage (C-V) techniques Mobile ion contamination control TXRF(Total X Ray Fluorescence) Determine concentration of heavier element eg. Nickel on SPV wafer substrate
AMK Site Training
AMK Site Training

Page: 89
Film Thickness Measurement Tool

Opti probe and UV machine are capable to measure oxide, silicon nitride, Poly on oxide, oxide on Poly and oxide-nitride-oxide (ONO)
Optiprobe UV machine
Page: 90
Film Thickness Principle

A non-destructive, non-contact to measure thin and transparent film (e.g. silicon oxide) Wafer is optically scanned by a laser
Re fractive Index , sin = sin SiO 2 ( ideal ) = 1.46 air = 1
Ellipsometer Principle
Oxide Thickness
AMK Site Training
Page: 91
Surface Photo Voltage(SPV) Measurement Tool

Function: To detect heavy metals (e.g. Fe, Copper, Cobalt, Nickel) found in wafers. SPV machine and the concentration of Fe dissolved in the silicon
SPV wafer
SPV Machine
SPV wafer Map

AMK Site Training
Page: 92
SPV Measurement Principle

SPV is the change of the electrostatic potential at the wafer surface caused by illumination. Diffusion Length, (L) average distance an excess minority carrier travels before recombination. It is a measure of imperfection in silicon (e.g. metal contamination, oxygen induce defects)
Photon flux Chopper Lock- in amp dV
e- e- e-
eBand to Band Recombination
Ec
Very Pure Silicon: Band to Band Recombination - Long Lifetime
EF Ev P type substrate e- e- eeEc

Ox Ppt Fe Silicon with Impurity/Defects: Recombination through Defect States - Kills Lifetime
SPV electrode
Silicon wafer Chuck
Cr
Defect State Recombination
P type substrate AMK Site Training Front-End Technology & Manufacturing Diffusion Process - Basic
EF Ev
AMK Site Training

Page: 93
SPV Measurement Principle

Calculation
Diffusion Length Measurement
(cont.)
L
1
Fe-B pairing occurs at room temperature (Iron mobile at room temp) Measure L1 The Fe-B Pair is a weak recombination center - little effect on lifetime Fe-B Pairs can be dissociated by exposure to bright light
Optical Activation (FeB Pair Dissociation)
Diffusion Length Measurement
L
2
Fe is an efficient recombination center significantly reduces lifetime Measure L2 Determine Iron calculation, Fe
C alculation
Universal constant
[Fe ] cm-3 =1.051016 L2-2 - L1-2
AMK Site Training
AMK Site Training

Page: 94
Capacitance Voltage(C-V) Measurement

Conventional method of C-V Metal-Oxide-Semiconductor structure Bias voltage from -5V to 5V and record capacitance
CV Test Setup
Page: 95

(cont.)
CV Plot for n-type silicon

C max Q=CV Capacitance Qm = C.V
Ideal curve V Real curve
where Q = Qm mobile charge V=Voltage shift
C min -5
AMK Site Training
0 Bias Voltage
+5
AMK Site Training
Page: 96

(Cont.)
Non-contact C-V measurement technique COCOS Metrology (Corona-Oxide-Characterization-Of-Semiconductor) Corona pulsing gun controls charge deposition (positive or negative) Fast and precise vibrating probe provides non-contact voltage transient measurement
Corona charge
Measured with noncontact probe
Q=CV C = Q/V
AMK Site Training

Page: 97
Sheet Resistance
The four-point probe technique is one of the most common methods for measuring semiconductor resistivity. A known value of current (I) is passed between the two outer probes, and the potential difference (V) developed across the inner probes is measured.
Ohm' s Law V I Sheet Re sis tan ce R= V I where C.F . is Correction Factor = 4.53 Rs = C.F .x R = C.F . x
Automatic 4 point probe system AMK Site Training Front-End Technology & Manufacturing
4 point probe Diffusion Process - Basic AMK Site Training

Page: 98
Spreading Resistance Probe

The spreading resistance probe (SRP) is used to measure both dopant concentration depth profiles and resistivity. It is capable of profiling very shallow p-n junction depths. The SRP probe has two carefully aligned probes that are moved in steps along a beveled wafer surface, with the resistance between the probes measured at each step. As the probes pass through the junction, the probes sense the change in conductivity type (n or p). The sample must be carefully prepared with a bevel angle, usually 0.5~ 5 which makes the SRP a destructive test. ,
AMK Site Training
AMK Site Training

Page: 99
Spreading Resistance Probe

(Cont.)
Beveled surface
V ~ 5 mV = fixed voltage
I I
The SRP measurement method is characterized as: specially prepared probes and the apparatus to raise, lower and step the probes; low applied voltages during the measurement;
P-N Junction
Silicon sample with doped profile
Z (depth) = l Sin
P substrate Concentration N P Substrate
xj
xj
Page: 100
SRP Profile
Arsenic doped
Boron doped Si SiO2 interface Diffusion Junction
Epitaxy n-doped concentration
AMK Site Training
AMK Site Training

Page: 101
AMK Site Training
AMK Site Training

Page: 102
~~~~THANKYOU~~~~
AMK Site Training
AMK Site Training

Page: 103
References
Silicon Wafer Manufacturing (Gilles Thomas, ST) AMK5 Cross-Functional Training Material, Diffusion (AMK5 Diffusion) Silicon Processing for the VLSI Era Volume 1 (S.Wolf & R.N. Tauber) Basic Process Technology (STMicroelectronics) Advance Semiconductor Handbook (Integrated circuit engineering cooperation) Technical article on Role of chlorine in silicon oxidation (J. Monkowski)
AMK Site Training
AMK Site Training

Page: 104

Thermal Oxidation Process Basics

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Thermal Oxidation Process Basics

Uploaded by

Copyright:

Available Formats

Diffusion Process - Basic

AMK Site Training

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

Course Agenda Outline

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

Topic 1: Basic Thermal Processes

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

Thermal Process Overview

Thermal Process Overview

Furnace / RTP Furnace Furnace Furnace Furnace

Post Implant Anneal

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

Thermal Process Overview

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

Topic 2: Thermal Oxidation

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

Oxide Thickness Range (20 to 10,000)

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

Si consumed = 0 .45 x T oxide

AMK Site Training

Front-End Technology & Manufacturing

Diffusion Process - Basic

AMK Site Training

AMK Site Training

Front-End Technology & Manufacturing