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SDH Multiplexing
It is very important to understand the SDH multiplexing hierarchy to truly understand and appreciate SDH. Multiplexing follows a rigid hierarchy in SDH. From an extremely high-level perspective, it is safe to say that low-level PDH signals are mapped to an SDH entity known as a container (C). The C is mapped along with POH bytes to form another entity known as a lower-order virtual container (VC). The lower-order VCs are aligned with tributary unit (TU) pointers to form entities known as tributary units (TUs). The TUs are multiplexed to form tributary unit groups (TUGs). The TUGs are further multiplexed to form higher-order VCs. These higher-order VCs are aligned with fixed byte-stuffing and administration units (AU) to form administration units (AUs). The AUs are further multiplexed to form administrative unit groups (AUGs). The AUGs are finally multiplexed along with RSOH and MSOH bytes to form the STM-N signal. There are variations to the flow just described as you will notice in the subsequent discussion. Before you read on, you need to understand a few simple terms. The multiplexing principles of SDH use the following terms:

Mapping A process used when tributaries are adapted into VCs by adding justification bits and POH information. Aligning This process takes place when a pointer is included in a TU or an AU, to allow the first byte of the VC to be located. Multiplexing This process is used when multiple lower-order path layer signals are adapted into a higher-order path signal, or when the higher-order path signals are adapted into a multiplex section. Stuffing As the tributary signals are multiplexed and aligned, some spare capacity has been designed into the SDH frame to provide enough space for all the various tributary rates. Therefore, at certain points in the multiplexing hierarchy, this space capacity is filled with fixed stuffing bits that carry no information, but are required to fill up the particular frame.

PDH traffic signals to be mapped into SDH are by definition continuous. Each PDH signal is mapped to an SDH container (C). The Cs are mapped to VCs. The purpose of this function is to create a uniform VC payload by using bit stuffing to bring all inputs to a common bit rate ready for synchronous multiplexing. There are two kinds of Cs: lower-order tributaries (Cs) and higher-order tributaries (Cs). Lower-order Cs (CNx, where N = 1, 2, and x = 1, 2) typically accommodate PDH signals, such as DS1, E1, and other PDH signals up to the DS2/J2 level. Higher-order Cs (C-N, where N = 3, 4) typically accommodate PDH signals, such as E3, DS3, and other PDH signals up to the E4 level. Similarly, there are two kinds of VCs: lower-order VCs and higher-order VCs. Lower-order VCs (VC-Nx, where N = 1, 2 and x = 1, 2) typically accommodate PDH signals, such as DS1, E1, and other PDH signals up to the DS2/J2 level. Higher-order VCs (VC-N, where N = 3, 4) typically accommodate PDH signals, such as E3, DS3, and other PDH signals up to the E4 level. Various VCs ranging from VC-11 to VC-4 are covered by the SDH hierarchy. Currently, the ITU-T has defined six SDH Cs/VCs. The six VCs defined are VC-11, VC-12, VC-2, VC-3 (E3/J3/ISDN H31), VC-3 (DS3/ISDN H32), and VC-4. Table 6-4 lists the various SDH VC levels.
Table 6-4. VC Levels

Low-Order VC Level VC-11

VC Bit Rate (Mbps) 1.728

PDH Level DS1/J1/ISDN H11

NADH (Mbps) 1.544

EDH (Mbps)

JDH (Mbps) 1.544

VC-12 VC-2 High-Order VC Level VC-3 VC-3 VC-4

2.304 6.912

E1/ISDN H12 DS2/J2 PD Level

6.312 NADH (Mbps) 44.736

2.048 EDH (Mbps) 34.368 139.264

6.312 JDH (Mbps) 32.064

48.960 48.960 150.336

E3/J3/ISDN H31 DS3/ISDN H32 E4/ISDN H4

Through the use of pointers and offset values, VCs can be carried in the SDH payload as independent data packages. VCs are used to transport lower-speed tributary signals. VCs can start at any point within the STM-1 frame. The start location of the J1 POH byte is indicated by the AU pointer byte values. VCs can also be concatenated to provide more capacity. Table 6-5 illustrates the various SDH paths and associated overhead. Higher levels of the synchronous hierarchy are formed by byte interleaving the payloads from a number N of STM1 signals and then adding a transport overhead of size N times that of an STM1 and filling it with new management data and pointer values as appropriate. Before transmission, the STMN signal has scrambling applied overall to randomize the bit sequence for improved transmission performance. A few bytes of overhead are left unscrambled to simplify subsequent demultiplexing.
Table 6-5. SDH Multiplexing Overhead

Path C-N to VC-N VC-N to TU-N VC-N to AU-N

SDH Overhead C-N + VC-N POH = VC-N (N = 11, 12, 2, 3, or 4) VC-N + TU-N pointers = TU-N (N = 11, 12, 2, or 3) VC-N + AU-N pointers = AU-N (N = 3 or 4)

AUG-N to STM-N AUG-N + RSOH + MSOH = STM-N

SDH Multiplexing of E1 Signals Low-level E1 (2.048-Mbps) signals are mapped to the C-12 container. As illustrated in Figure 6-4, the C-12 container gets mapped with VC-12 POH bytes into a lower-order VC-12 virtual container. The VC-12 along with TU-12 pointers gets aligned into a TU-12 tributary unit. The TU-12 gets multiplexed (x3) to a TUG-2, which means that three TU-12s are multiplexed into a TUG-2. The TUG-2 gets multiplexed (x7) into a higherorder VC-3. This VC-3 gets aligned with AU-3 pointers to form an AU-3. The AU-3 can get directly multiplexed (x1) to form an STM-0 signal or get multiplexed (x3) to form an AUG-1. The AUG-1 gets multiplexed (x1) along with MSOH and RSOH bytes to form an STM-1.
Figure 6-4. SDH Multiplexing

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SDH Multiplexing of DS1 Signals Low-level DS1 (1.544-Mbps) signals are mapped to the C-11 container. As illustrated in Figure 6-4, the C-11 container gets mapped with VC-11 POH bytes into a lower-order VC-11 virtual container. The VC-11 along with TU-11 pointers gets aligned with a TU-11 tributary unit. The TU-11 gets multiplexed (x4) to a TUG-2, which means that four TU-11s are multiplexed into a TUG-2. In the case of the VC-11, however, there is an alternate path. The VC-11 could also get aligned along with TU-12 pointers to form a TU-12 tributary unit, in which case the TU-12 would get multiplexed (x3) to a TUG-2. The TUG-2 gets multiplexed (x7) into a higherorder VC-3. This VC-3 gets aligned with AU-3 pointers to form an AU-3. The AU-3 can get directly multiplexed (x1) to form an STM-0 signal or get multiplexed (x3) to form an AUG-1. The AUG-1 gets multiplexed (x1) along with MSOH and RSOH bytes to form an STM-1. SDH Multiplexing of DS2 Signals Low-level DS2 (6.312-Mbps) signals are mapped to the C-2 container. As illustrated in Figure 6-4, the C-2 container gets mapped with VC-2 POH bytes into a lower-order VC-2 virtual container. The VC-2 along with TU-2 pointers gets aligned with a TU-2 tributary unit. The TU-2 gets multiplexed (x1) to a TUG-2. The TUG-2 gets multiplexed (x7) into a higher-order VC-3. This VC-3 gets aligned with AU-3 pointers to form an AU-3. The AU-3 could get directly multiplexed (x1) to form an STM-0 signal or get multiplexed (x3) to form an AUG-1. The AUG-1 gets multiplexed (x1) along with MSOH and RSOH bytes to form an STM-1. SDH Multiplexing of E3 Signals High-level E3 (34.368-Mbps) signals are mapped to the C-3 container. However, the C-3 mapping for E3 takes place differently as compared to the C-3 mapping for DS3. This is illustrated in Figure 6-4. The E3 gets mapped to a C-3 that in turn gets mapped along with VC-3 POH bytes into a VC-3. This VC-3 is aligned along with TU3 pointers to form a TU-3. The TU-3 gets multiplexed into a TUG-3. The TUG-3 gets multiplexed (x3) into a higher-order VC-4, which in turn gets aligned with AU-4 pointers to form an AU-4. This AU-4 gets multiplexed (x1) into an AUG-1 that can get multiplexed (x4) into a higher-order AUG-4 or multiplexed (x1) along with MSOH and RSOH bytes to form an STM-1.

SDH Multiplexing of DS3 Signals High-level DS3 (44.736-Mbps) signals are also mapped to the C-3 container. However, the C-3 mapping for DS3 takes place differently as compared to the C-3 mapping for E3. This is illustrated in Figure 6-4. The DS3 gets mapped to the C-3 container that gets directly mapped with the VC-3 POH bytes to the higher-order VC-3 virtual container. The VC-3 is aligned along with AU-3 pointers into an AU-3. The AU-3 can get multiplexed (x3) into an AUG-1 or directly multiplexed (x1) to form an STM-0 signal. The AUG-1 can get further multiplexed (x4) to an AUG-4 or directly multiplexed (x1) along with MSOH and RSOH bytes to form an STM-1. SDH Multiplexing of E4 Signals High-level signals, such as an E4 (139.264 Mbps), are mapped to the C-4 container. As illustrated in Figure 6-4, the C-4 container along with the VC-4 POH bytes is mapped to a higher-order VC-4 virtual container. The VC4 is aligned along with AU-4 pointers into an AU-4. The AU-4 then gets multiplexed (x1) to an AUG-1. The AUG-1 could get further multiplexed (x4) to an AUG-4 or directly multiplexed (x1) along with MSOH and RSOH bytes to form an STM-1. < Day Day Up >