Lecture 10: Memory Organization y g

Todays topics: Cache hierarchies Cache Direct Map

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Locality y
Temporal l T l locality: if you used some d t recently, you lit d data tl will likely use it again

Spatial locality: if you used some data recently, you p y y y y will likely access its neighbors

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Memory Hierarchy y y
The faster Th f t memories are more expensive per bit th i i than the slower memories and thus smaller.

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Memory Hierarchy y y
A you go f th capacity and latency increase As further, it dl t i

Registers 1KB 1 cycle y

L1 data or instruction Cache 3 32KB 2 cycles

L2 cache 2MB 15 cycles 5 cyc es

Memory 1GB 300 cycles y

Disk 80 GB 10M cycles

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Cache
Wh d caches work? Why do h k? assume that there are two-level memory No hierarchy: average access time for data = 300 cycles 32KB 1-cycle L1 cache that has a hit rate of 95%: average access time = 0.95 x 1 + 0.05 x (301) = 16 cycles l
CPU Word access cache 512 x 8 Main Memory 32K x 8 Block transfer
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Accessing the Cache ( g (direct-mapped) pp )

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Accessing the Cache ( g (direct-mapped) pp )

00000

1220 2340 3450 4560 5670 6710 777 27 Cache 6710 Index 000 Tag 00 Data 1220

00777 01000

01777 02000 27777

Main memory
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Example ( p (direct-mapped) pp )
22(10110) 26(11010) 22(10110) 26(11010) 16(10000) 3 (00011) 16(10000) 18(10010)

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Example ( p (direct-mapped) pp )
22(10110) 26(11010) 22(10110) 26(11010) 16(10000) 3 (00011) 16(10000) 18(10010)

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Direct-mapped pp

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Direct-mapped pp

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Example ( p (Bits in a cache) )

How many total bits are required for a direct mapped cache with 16 KB of direct-mapped data and 4-word blocks, assuming a 32-bit address? Number f blocks=2^10 N b of bl k 2^10 Number of bits in each block:128 bits Tag=32-10-2-2 Valid bit=1 Total cache size:

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Computing Cache blocks p g

Block address=

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Direct-mapped pp

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Handling Cache Misses

1. Send the original PC value ( g (current PC 4) to the memory. ) y 2. Instruct main memory to perform a read and wait for the memory to complete its access. 3. Write the cache entry, putting the data from memory in the data portion of the entry writing the upper bits of the address (from the entry, ALU) into the tag field, and turning the valid bit on. 4. 4 Restart the instruction execution at the first step which will refetch step, the instruction, this time finding it in the cache.

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Handling Write
1. Write-through g Example: 10% of the instructions are stores the CPI without cache misses was 1.0 100 extra cycles on every write CPI becomes: 1.0 + 100 * 10% = 11 Solution: write buffer 2. Write-back

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