An investigation on the effects of nonidealities existed in implementation of a binary weighted current source digital to analog converter

Hani Esmaeelzadeh Mohammadreza Fatemi Sharif University of Technology Tehran,Iran

ii

Abstract

Digital to analog converters are systems that work as an interface between digital and analog domains. These systems accept digital codes as input and generate their related analog values at the output. Among different types of digital to analog converters, binary weighted current source digital to analog converters are noticeable due to their simplicity in implementation and high speed performance. In this thesis, one of the mostly used architectures of binary weighted current source digital to analog converters is firstly introduced and then different aspects of nonidealities that a designer faces in implementation of this system will be discussed. With the information obtained of this thesis, the designer will be aware of the effects of the implementation nonidealities on the digital to analog converter functionality and prepare suitable considerations to achieve the closest approximation of the ideal digital to analog converter.

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Contents

CHAPTER 1: Data Converter Basics 1.1 Conversion basics 2

1.2 Data Converters Non-idealities 1.2.1 Offset error 1.2.2 Gain error 5 6

1.2.3 Differential non linearity error 1.2.4 Integral non linearity error CHAPTER 2: Binary weighted current source DAC 2.1 Unit element current source DAC 2.2 Binary weighted current source DAC 10 12

7 8 10

2.3 Realizing binary weighted current source DAC 2.3.1 Implementation of current sources 2.3.2 Implementation of switches 2.4 current to voltage converter 15 15 13

13

CHAPTER 3: Non Ideality Effects on Binary Weighted DAC Functionality 17 3.1 Reference current generation error 3.2 Mismatch in current mirrors
iv

18 20

3.3 effect of ON-resistance of switches 3.4 effect of OFF-resistance of switches 3.5 effect of offset error of OpAmp 34

26 30

3.5.1 Input offset voltage of the emitter coupled pair 3.5.2 Input offset voltage of the source coupled pair CHAPTER 4: Conclusion References 42 40

36 38

Appendix A Appendix B Appendix C Appendix D Appendix E

43 44 45 46 47

CHAPTER 1
Data Converter Basics

Nowadays most of electronic systems are operating based on digital signal processing. Its the result of benefits that digital processing offers versus conventional analog one, such as: Direct benefit from the down scaling of VLSI technology Not sensitive to analog noise Enhanced functionality & flexibility Amenable to automated design & test Arbitrary precision Provides inexpensive storage capability Robustness to supply and process variations

So its said the world is becoming more digital every day. But the real world is analog and many of quantities we are dealing with, like temperature, velocity, voice, music and etc are analog signals. Therefore, if we want to process these signals digitally to obtain its benefits, its necessary to have a device works as interface between analog world and digital processor. On the other hand, there should be a device to return the processed signals in analog. These devices are called Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC), respectively. Figure 1 shows the idea expressed above. 1

Figure 1: Interface between analog world and digital processor

1.1

Conversion basics

In order to transfer analog values to digital domain, we should assign a unique digital code to each value and when getting back to analog, each value will be reconstructed based on the code. If B bits are used then we are limited to different codes. To have infinite number of codes, infinite number of bits should be used, but its not possible. Since there is infinite number of analog values, mapping of analog values to digital codes could not be one to one, so we have to choose a limited analog interval and divide it into subintervals and relate each subinterval to a code.Figure 2 shows this concept for a 2-bit ADC applied over (a,b) interval.

a+

a+2

a+3

b= a+4

00

01

10

11

Figure 2: analog subintervals and assigned digital code for a 2-bit ADC

As it can be seen, each subinterval has the length of which can be obtained from (1-1).

(1-1)

where b-a is the range of input variations called the full scale range, FSR, of ADC, for instance if the analog quantity is voltage or current then full scale range is V FS or IFS, respectively. If we assume that there is a point in each subinterval that the associated output code is the exact conversion of it, then in conversion of other values in the subinterval we are suffering from an error. If this point is the start point or the end point of the subinterval, then maximum error will be the length of subintervals, . It can be proved that if the midpoint is chosen, the worst case error will be minimized to /2. So as its shown in figure 1-3, all subintervals are shifted by /2 in order to have minimum error. Now it can be seen that for the input interval of (0,FS), values 0, , 2, 3, ( ) are assigned to codes 0, 1, 2, 3, ,( ). Since increasing input value by will result in an increment of one LSB in digital code, is called LSB, too.

Figure 1-3: Ideal ADC transfer characteristic

Similarly a DAC will get digital codes 0, 1, 2, 3, ,(

)as input and generate

0, , 2, 3, ( of a 3-bit DAC.

) as output.Figure1-4 shows the ideal transfer characteristic

Figure 1-4: Ideal DAC transfer characteristic

Generally, the output of a DAC for input code ith is i. If digital n-bit binary code is bB-1b1b0 then i = bB-12B-1 + + b121 + b020 Vout,DAC = (bB-12B-1 + + b121 + b020 ) Vout,DAC = (bB-12B-1 + + b121 + b020 ) Vout,DAC = VFS ( ++ + ) (1-2) (1-3) (1-4) (1-5)

1.2 Data Converters Non-idealities

In practice, data converters deviate from their ideal transfer characteristic by following errors:

Offset Gain error Differential Nonlinearity, DNL Integral Nonlinearity, INL

1.2.1 Offset error

The offset describes a shift for zero input. Offset is an error that can affect either an ADC or a DAC. Figure 1-5 compares the input-output transfer characteristics of a real and an ideal ADC. The offset changes the transfer characteristics so that all the quantization steps are shifted by the ADC offset. The offset of a DAC is defined by using the real response of Figure 1-6. The analog signal generated by the digital code 0 0000 is the DAC offset. The offset can be measured in LSB or absolute value (volts or amperes).

Figure 1-5: Offset error for an ADC 5

Figure 1-6: Offset error for a DAC

1.2.2Gain error
Gain error is the error on the slope of the straight line interpolating the transfer curve. For an ideal converter the slope is DFS/XFS, where DFS and XFS are the full-scale digital code and full-scale analog range respectively. Since DFS represents XFS, we normally say that the ideal slope is one. The gain error defines the deviation of the slope of a data converter from the expected value. Figure 1-7 shows the input-output diagrams for a real and an ideal ADC (a) and DAC (b).Another measure of the gain error is given by the difference between the input voltage causing a transition to the full scale and the reference (minus half LSB). When using this definition the gain error is known as the full scale error.

Figure 1-7: Gain error for an analog-to-digital (a) and a digital-to-analog (b) converter.

1.2.3Differential Nonlinearity (DNL)

DNL is the deviation of the step size of a real data converter from the ideal width of the bins . Assuming that Xk is the transition point between successive codes k 1 and k, then the width of the bin k is r(k) = (Xk+1 Xk); the differential non-linearity is ( )
( )

(1-6)

This function is also known as the differential linearity error (DLE). The DNL can be also measured in Volts (or Amperes when the input is a current). The maximum differential nonlinearity is the maximum of |DNL(k)| for all k. Often the maximum differential nonlinearity is simply referred to as DNL. An additional specification given by some data sheets is the root mean square(RMS) of the DNL. { ( ) } (1-7)

Figure 1-8: ADC DNL error

Figure 1-9: DAC DNL error

1.2.4 Integral Nonlinearity (INL)

INL is a measure of the deviation of the transfer function from the ideal interpolating line. Another definition of the integral non-linearity measures the deviation from the endpoint-fit line. The use of the endpoint-fit line corrects the gain and offset error. The second definition is chosen as standard since it is more informative. The maximum of the INL is the maximum of |INL(k)| for all k. Often, it is referred to as just INL. The INL, as for the DNL, is measured in LSB. It can also be measured using absolute value (Volts or Amperes). Let us consider the endpoint-fit line which is the transfer curve with corrected offset and gain. An iterative use of (1-7) gives the transition point between codes after correction, ( ) ( ) { ( )} (1-8)

) gain error; kosis the offset measured in LSB. Since the where ( offset compensated for the endpoint-fit line is kos , the INL inLSB becomes 8

( )

( )

()

(1-9)

showing that the INL at bin k is the running sum of the DNL corrected by the gain error. Figures 1-10 and 1-11 show the INL error for a 3-bit ADC and DAC on the corrected transfer characteristic, i.e. after correcting offset and gain errors.

Figure1-10: ADC Integral Nonlinearity

Figure 1-11: DAC Integral Nonlinearity

CHAPTER 2
Binary weighted Current Source DAC

Generally there are two ways to generate analog values based on the digital codes. As its said in chapter 1, the analog value corresponds to code i is i. So a DAC should sum i number of of a specific quantity. This quantity could be electrical charge, current, voltage or any other quantity that can be expressed electrically. The DAC that uses this approach for conversion operation is called unit element. The name comes from the fact that output is the summation of unit elements of the quantity. The second way to implement a DAC is to use (1-5). Based on this equation the output could be generated by summing weighted elements of the quantity instead of unit elements. Since the elements are weighted in a binary way, these types of DAC are called binary weighted.

2.1Unit Element Current Source DAC

In unit element current source architecture the quantity used in summation is current. As shown in figure 1-12, there are identical current sources that the value of each one is

11

(2-1)

If the input code is i then i number of current sources switched to output. Therefore, the output current is Iout = iIu = i (2-2)

Iout

Iu

I Iu

Iu

Figure2-1: unit element current source DAC If voltage is the desired output quantity, a resistive load can be connected to the output node as a current to voltage converter and then VFS = IFS RL (2-3)

As it can be guessed each input code has B binary digits, b B-1 b0, and there are 2B-1 switches. So a B-to-2Bdecoder is needed to determine about the state of each switch. Functional operation of a 3-to-8 decoder is shown below Binary Code Decoder output 000 001 010 011 100 101 11 0000000 0000001 0000011 0000111 0001111 0011111

110 111

0111111 1111111

For large values of B, complex decoder and too many switches is the main weakness of unit element architectures.

2.2 Binary Weighted Current Source DAC

As its said, binary weighted architectures should have weighted elements. So instead of using identical current sources, binary weighted current sources are used. According to (1-5), if bit bi is 1 then the associated switch is turning on and the weighted current related to it participates in output current.

Iout bB-1
I

b1
I 2Iu

b0 Iu

2B-1Iu I

Figure 2-2: binary weighted current source DAC Unlike unit element one, in this architecture, no decoder is needed and binary digits are directly applied to the switches. In addition just B switches are needed. For accuracy reasons instead of making a current source with value nIu ,n identical current sources, with value of Iu, are used in parallel. So there is no difference in the number of current sources between these two architectures.

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2.3Realizing Binary Weighted Current Source DAC

What is existed in real electronic circuits, are transistors, resistors, capacitors and maybe inductors. So current sources, switches and should be realized with these basic elements. 2.3.1 Implementation of current source A current source simply can be a transistor which is biased in saturation region if its a MOSFET transistor, or active region in the case of BJT transistors. But an exact constant current could not be guaranteed in these implementations. For example, the bias current of CE and CS stages is a function of the supply voltagea serious issue, because in practice, this voltage experiences some variation. The rechargeable battery in a cell phone or laptop computer, for example, gradually loses voltage as it is discharged, thereby mandating that the circuits operate properly across a range of supply voltages. Another critical issue in biasing relates to ambient temperature variations. A cell phone must maintain its performance at -20C in Finland and +50C in Saudi Arabia. Fortunately, an elegant method of creating supply- and temperatureindependent voltage sand currents exists and appears in almost all microelectronic systems. Called the bandgap reference circuit and employing several tens of devices, this scheme is studied in more advanced books [5].In order to avoid supply and temperature dependence, a bandgap reference can provide a golden current while requiring a few tens of devices. Therefore a method of copying the golden current without duplicating the entire bandgap circuitry should be used. Current mirrors serve this purpose. Figure 2-3 conceptually illustrates this goal here. The golden current generated by a bandgap reference is read by the current mirror and a copy having the same characteristics as those of IREF is produced. For example, Icopy = IREF.[4]

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Figure 2-3: Concept of current mirror.

The simplest implementation of current mirror box shown in Figure 2-3, with MOSFET transistors shown in Figure 2-4.

Figure 2-4: simple current mirror with MOSFET transistors

Since MOS devices have finite output resistance, Icopy will have another component that depends on output voltage. Figure 2-5 shows the circuit model including this effect.
Icopy RCS

Figure 2-5: Circuit model of real current mirror

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According to this investigation, in a current source based DAC, to have relatively exact current sources, a reference current source with value Iu is provided by a bandgap and 2B-1 copies will be generated. But the issue of limited output resistance still exists. Using more complex current mirror circuits will improve the output resistivity. 2.3.2 Implementation of switches Switches are implemented with transistors too. A simple MOS transistor shown in Figure 2-6 can operate as a switch. Vcont controls on and off states of the switch. In the binary weighted DAC introduced in section 2-2, binary digits will operate as Vcont of the switches.

Vcont A B A

Vcont B

Figure 2-6: MOS transistor as a switch

But MOS switches cannot operate that ideally shown in Figure 2-6. A real MOS transistor operates like a small and a large resistor in on state, Ron, and off state, Roff, respectively. More complex switches can be designed in order to have near ideal behavior. But the issue off non zero on state resistance and finite off resistance still exist.

2.4 Current to Voltage Converter

In many applications, we are interested to have voltage as the output quantity. In order to achieve this goal several ways exist. The simplest idea is connecting the output node to voltage supply through a resistive load.

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VCC

Iout bB-1
I

RLOAD
R

Vout

b1
I 2Iu

b0 Iu

2B-1Iu I

Figure 2-7: Current to voltage converter with resistive load

The output voltage of DAC is across the current sources and because of the limited output resistance of the current sources, variation of output voltage based on different input codes will result in current variation. Therefore DAC transfer characteristic will deviate from the ideal one. To overcome this issue, an operational amplifier can be used to isolate the output nodes of DAC and current sources. Based on the architecture shown in Figure 2-8, OpAmp will kept output voltage of current sources equal to virtual ground.
R Iout bB-1
I

b1
I 2Iu

b0 Iu

Vout

2B-1Iu I -Vss

Figure 2-8: DAC with Op Amp as current to voltage converter

While previous issue has been solved, nonidealities of Op Amp, like offset and limited gain, are introduced to the circuit. But they are not as annoying as Figure 2-7 circuits issue. In the next chapter will focus on this architectures non ideal effects in more details. 16

CHAPTER 3
Non Ideality Effects on Binary Weighted DAC Functionality

As we said in previous chapter, there are some nonidealities in realization of introduced binary weighted DAC. These effects cause deviation in DAC transfer characteristic and result in errors discussed in chapter 1, i.e. offset, gain error, DNL and INL. In this chapter we will try to investigate deviation of binary weighted current source functionality caused by nonidealities occur in implementation. Before starting our investigation, we first write a MATLAB code to verify our claims and findings. The basic MATLAB code that generates the ideal transfer characteristic and constructs the core of other codes is in appendix A. This code is written for an 8-bit DAC and for simplicity =Iu=Iref=1,so digital code i mapped to analog value i. Figure 3-1 shows the ideal characteristic generated by this code. We will then change this code in order to add each non ideal effect.

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Figure 3-1: Ideal binary weighted current source DAC characteristic

3.1Reference Current Generation Error

As it is said in previous chapter, to increase accuracy of current sources, it is proposed to use a bandgap to generate a reference current and then copy it by current mirrors. Now if the bandgap or reference current generator has error itself, the overall functionality will be affected. To see the effect of reference current error, we suppose that it deviates from its ideal value by I. So new reference current will be Iref,new = Iref + I (3-1)

Since other currents are all a copy of reference current, they will all deviate by I from their ideal value Iu that is equal to Iref. Digit bi switches a current source that is made of 2i unit current source in parallel. So its current will be Ibi = 2iIu + 2iI = 2i(Iu+I) (3-2)

Therefore, we still have some weighted currents that the new unit current is 18

Iu,new=Iu+I

(3-3)

Based on the offset definition, offset is output value generated by code 0. In this case for code 0 still all current sources are switched off the output. So output value is zero and there is no offset error. Since error in reference current introduces a new step size, =Iu+I, which is consistent for all steps, therefore all steps scale uniformly and the last step that correspond to code 2B-1, changes to (2B-1)(Iu+I) instead of (2B-1)Iu and gain of the converter will be Gain =
( ( ) ( ) )

(3-4)

While the ideal gain should be Iu, or 1 LSB. So there is a gain error of I, that is equal to LSB. To calculate DNL and INL errors we should first correct the and this will move us to ideal

gain error and it means multiply all steps in

transfer characteristic. So DNL and INL errors are both equal to zero if an error in reference current generation occurs. The MATLAB simulation result, shown in Figure 3-2, confirms what has been discussed above. In ideal case that shown with solid line, output value corresponds to end code, 255, is 255. But when I=10% Iref error in reference current is applied, end code output shifted to
.

(3-5)

That shown with dashed line. In addition the characteristic is linear indicating that there are no non linear errors, i.e. DNL and INL, and gain error is the only deviation. The MATLAB code can be found in appendix B.

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Figure 3-2: Error in reference current, solid, and ideal, dashed, characteristics

3.2 Mismatch in Current mirrors

Since the wafers surface which integrated circuits are fabricated on, is not uniform and dopants density varies from one point to other point on the wafer, consequently we cannot have fully matched and identical transistors. For instance if we want to fabricate MOS transistors on a wafer, characteristics of them like threshold voltage are different with each other. In addition in lithography process, error occurs in sizing of transistors, i.e. width and length of transistor are not the exact expected values. When identical current mirrors are aimed to be fabricated on a chip, inequality in the transistors prevents us from having equal currents. This current is different from one current mirror to another one and each one has its own current error. Because there is no knowledge about the value of error in each transistor its considered as a random effect. Sine each transistor error is independent of others and probability of occurrence of a specific error is uniform, central limit theory tells that the probability density function of errors in different transistors is a Gaussian function. (3-6) shows Gaussian function equation 21

( )

(3-6)

Where is the standard deviation and is the mean value of x. The mean value represents the designed value or the value considered in the design procedure. The standard deviation is a function of how mature is the fabrication process. Since all parameters that cause errors in current mirrors accuracy have Gaussian Probability Density Function, the overall current mirrors error will have Gaussian Probability Density Function. To see how the matching errors in current sources affect the DAC functionality, we make a random Gaussian error with zero mean value and standard deviation of 0.1 with randn function in MATLAB, then we add it to the exact value of current mirrors, therefore the mean value is shifted to I ref. Because its a random effect and is not linear it can be guessed that it has nonlinear effects on the DAC characteristics, i.e. DNL and INL. The related MATLAB code is in appendix C.

Figure 3-3: characteristic with error in matching current mirrors

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Figure 3-3 shows the transfer characteristics in the presence of Gaussian error. Because of the high 8-bit resolution, the error is not much clear. There is no offset error because for code 0 all current sources are switched off the output and the output is independent from the current error. The error for output value of each code is the summation of current sources errors that participate in generating the output value. So the variance of error in the output value will be the summation of variances of the participated current sources and the end point of the characteristic deviates from the ideal end point value. Consequently there is a gain error. The gain error for Figure 3-3, which is a random run of the MATLAB code, is -0.27% LSB/code. For calculating DNL and INL errors first the offset and gain error should be cancelled. Based on the output voltages that generated by MATLAB code, DNL is calculated after correcting gain error. Figure 3-4 shown the result achieved of simulation.

Figure 3-4: DNL error due to mismatching of current mirrors

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The worst case DNL is -1.48 in this simulation. It should be noted when the MALLAB code is run, Gaussian random numbers are generated and all other calculations are based on them, so each time that the code is run, different answers should be expected. INL error can be obtained by simply calculating the cumulative sum of DNL vector in MATLAB. cumsum is the MATLAB function that has this functionality and by applying this on DNL, INL vector for all codes is achieved and shown in Figure 3-5.

Figure 3-5: INL error due to mismatching of current mirrors

Worst case value of INL is 1.12 that occurs in code 188. Again it should be noted that because it is a random run, exact result will change in every simulation. But the mean value and standard deviation of errors are fixed. Now we will try to find an analytic approach to investigate what happens to DNL and INL when there are current mirror mismatches in more details. The output value is made by the sum of current mirrors. So absolute error that occurs in the output value is the summation of absolute errors occurred in the current of current mirrors. When input code changes to the next code, based on the binary 23

digits of the new code some of current mirrors switch off and some other new ones switch to the output node. Since DNL simply is the deviation of step widths from the ideal steps, it could be concluded that error in each step width is the summation of current sources which are switched on minus current source swhich are switched off. From the theory of statistics, we know that the variance of algebraic summation of some variables is equal to the summation of all variables variances. Therefore variance of each codes DNL is obtained by summing the variances of all current mirrors that are switched off and switched on. In binary weighted current source digital to analog converters, the worst case is occurring when transition is between codes 01111 and 1000.0. In this case all 2B-1 parallel current mirrors related to MSB switch on by digit b B-1, and all other current mirrors are switched off. So error of output step is the summations of errors have been occurred in all current mirrors. Since DNL is calculated by normalizing each steps error to ideal step width or 1 LSB as (3-6), the worst case DNL error will be obtained by (3-7). (3-6)
( )

(3-7)

Where variables 8).

is the current error of the current mirror number i. So if the variances of are given, variance of maximum DNL error could be calculated as (3-

(3-8)

And since all current mirrors are identical, their variances are equal, too. Therefore standard deviation of maximum DNL can be written as (3-9). ( ) (3-9)

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Where

that in the case of MATLAB simulation it

is set to 0.1 or 10% of Iref = Iu. So if we calculate the standard deviation of the 8-bit DACs DNL error that is simulated, based on (3-9) we will obtain DNLmax= 1.59 that is not too much far from the absolute value of maximum DNL extracted from the simulation results, 1.48. To derive an analytic equation for INL error, we first assume that n is the input code and it is intended to generate analog value n at the output. But because of the current mirrors error, what is really appearing at the output is A. we then define E=A-n as the INL error occurs in code n, because its the deviation of the DAC transfer characteristic from the ideal case. For generating code n, n numbers of current sources (mirrors) are switched to the output node. So the variance of the variable A would be . B is the difference of the output value related to input code, n,from the end code, N, and its a representation of the number of current sources which are switched off. As a result the variance of B will be calculated as( ) . Figure 3-6 represents all these concepts.

Figure 3-6: representation of INL error occurs on transfer characteristic

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Before calculating INL error of code n we first define have: ( ) ( )

, and so we
(3-10)

therefore, variance of E that is the variance of INL error is calculated as: ( ) ( )

(3-11) (3-12)

And the maximum value of INL errors variance occurs when r = 0.5, i.e. middle code of the range. What is usually thesised for INL error is the worst case INL or maximum INL error. By substituting r = 0.5 in (3-12), standard deviation of maximum INL error obtains as (3-13). (3-13)

As it is said, MATLAB simulation is based on an 8-bit DAC with 10% standard deviation in current mirrors, so (3-13) result in INLmax = 0.8 that is not too much far from the maximum value of INL error obtained, 1.12.

3.3Effect of ON-Resistance of Switches

As it is said in chapter 2, when a switch is implemented by transistors, it will deviate from an ideal switch function. A serious non ideality of transistor-based switches that affects the DAC functionality is the on-state resistance. If we consider on-state resistance of the switches, i.e. replace the on-switch with a finite resistor instead of short circuit, there will be a voltage drop on the switch that is relative to the current across it. It seems that the series resistor with a current source will not affect the current value. But current sources will be implemented by transistors, and as its said in previous chapter, there is a finite resistance in 26

parallel with a current source in the circuit model of current source/mirror. So variation of voltage at the output of current source will affect its current. Placing an OpAmp for transferring the currents of current sources while fixing the output nodes voltage of them is introduced as a solution. But on state resistance of switches will corrupt the aim of this design technique. Dropped voltage on the switches will decrease the output voltage of the current mirrors and consequently their currents. In order to model the on state resistance of switches we use a first order approximation. We suppose that in the absence of Ron of the switch, current mirrors are regulated to sink the desired current, I. voltage drop of Vss is existed across the current source and therefore is the current component flowing

through the resistor. When on state resistor of the switch is added to the model, output voltage of current source drops by V=Ron I and current portion of the current source output resistance is reduced to current source is reduced to ( ) (3-14)

. So the overall current of the

In MATLAB simulation, we consider ro = 500kfor each current mirror. In addition, it is worth noting that for digit bi, 2biunit current sources are placed in parallel and the overall output resistance will be decreased to .MATLAB code that is considered this issue is in appendix D. Ron is assume to be 500 and all current sources values are in mA.

27

Figure 3-7: Binary weighted DAC transfer characteristic whit switches model with Ron

Figure 3-7 shows the transfer characteristic of the binary weighted current source DAC with considering the on state resistance of switches. As it can be guessed, current mirror related to the MSB bit will have the worst case current reduction. Because it has the largest current and smallest output resistance, 128I u and ro/128, respectively. Therefore when the input code transits form 0111 to 1000, DACs output value will experience a falling transition. If we neglect MSB transition, the worst case will go to the bit just before the MSB. And the reason could be expressed as MSB case. The related transition is X011 to X100 where X is the MSB. This case will occur two times, once for X=0 and other one when X=1.By the same explanation other binary digits will cause falling effect when it is their turn to transit. The current reduction of all current mirrors results in lower output value for the end code point and so there will be a negative gain error. End code output value of the simulation result is 210.31 and therefore characteristics gain error will be -0.17 LSB/code. 28

There is no offset error due to the addition of the on state resistance of switches to the DAC model, because output value is still zero for the input zero code. The non linear behavior of the transfer characteristic shows that it experiences DNL and INL errors. In order to obtain DNL and INL characteristics, we first correct the gain error and then calculate them as expressed in previous subsection. Figure 3-8 shows the DNL error occurs due to on state resistance of the switches. Based on the transfer characteristic of Figure 3-7, it could be guessed that the maximum DNL occurs at the midpoint of the range and transition of each bit that has the larger numerical value causes larger DNL error. Figure 3-8 shows the DNL error characteristic that confirms this conclusion. INL error is obtained by integration of DNL errors. As it is shown in Figure 3-9 the maximum INL error again occurs at the midpoint of the input range. What is concluded of this discussion is, if we are interested in a desired DNL and INL accuracy, we should design switches with maximum on state resistance carefully and as the DNL and INL characteristics are suggesting, its better to down scale the on state resistance as numerical value of digits increases in switch design step.

Figure 3-8: DNL error occurs due to on state resistance of switches

29

Figure 3-9:INL error occurs due to on state resistance of switches

3.4Effect of OFF-Resistance of Switches

As expressed in previous section, real world switches do not behave as an ideal short circuit in on state, and they are modeled by a resistor. This non ideality also exists in off state. When a switch is in its off mode, instead of an ideal open circuit, it should be modeled by a relatively large resistor, Roff. If we consider ideal current sources, flowing current through a large Roff will cause a large voltage drop on it. But since the current source is ideal, its functionality will not be affected and its current is still crossing through the switch. Therefore the switch cannot turn the current off ever. Fortunately, current sources are not ideal. As the voltage drop on the switch increases, current source portion decreases with the same value. If we assume current mirrors are constructed by MOS transistors, then they need a minimum voltage for operating in saturation region. Therefore, since large off state resistor takes a large portion of the supply voltage, transistors of the current source are shifted to the triode region that the overall current source can be modeled by a small triode region resistance of transistors. Off resistance of switch is too much 31

larger than the triode region resistance of the current source. So it can be assumed that when a switch is in its off state, a current equal to is across it.

Figure 3-10: Transfer characteristic with including off state resistance of switches

In MATLAB code of appendix E, off state resistance, ROFF, is considered. In this simulation ROFF is assumed to be 1000 k and Vss = 5v, so off state current of each switch is predicted to be 5A. For offset error calculation, all B = 8 switches are in their off state and the overall off current for zero input code is 5 A * 8 = 40A. because the current to voltage converters resistance is 1k , offset error of the digital to analog converter will be 40mv or 0.04 volt confirmed by MATLAB simulation result. Figure 3-10 shows the zoomed transfer characteristic of the digital to analog converter around input code zero, it can be seen that there is an offset error of 0.04 volt.

31

As it can be guessed, summation of some constant current components related to off state switches will cause non linearity in digital to analog converter characteristic. to calculate DNL and INL errors we should first omit the effect of offset error which is done by shifting the output axis in a way that the output for zero input code becomes zero. The gain error is cancelled in a similar way as explained in previous MATLAB codes.

Figure 3-11: DNL error occurs due to off state resistance of switches

32

Figure 3-12: INL error occurs due to off state resistance of switches

Figure 3-11 and 3-12 shows the simulation results for DNL and INL, respectively. Usually in practical designs, we attempt not to put current sources in triode region because returning them from triode region to saturation is too slow and the DAC operation would be slow. So we should employ a circuit that does not put the current mirrors in the triode region during switch off state. The circuit shown in Figure 3-13 is proposed for this aim. Its a simple differential source/emitter coupled pair used in the non linear region, i.e. input differential voltage is much larger than small signal constraint. So when the input voltage is applied, all the current is steered to one differential arm. In this configuration, the current source does not experience its triode region. When turning off the switch is intended, all the current is sink of the vdd instead of OpAmp input node. The trade off here is the increased power consumption. 33

VCC IBi

VCC IBi

VBias

bi

VBias

bi

Figure 3-13: high speed current switch

It may seems that there is no off state resistance effect in the circuit, but in reality a very small portion of the current source crosses the off transistor due to channels finite resistance in MOS transistors that is a very large resistor in the order of hundreds of Mega ohm. For BJTs the reverse saturation current is existed in off region which is in the order of nano Amperes. So an equivalent off resistance can be defined.

3.5Effect of offset error of OpAmp

As explained in previous chapter, an OpAmp is employed to relax the digital to analog converter from the finite output resistance of current sources. Using an OpAmp introduces some issues in the DAC operation that should be considered during design procedure. These issues come from the non ideality of OpAmp. In this section we investigate the offset error of OpAmp and try to come to an equation for this effect. An important aspect of the performance of differential amplifiers is the minimum dc and ac differential voltages that can be detected. The presence of component mismatches within the amplifier itself and drifts of component values with temperature produce dc differential voltages at the output that are indistinguishable from the dc component of the signal being amplified. Also, such mismatches and drifts cause nonzero common mode to differential mode 34

gain as well as nonzero differential to common mode gain to arise. Nonzero Acm-dm is especially important because it converts common mode inputs to differential outputs, which are treated as the desired signal by subsequent stages. In many analog systems, these types of errors pose the basic limitation on the resolution of the system, and hence consideration of mismatch induced effects is often central to the design of analog circuits. For differential amplifiers, the effect of mismatches on dc performance is most conveniently represented by two quantities, the input offset voltage and the input offset current. These quantities represent the input referred effect of all the component mismatches within the amplifier on its dc performance. As illustrated in Figure 3-14, the dc behavior of the amplifier containing the mismatches is identical to an ideal amplifier with no mismatches but with the input offset voltage source added in series with the input and the input offset current source in shunt across the input terminals. Both quantities are required to represent the effect of mismatch in general so that the model is valid for any source resistance. For example, if the input terminals are driven by an ideal voltage source with zero resistance, the input offset current does not contribute to the amplifier output, and the offset voltage generator is needed to model the effect of mismatch. On the other hand, if the input terminals are driven by an ideal current source with infinite resistance, the input offset voltage does not contribute to the amplifier output, and the offset current generator is needed to model the effect of mismatch. These quantities are usually a function of both temperature and common mode input voltage. In the next several sections, we calculate the input offset voltage of the emittercoupled pair and the source-coupled pair.

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Figure 3-14: Equivalent input offset voltage (Vos) and current (Ios) for a differential amplifier. (a) Actual circuit containing mismatches. (b) Equivalent dc circuit with identically matched devices and the offset voltage and current referred to the input.

3.5.1Input Offset Voltage of the Emitter-Coupled Pair

The predominant sources of offset error in the emitter-coupled pair are the mismatches in the base width, base doping level, and collector doping level of the transistors, mismatches in the effective emitter area of the transistors, and mismatches in the collector load resistors. To provide analytical results simple enough for intuitive interpretation, the analysis will be carried out assuming a uniform-base transistor. The results are similar for the non uniform case, although the analytical procedure is more tedious. In most instances the dc base current is low enough that the dc voltage drop in rb is negligible, so we neglect rb . Consider Figure 3-15 with dc signals so that Vi1 = VI1, Vi2 = VI2, Vo1 = VO1, and Vo2 = VO2. Let VID = VI1 - V12. Also, assume that the collector resistors may not be identical. Let Rcl and Rc2 represent the values of the resistors attached to Q1 and Q2, respectively. From KVL around the input loop, (3-15)

36

Therefore, (3-16) The input offset voltage Vos is equal to the value of VID = VI1 VI2 that must be applied to the input to drive the differential output voltage VOD = VO1 - VO2 to zero. For VOD to be zero, Ic1 * Rc1 = IC2 * RC2 therefore, (3-17) Therefore, [( )( )(
( ( ) )

)]

(3-18)

( ) is the total base impurity doping per unit area for Where ( ) and Q1 and Q2 , respectively. This expression relates the input offset voltage to the device parameters and RC mismatch. Usually, however, the argument of the log function is very close to unity and the equation can be interpreted in a more intuitively satisfying way. In the following section we perform an approximate analysis, valid if the mismatches are small.

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Figure 3-15: Emitter-coupled pair circuit diagram

3.5.2Input Offset Voltage of the Source-Coupled Pair

MOS transistors inherently provide higher input resistance and lower input bias current than bipolar transistors when the MOS gate is used as the input. This observation also applies to differential-pair amplifiers. The input offset current of an MOS differential pair is the difference between the two gate currents and is essentially zero because the gates of the input transistors are connected to silicon dioxide, which is an insulator. However, MOS transistors exhibit lower transconductance than bipolar transistors at the same current, resulting in poorer input offset voltage and common-mode rejection ratio in MOS differential pairs than in the case of bipolar transistors. In this section we calculate the input offset voltage of the source coupled MOSFET pair. Consider Figure 3-16 with dc signals so that Vi1 = VI1, Vi2 = VI2, Vol = VO1, and Vo2 = VO2. Let VID = VI1 - VI2, Also, assume that the drain resistors may not be identical. Let RD1 and RD2 represent the values of the resistors attached to M1 and M2, respectively. KVL around the input loop gives (3-19) Therefore, (3-20)
( )

( )

(3-21)

As in the bipolar case, the input offset voltage Vos is equal to the value of VID = VI1 VI2 that must be applied to the input to drive the differential output voltage VOD = VO1 - VO2 to zero. For VOD to be zero, ID1 * RD1 = ID2 * RD2; therefore,
( )

( )

(3-22)

38

Subject to the constraint that ID1 * RD1 = ID2 * RD2. To investigate the OpAmp offset on the DACs functionality, we use Figure 3-14 (b) model. So output voltage is the summation of desired output analog value that exists across the feedback resistance of the OpAmp and offset voltage of the OpAmp. Therefore, OpAmp offset is translated directly to the DACs offset.

Figure 3-16: n-channel MOSFET source coupled pair

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CHAPTER 4
Conclusion

Digital to analog converter is a system that accepts a digital input code and generates an analog value that is its counterpart in analog domain. In this thesis we first introduce a binary weighted DAC architecture in chapter 2 and then in chapter 3 try to investigate nonidealities that may occur in implementation of it. Results that obtained of studying about the introduced binary weighted DAC are as follows: Error in generating the golden fixed current that all other current mirrors copy it will result in a gain error in DAC characteristic. Mismatching of current mirrors that its distribution function is a Gaussian function will result in gain, DNL and INL errors. Mismatch is forced by the technology and it is circuit designers task to use an approach to minimize it. On state resistance of the switches will cause in reduction of current of current mirror and because its not uniform for all bits, in addition to gain error that is a linear error, nonlinear effects will be seen in DAC 41

transfer characteristic. Reducing the on state resistance of each switch, proportional to the current that flows through it, will omit the DNL and INL errors. Off state resistance of the switches allows a very small current to flow across the switch when its off, so there would be an offset error in DAC characteristic. Using current differential switches will improve the off resistance effectively. If there are mismatches in OpAmp design, offset voltage of the OpAmp will appear directly in DAC characteristic as its offset. As a conclusion of this thesis, there are a lot of nonideal effects in implementation that a professional circuit designer will try to reduce them, firstly by increasing his knowledge about the sources of these effects and then finding some effective solutions to reduce them on the circuit functionality.

41

References

[1] Franco Maloberti, Data converters Springer, 2007 [2] Lecture notes of Haideh Khorramabadi, UCB, Department of Electrical Engineering and Computer Sciences [3] B. Razavi, Principle of data conversion system design IEEE press, 1995 [4] B. Razavi, Fundamental of Microelecreonics Wiley, 2008 [5] B. Razavi, Design of Analog CMOS Integrated Circuits McGraw-Hill, 2001. [6] P. Gray, P.J. HURST, S.H. LEWlS, R.G. MEYER, Analysis and design of analog integrated circuits WlLEY, fourth edition, 2001

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Appendix A
clc B=8; code=0:2^B-1; Iref=1; R = 1; I = Iref*ones(1,2^B-1); Iw= zeros(1,B); help_var=0; for i=0:B-1 for j=1:2^i help_var=help_var+1; Iw(i+1)= Iw(i+1)+I(help_var); end end help_var=0; for b7=0:1 for b6=0:1 for b5=0:1 for b4=0:1 for b3=0:1 for b2=0:1 for b1=0:1 for b0=0:1 help_var=help_var+1; Iout(help_var) = b0*Iw(1)+b1*Iw(2)+b2*Iw(3)+b3*Iw(4)+b4*Iw(5)+b5*Iw(6)+b6*Iw(7)+b7*Iw(8); Vout(help_var)=R*Iout(help_var); end end end end end end end end plot(code,Vout) title('Ideal binary weighted current source DAC charectristic') xlabel('Digital code') ylabel('Analog output voltage')

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Appendix B
clc B=8; code=0:2^B-1; Iref=1+delta_I; delta_I=0.1*Iref; R = 1; I = Iref*ones(1,2^B-1); Iw= zeros(1,B); help_var=0; for i=0:B-1 for j=1:2^i help_var=help_var+1; Iw(i+1)= Iw(i+1)+I(help_var); end end help_var=0; for b7=0:1 for b6=0:1 for b5=0:1 for b4=0:1 for b3=0:1 for b2=0:1 for b1=0:1 for b0=0:1 help_var=help_var+1; Iout(help_var) = b0*Iw(1)+b1*Iw(2)+b2*Iw(3)+b3*Iw(4)+b4*Iw(5)+b5*Iw(6)+b6*Iw(7)+b7*Iw(8); Vout(help_var)= R*Iout(help_var); end end end end end end end end plot(code,Vout) title('Error in current reference binary weighted current source DAC charectristic') xlabel('Digital code') ylabel('Analog output voltage')

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Appendix C
clc B=8; code=0:2^B-1; delta_I=0; Iref=1+delta_I; R = 1; I = Iref*ones(1,2^B-1)+ 0.1*randn(1,2^B-1); Iw= zeros(1,B); help_var=0; for i=0:B-1 for j=1:2^i help_var=help_var+1; Iw(i+1)= Iw(i+1)+I(help_var); end end help_var=0; for b7=0:1 for b6=0:1 for b5=0:1 for b4=0:1 for b3=0:1 for b2=0:1 for b1=0:1 for b0=0:1 help_var=help_var+1; Iout(help_var) = b0*Iw(1)+b1*Iw(2)+b2*Iw(3)+b3*Iw(4)+b4*Iw(5)+b5*Iw(6)+b6*Iw(7)+b7*Iw(8); Vout(help_var)= R*Iout(help_var); end end end end end end end end plot(code,Vout) title('Error in matching current mirrors') xlabel('Digital code') ylabel('Analog output voltage')

cVout = Vout*255/Vout(256); DNL = [diff(cVout)-1 0]; INL = cumsum(DNL); figure(2) plot(code,DNL) figure(3) plot(code,INL)

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Appendix D
clc B=8; code=0:2^B-1; Iref=1; R = 1; I = Iref*ones(1,2^B-1); Iw= zeros(1,B); help_var=0; for i=0:B-1 for j=1:2^i help_var=help_var+1; Iw(i+1)= Iw(i+1)+I(help_var); end end Ro = 500./Iw; Iw = Iw.*(1-1./Ro); help_var=0; for b7=0:1 for b6=0:1 for b5=0:1 for b4=0:1 for b3=0:1 for b2=0:1 for b1=0:1 for b0=0:1 help_var=help_var+1; Iout(help_var) = b0*Iw(1)+b1*Iw(2)+b2*Iw(3)+b3*Iw(4)+b4*Iw(5)+b5*Iw(6)+b6*Iw(7)+b7*Iw(8); Vout(help_var)= R*Iout(help_var); end end end end end end end end plot(code,Vout) title('Error occurs due to on state resistance of switches') xlabel('Digital code') ylabel('Analog output voltage') cVout = Vout*255/Vout(256); DNL=[diff(cVout)-1,0]; figure(2) plot(code,DNL) title('DNL error occurs due to on state resistance of switches') xlabel('Digital code') ylabel('DNL error') INL=cumsum(DNL) figure(3) plot(code,INL)

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title('INL error occurs due to on state resistance of switches') xlabel('Digital code') ylabel('INL error')

Appendix E
clc B=8; Vss=5; Roff=1000 code=0:2^B-1; Iref=1; R = 1; Ioff = Vss/Roff; I = Iref*ones(1,2^B-1); Iw= zeros(1,B); help_var=0; for i=0:B-1 for j=1:2^i help_var=help_var+1; Iw(i+1)= Iw(i+1)+I(help_var); end end help_var=0; for b7=0:1 for b6=0:1 for b5=0:1 for b4=0:1 for b3=0:1 for b2=0:1 for b1=0:1 for b0=0:1 help_var=help_var+1; Iout(help_var) = b0*Iw(1)+b1*Iw(2)+b2*Iw(3)+b3*Iw(4)+b4*Iw(5)+b5*Iw(6)+b6*Iw(7)+b7*Iw(8); Iout(help_var) = Iout(help_var)+(1-b0)*Ioff+(1b1)*Ioff+(1-b2)*Ioff+(1-b3)*Ioff+(1-b4)*Ioff+(1-b5)*Ioff+(1-b6)*Ioff+(1b7)*Ioff; Vout(help_var)= R*Iout(help_var); end end end end end end end end plot(code,Vout) title('Error occurs due to on state resistance of switches') xlabel('Digital code') ylabel('Analog output voltage')

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cVout = (Vout-Vout(1))*255/(Vout(256)-Vout(1)); DNL=[diff(cVout)-1,0]; figure(2) plot(code,DNL) title('DNL error occurs due to on state resistance of switches') xlabel('Digital code') ylabel('DNL error') INL=cumsum(DNL) figure(3) plot(code,INL) title('INL error occurs due to on state resistance of switches') xlabel('Digital code') ylabel('INL error')

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