INTRODUCTION TO ADDERS IN QUARTUS

Prepared by: Steven Medina

PURPOSE The purpose of this lab is to learn how to use Quartus software. Most, if not all of you have never used this software packages. This lab is a step-by-step guide on how to create a Quartus project file (qpf), a block diagram file (bdf), a vector waveform file (vwf), and VHDL (there are many interpretations for this acronym, but HDL stands for Hardware Description Language). You will be creating a simple full adder. This will be done using both VHDL and block diagram files in Quartus. Quartus is an important tool in developing digital circuits. Before an engineer builds a building, he has an architect design it. The design then may be simulated in special software to see if is structurally stable. This is what Quartus does for us. We use this software to design different kinds of digital circuits before we implement them. These designs can then be tested on an FPGA (Field Programmable Gate Array) chip. We will save the FPGA chips for another semester. The flowchart below gives more detail on the design process of digital circuits.

Figure 1: Design flowchart for a digital circuit.

Some of the steps in the above flowchart are a little more electrical engineering than computer science (such as power analysis). However, it is important to get familiar with the basic idea of how a circuit is designed. CREATING A NEW QUARTUS PROJECT FILE 1) Right click the desktop and click terminal. Type Quartus in the box that appears to open the Quartus software. Click on file new project wizard. The following box will appear.

Figure 2: New Project Wizard: Directory

You will see three boxes that you can type in. The top box will ask for the directory that you wish to save your project in. You can click on the small box to the right and save it to a directory you feel comfortable with. I recommend your USB drive, as the computers in this lab only give you 32MB of memory to work with. 2) After doing this, click on the middle text box. This is where you name your project. I recommend calling it full_adder. You will notice while typing in the second box, the name of the project will also be typed in the third box. Leave it like this for now. Click Next on the lower right corner. 3) You will now see the following menu.

Figure 3: New Project Wizard: Add Files

If we wanted to add pre-existing design files to our new project, this is where it would be done. However, we currently have no pre-existing files. For now, we will click Next. 4) The following menu will now appear.

Figure 4: New Project Wizard: Device Settings This screen allows the user to select the FPGA chip being used to test our design. However, as mentioned previously, we will save FPGA's for another semester. Click Finish to end the New Project Wizard.

FIRST BLOCK DIAGRAM FULL-ADDER A full-adder is an adder that takes 3 inputs (A, B, carry-in) and has 2 outputs (sum, carry-out). In case you are wondering, there is such a thing as a half-adder. The half-adder simply does not have a carry-in. We will concentrate on the full adder because it can be used to create much larger adders, such as the ripple-carry adder. A general schematic of a full-adder is shown below in figure 4.

Figure 4: Full Adder

The full-adder shown in figure 4 consists of two XOR gates and one Multiplexer. This will be implemented using both a block diagram file and VHDL code. The simulations will then be compared for logistic equality. 1) We begin by opening a blank block diagram file. Click File New to get the menu shown in figure 5a.

Figure 5a

Figure 5b

Click on the option that says Block Diagram/Schematic File (highlighted in figure 5a. This will give you a blank page filled with dots. This blank page will be our canvas for connecting logic gates (and larger circuits) together. The blank block diagram file is shown in figure 5b. 2) Now we want to start designing out adder. Double-click anywhere on the blank surface to bring up a menu of logic gates called the Symbol Tool. This menu is shown in figure 6a.

Figure 6a

Figure 6b

The symbol tool menu is where basic (or predefined) logic gates are selected. Click the + sign next to the directoy shown under libraries. You should not see 3 sub-menus called megafunctions, others, andprimitives. Click on the + sign next to primitives to reveal several more sub-menus. Click the + sign next to logic. This will reveal a list of basic logic gates you can select. Scroll down until you see xor. When you click on the xor gate, it a preview of it should appear to the box on the right (refer to figure 6b). Click OK to select this gate. 3) The xor gate should now be under the control of your mouse cursor. Click anywhere on the black space to place it down. You have placed your first logic gate on your design. Remember that the full adder requires 2 xor gates. Repeat the process in step 2) to add another xor gate to your design. You should have something similar to what is shown in figure 7.

Figure 7: BDF file with 2 exclusive or gates

4) The final component needed for our full adder is a 2-to-1 multiplexer. Although we can create this manually, it would be easier to use one already created by quartus. Specifically, we will tell Quartus to give us a multiplexer with parameters specified by us. This called an LPM muduel (Library of Parameterized Modules).

Open the symbol tool box again. This time, click on the folder megafunctions gates lpm_mux to bring up a menu similar to that in figure 8. This is called the megawizard plug-in manager.

Figure 8: Megawizard Plug-In Manager: Select output type

This will simply be a series of menus where we select the parameters we want for our multiplexer. In the first screen (Figure 6), make sure VHDL is selected under Which type of output file do you want to create?. Click Next to get the menu in figure 9.

Figure 9: Megawizard Plug-In Manager: Select input and output parameters

In the menu shown in figure 9, make sure you select 2 data inputs and a 1-bit wide bus. Thats it! Click Finish twice. Your mouse cursor should now have control over the 2-to-1 multiplexer. Place it down anywhere. Refer to figure 10.

Figure 10: Two xor gates and one 2-to-1 multiplexer

5) Although you have the logic gates you need for your adder, you are missing input and output pins. These pins can be reffered to in simulations to find the values of an output given some programmed input. Input/Output pins are found in the symbol toolbox under primitives pin. You will need 3 input and 2 output pins. Place them in your design in a way similar to figure 12 below.

Figure 11: Input/Output Pins

6) Now that our 3 logic gates are placed down, they must be connected together as in figure 4. To do this, place your mouse cursor on the output edge of one gate, and click and hold the left mouse button. Drag the wire to the input edge of another gate, and release when a small box is drawn around your cursor indicating a clean connection. An example connection is shown below in figure 11. Make sure there are no wires hanging around that are connected to nothing. If you mess up, you can click a wire to highlight it, and press DELETE on your keyboard to delete it.

Figure 12: Clean connections

Connect your wires as in figure 12, which is based on figure 4. We are almost done with our fulladder! 7) If you look carefully, the names of the pins are given automatically, such as pin_name, pin_name2, etc. It is very nice of Quartus to name our pins for us. However, this makes analyzing simulations difficult. To change the name of a pin, double-click it and change the name in the box that appears. When you are done, click OK. Our full-adder is complete!!

COMPILING AND SIMULATING YOUR DESIGN COMPILING To compile your design, simply click on processing=>start compilation. If your design has no loose wires or incorrect inputs, all the bars under the status menu on the left side will reach 100%. SIMULATING 1) Now that you have compiled, you are ready to simulate. First, click on file new. In the box that appears, look under verification/debugging files and select vector waveform file. A new screen will appear on top of your design. It will look like the image in figure 13.

Figure 13: Vector Waveform File

2) Looking at the image above, I placed a red box that says right click here. As I am sure you have already guessed, you are going to right click in that area. In the menu that appears, click insert node or bus. You will see the following box in figure 14 appear.

Figure 14: Insert node or bus

3) After clicking insert node or bus, a menu will appear asking which pins to analyze in the simulation. Refering to figure 15a, click List to list the nodes that are available (figure 15b).

Figure 15a (upper-left), Figure15b (upper-right, Figure 15c (bottom)

After listing the available nodes, click the double right arrow >> to move them to the Selected Nodes list. Click OK to go back to the Insert Node or Bus menu. Click OK again. 4) You are now back to the original vector waveform file screen. You will now notice all of your inputs and outputs. To simulate, we need to give all the inputs initial values. Right click on the first input and select Value. From the menu that appears, click on Random Values. On the box that appears, click OK without changing the selected parameter. Next, do the same with the second input, as well as the carry in. This will give all of you different input test values (because they are random). 5) Now, we can simulate. Click on Processing Simulator Tool. This will bring up the menu in figure 16 below called the Simulator Tool.

Figure 16: Simulator Tool

In the simulator tool, click the dropdown menu that says timing next to simulation mode and change it to functional. Then click Generate Functional Simulation Netlist. What we just did is change the simulation mode to be pure logic and have no reports of time delay that each transistor produces. For the purposes of this lab, we will only concentrate on the logic of the circuit. Next, click Start in the lower left corner of the Simulator Tool to start the simulation. Assuming the progress hits 100%, click Report to view the simulation results. You should see a waveform similar to the one shown in figure 17.

Figure 17: Simulated waveform based on full-adder

6) Analyze the simulation waveform. All the inputs should add correctly, giving the correct sum and carry out result. For example, refering to figure 17, at time 27.45ns, we have A=1, B=0, and Cin=0 for our input values. The simulated output values are Cout=0 and Sum=1. In other words, 1+0+0 = 01, which is binary for 1. This is a correct result. Analyze your results to see if your adder works correctly. FULL ADDER IN VHDL VHDL is a hardware description language. This is different than the C++ and Java languages you may have seen. While C++ and Java are used for software development, VHDL is used purely to describe hardware. This greatly simplifies the hardware design process, as you can design a circuit without knowing the exact logic gates inside. A circuit can be design purely based on its behavior. An example code for VHDL is shown below.
LIBRARY IEEE; use IEEE.STD_LOGIC_1164.ALL; entity one_bit_adder is port( I1, I2, Cin Sum, Cout end one_bit_adder; : in STD_LOGIC; : out STD_LOGIC );

architecture arch of one_bit_adder is begin Sum <= (not I1 and not I2 and Cin) or (not I1 and I2 and not Cin) or (I1 and not I2 and not Cin) or (I1 and I2 and Cin); Cout <= (not I1 and I2 and Cin) or (I1 and not I2 and Cin) or (I1 and I2 and not Cin) or (I1 and I2 and Cin); end arch;

The code above describes a one-bit adder functionally similar to the one we created using a block diagram file. However, the hardware used to describe it is based on the image in figure 18.

Figure 18: Schematic of one-bit adder described in the VHDL code one_bit_adder.vhd.

VHDL is seperated into two main parts; They are the entity and the architecture. Looking at the code in the previous page, the following entity is seen.
entity one_bit_adder is port( I1, I2, Cin Sum, Cout end one_bit_adder; : in STD_LOGIC; : out STD_LOGIC );

The entity describes a black box representation of your design. It only describes the inputs and outputs. In the case of the above adder, there are 3 inputs (I1, I2, Cin) and 2 outputs (Sum, Cout). The architecture describes what is inside your black box. It shows how your design works and what it does. In the case of the adder in figure 18, the VHDL code given above gives a dataflow style description of the one-bit adder. This means each gate is described in the architecture, with its corresponding connections. The architecture is shown again below for your convinience.
architecture arch of one_bit_adder is begin Sum <= (not I1 and not I2 and Cin) or (not I1 and I2 and not Cin) or (I1 and not I2 and not Cin) or (I1 and I2 and Cin); Cout <= (not I1 and I2 and Cin) or (I1 and not I2 and Cin) or (I1 and I2 and not Cin) or (I1 and I2 and Cin); end arch;

1) Compare the code above with figure 18 and connect how the code directly reflects the gates in the design. 2) Click New VHDL File to bring up a blank text document in Quartus. Type the one-bit adder given in the beginning of this section. Compile and Simulate. Compare the simulated results with the simulation from the block diagram file. Make sure the file is called one_bit_adder.vhd or you will get an error. The name of the entity must always be the same as the name of the file.

MULTIPLEXER IN VHDL A multiplexer has 2^n inputs with n selectors. For example, a multiplexer with 1 selector will have 2^1=2 inputs. The multiplexer will pass one of the inputs to its output depending on the value of its selector. Below is code for a 4-to-1 multiplexer.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity mux_gate is port ( I0 I1 I2 I3 Sel Output ); end mux_gate; : : : : : : in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; in STD_LOGIC_VECTOR(1 downto 0); out STD_LOGIC

architecture behav of mux_gate is begin with Sel select Output <= I0 when "00", I1 when "01", I2 when "10", I3 when "11"; end behav;

1) Alter the entity in the code above to have a single 4-bit input by using a 4-bit vector (std_logiv_vector). There will still be a single 2-bit selector after; This will not change. Also, the output will still be 1-bit. 2) Alter the architecture in the code above to reflect the fact that there is a single 4-bit input. You must access a single bit from the 4-bit input to pass through to the output (depending on the selector value). For example,
with Sel select Output <= Input(0) when 00