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DIGITAL CIRCUITS AND SYSTEMS LAB PROJECT REPORT MP3 PLAYER

BY: (B-21)
VIPUL RAWAL(Y08UC140) SHUBHAM JAIN(Y08UC118)

STEP 1
Design and implement a circuit on Xilinx Spartan III to produce various sound signals, for example: Siren, Bang etc. Normal Human Being hearing limit : 20 Hz to 20 KHz Various sound signals are nothing but sound frequencies of different time period. Step A : In this step we decided to divide our project part 1 problem statement into 2 parts :1.) Obtaining various frequencies on FPGA. 2.) Getting output of these frequencies on speaker and taking observations.

Obtaining various frequencies on FPGA :1. Building a circuit at gate level which can provide us the various frequencies. 2. 4 MHz is the source of frequency on the FPGA kit is the GLOBAL CLOCK. But the problem is that the available frequency is so much high that it is not even in hearing

range. To make it audible it should be in the range of 20Hz to 20KHz. 3. Designing a frequency divider circuit on FPGA at gate level which can take input as the clock of 4MHz and gives us the frequencies in audible range (20Hz 20KHz). Design-4 bit binary counters and 1 multiplexer unit(4:1 mux). Working of Frequency Dividing Circuit : Counter divides the input frequency (4MHz) and using the multiplexer and some counters, we can have 4 different frequencies which can be used as input in the speaker and using the select lines at a time one of them can be passed on the output. Note : These 4 frequencies can be from any range starting from 4 MHz and ending in some Hertz. Some of them can be in audible range and some of them may not.

Frequency Dividing Circuit

Synthesis Report :
Final Register Report Macro Statistics # Registers # Flip-Flops : 16 : 16

Cell Usage : # BELS : 44 # AND2 :8 # AND3 :6 # AND3B1 :2 # AND4 :4 # GND :1 # MUXF5 :1 # OR2 :2 # VCC :4 # XOR2 : 16 # FlipFlops/Latches : 16 # FDCE : 16 # Clock Buffers :1 # BUFGP :1 # IO Buffers :4 # IBUF :3 # OBUF :1 ================================================================== Device utilization summary: Selected Device : 3s400pq208-5 Number of Slices: 8 out of 3584 Number of Slice Flip Flops: 16 out of 7168 Number of IOs: 5 Number of bonded IOBs: 5 out of 141 Number of GCLKs: 1 out of 8 Timing Summary: --------------Speed Grade: -5 Minimum period: 3.974ns (Maximum Frequency: 251.620MHz) Minimum input arrival time before clock: 2.766ns Maximum output required time after clock: 10.353ns Maximum combinational path delay: 9.785ns

Step B :

Getting output of these frequencies on speaker and taking observations: We control the select lines using the manual switches available on FPGA kit. By changing the input frequencies, we gave various frequencies in audible range as the output on speaker. Observations :1.) Bandwidth of the speaker - 250Hz to 15625Hz. 2.) The pitch of the sound from the speaker increases on increasing the frequency. 3.) Activity : Changing input frequencies Output : Sound produced like siren, bang, buzzer etc.

STEP : 2
MP3 song as the input to FPGA through serial port of your computer. Step A : MP3 song format cannot be given as input directly to FPGA. So we decided to use the concept of PCM (pulse code modulation). Using PCM for input to FPGA Songs in PCM format contains only data bits like .wav format. Thus, we use .wav format song which can be used as input to the FPGA. We converted a MP3 song into WAV format using Xillsoft Convertor Software. Step B : For input serially on the FPGA : Sending .wav format song to FPGA we use following software. Advanced Serial Port Monitor sending and monitoring the data on the serial port. controls the number of bits and other communication protocols. Step C : For taking serial bits as input and playing the input as the song, we design PWM module at gate level.

PWM : It gives the output pulse according to the width of data.


Circuit details Components detail : 8 bit shift register one up-down counter toggle flip-flop 2 counters (for frequency division) 8 bit shift register (as data accumulator) Working of PWM :1. The shift register supply the input data to the counter. 2. Counter start from this value of input and count upto its terminal count. This terminal count produces a TC which changes the output wave-pulse according to the terminal count of the counter. 3. Other 2 counters works to give different clock to the shift register and the up/down counter. 4. Shift register should work at the speed at which we are sending the data via serial. For that we are sending the data at baud rate of 115200 Hz and this is running the shift register at the same rate.

PCM to PWM Convertor

Synthesis Report :Final Register Report Macro Statistics # Registers # Flip-Flops Cell Usage : # BELS # AND2 # AND2B1 : 101 : 24 : 16 : 29 : 29

# AND2B2 :2 # AND3 :5 # AND3B2 :1 # AND3B3 :1 # AND4 :5 # AND4B3 :1 # AND4B4 :1 # AND5 :2 # AND5B4 :1 # GND :1 # OR2 : 17 # VCC :3 # XOR2 : 21 # FlipFlops/Latches : 29 # FDC :1 # FDCE : 28 # Clock Buffers :1 # BUFGP :1 # IO Buffers :4 # IBUF :3 # OBUF :1 ================================================================== Device utilization summary: --------------------------Selected Device : 3s400pq208-5 Number of Slices: 15 out of 3584 Number of Slice Flip Flops: 29 out of 7168 Number of IOs: 5 Number of bonded IOBs: 5 out of 141 Number of GCLKs: 1 out of 8 Timing Summary: --------------Speed Grade: -5 Minimum period: 12.471ns (Maximum Frequency: 80.189MHz) Minimum input arrival time before clock: 3.497ns Maximum output required time after clock: 6.739ns Maximum combinational path delay: 8.276ns

Observations :1. From the speaker , we are getting some random sound (which is coming at a constant frequency). 2. As we are stopping the data input the sound which is coming out of the speaker stops .

3. Error : There is frequency mismatch between the PWM circuit and and the serial port data coming. 4. Now we are trying to matching the frequency and also trying to remove the stop bit which is coming via the serial port. 5. Upto this level we have completed the project and working for remaining part.