United Arab Emirates University Faculty of Engineering Department of Electrical Engineering Second Semester 2008-2009

Computer Architecture and Organization

(ELEC 462)

Xilinx Tutorial (1)

Objectives:The main objective of this tutorial is to understand the basic features of the Xilinx program through simulating a 2-input AND gate, and to practice on simulating more complicated circuits.

Starting the Xilinx program:1) Start the Xilinx program by clicking Start 2) All Programs Xilinx ISE 8.2i Project Navigator

After starting the Xilinx program window click on File New Project This will open the window shown in Fig-1.

Fig-1

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Type Example1 in the area labeled Project Name (make sure that you leave no spaces in the names or paths, and it always starts with a letter). Choose Schematic from the area labeled Top-Level Source Type, as seen in Fig-2, then press the Next button. The Device Properties window will appear to you as seen in Fig-3. Make sure to choose Spartan3 from the area labeled Family, and ISE Simulator (VHDL/Verilog) from the area labeled Simulator. Then press the Next button.

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Fig-2

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The Create New Source window will appear to you as seen in Fig-4. Press the Next button.

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Fig-3

Fig-4

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The Add Existing Sources window will appear to you as seen in Fig-5. Press the Next button.

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The Project Summary window will appear to you as seen in Fig-6. Press the Finish button.

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The Sources and Processors windows will appear to the left of your screen as shown in Fig-7.

Fig-5

Fig-6

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Fig-7 10) Create a new schematic source file as follows Example1 (Right click) New Source

This step will create the Select Source Type window shown in Fig-8. 11) Select Schematic and type Simple_2in_AND_Gate in the area labeled File name, as seen in Fig-9. Make sure to leave no spaces between the words in the File Name area. Press the Next button. The Summary window will appear to you as seen in Fig-10. Press the Finish button. The Xilinx ISE window will appear to you as seen in Fig-11.

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Fig-8

Fig-9

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Fig-10

Fig-11 Eng. Eyad Kamal Shams 8

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Select the Simple_2in_AND_Gate window, as seen in Fig-12.

Fig-12 15) In the Sources window, make sure to choose Logic from the area labeled Categories, and and2 from the area labeled Symbols, as seen in Fig-13. Click on the and2 symbol from the Sources window, point your mouse into the Simple_2in_AND_Gate window, then click on the white area to create the 2 input AND gate shown in Fig-14. Press the Escape key to end inserting another gate. Click on the zoom in button shown in Fig-15. to magnify the shape of the 2 input AND gate, as

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Click on the Add I/O Marker button input AND, as shown in Fig-16.

to add the inputs and outputs of your 2

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Fig-13

Fig-14

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Fig-15

Fig-16

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Change the name of input XLXN_1 to A as follows XLXN_1 (Right click) Rename Port

This step will show you the Rename Net window in Fig-17. Type A instead of XLXN_1 in the area specified for that, as seen in Fig-18.

Fig-17

Fig-18 20) Change the names of input XLXN_2, and output XLXN_3 to B and C respectively, as seen in Fig-19.

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Fig-19 21) 22) Save your work to be able to continue. Click on Simple_2in_AND_Gate (Simple_2in_AND_Gate.sch) in the Sources window as shown in Fig-20.

Fig-20

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Double click on Synthesize XST in the Processors window and make sure that it gives you a green mark indicating that no errors were found as seen in Fig-21.

Fig-21 24) Double click on Implement Design in the Processors window and make sure that it gives you a green mark indicating that no errors were found as seen in Fig-22.

Fig-22 25) Choose Behavioral Simulation instead of Synthesis/Implementation in the area labeled Sources for in the Sources window as shown in Fig-23. Create a new Test Bench Waveform as follows New Source

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Simple_2in_AND_Gate (Simple_2in_AND_Gate.sch) (Right click)

This step will create the Select Source Type window shown before in Fig-8.

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Fig-23

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Select Test Bench Waveform and type AND_Gate in the area labeled File name, as shown in Fig-24. Make sure to leave no spaces between the words in the File Name area, and always start the name with a letter. Press the Next button.

Fig-24 28) The Associate Source window will appear to you as seen in Fig-25. Press the Next button.

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Fig-25 29) The Summary window will appear to you as seen in Fig-26. Press the Finish button.

Fig-26

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Now, the Initial Timing and Clock Wizard Initialize Timing window will appear to you as seen in Fig-27.

Fig-27 30) Choose Combinational (or internal clock) from the area labeled Clock Information, then change the time of simulation from 1000 ns to 1500 ns by typing 1500 in the area labeled Initial Length of Test Bench, as seen in Fig-28. Then press the Finish button. You will now notice that a new window having the inputs and output signals and having the name AND_Gate.tbw is appearing at your monitor, as seen in Fig-29.

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Fig-28 32) Use your mouse to change the input signals to have the shapes shown in Fig-30.

Note: At this stage, you may change the shape of the output signal using your mouse; however, this will not affect the result of the simulation. 33) Save your work, and then make sure that your Hierarchy in the Sources window has the shape shown in Fig-31. Click on AND_Gate (AND_Gate.tbw) in the Sources window, as shown in Fig-32.

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Fig-29

Fig-30

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Fig-31

Fig-32 35) Click on the mark to the left of Xilinx ISE Simulator in the Processors window and make sure that Simulate Behavioral Model is available, as seen in Fig-33. Then double click on Simulate Behavioral Model to run the simulation. A new window having the results of the simulation is now created and shown in the Simulation window. The simulation result should be similar to Fig-34.

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Fig-33

Fig-34

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Practice Problems:
1) Draw a truth table for the circuit shown in Fig-HW1, then create a new project and name it HW1 to simulate the circuit shown in Fig-HW1. Your simulation should last for 800 ns, where each 100 ns represent one of the states of the truth table. Then compare your simulation results with the predicted results found in your earlier truth table. What is the function of this circuit? A B A
C D

B C Fig-HW1

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Draw a truth table for the circuit shown in Fig-HW2, then create a new project and name it HW2 to simulate the circuit shown in Fig-HW2. Your simulation should last for 1600 s, where each 200 s represent one of the states of the truth table. Then compare your simulation results with the predicted results found in your earlier truth table. What is the function of this circuit?

Fig-HW2

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