High Performance Multi-Radio WSN Platform

Likhith S and Rakshith R Electronics and Communication, R.V College of Engineering

Abstract A high performance multi-radio Wireless

Sensor Network (WSN) platform along with its implementation and design is presented in this paper. This platform is implemented using four parallel radio transceivers with 83 selectable frequency channels. This in turn allows us to develop communication protocols with high interference tolerance, low latency and high mesh networking performance due to the presence of large number of selectable frequency channels. As a result, data exchange with neighbors can be done simultaneously. Performance measurement is done using Nios II softcore processors as a case design. Taking this into reference two additional case designs are developed to achieve ultra low latency and higher throughput using four radio transceivers. I. INTRODUCTION

A wireless sensor network (WSN) consists of spatially distributed autonomous sensors to monitor physical or environmental conditions, such as temperature, sound, vibration, pressure, humidity, motion or pollutants and to cooperatively pass their data through the network to a main location. The more modern networks are bi-directional, also enabling control of sensor activity. The development of wireless sensor networks was motivated by military applications such as battlefield surveillance; today such networks are used in many industrial and consumer applications, such as industrial process monitoring and control, machine health monitoring, and so on. The WSN is built of "nodes" from a few to several hundreds or even thousands, where each node is connected to one (or sometimes several) sensors. Each such sensor network node has typically several parts: a radio transceiver with an internal antenna or connection to an external antenna, a microcontroller, an electronic circuit for interfacing with the sensors and an energy source, usually a battery or an embedded form of energy harvesting. A sensor node might vary in size from that of a shoebox down to the size of a grain of dust, although functioning "motes"

of genuine microscopic dimensions have yet to be created. The cost of sensor nodes is similarly variable, ranging from a few to hundreds of dollars, depending on the complexity of the individual sensor nodes. Size and cost constraints on sensor nodes result in corresponding constraints on resources such as energy, memory, computational speed and communications bandwidth. The topology of the WSNs can vary from a simple star network to an advanced multi-hop wireless mesh network. The propagation technique between the hops of the network can be routing or flooding. Multi radios typically function as isolated air interfaces for isolated networks. The advantages of using multi radio platforms are Improve Performance, Improve Reliability, Improve Security, Improve Efficiency. Collaborating radios have a great potential for system wide improvement. To save energy, it is reasonable to reduce the amount of transferred data by data fusion in WSN nodes. In addition, applications like access control require data authentication and encryption, such as Advanced Encryption Standard (AES). Although WSNs are usually considered as very low data rate networks, there might occur areas with high data rate densities. The combination of low power consumption with complex computing and networking set very high challenges for the design of hardware architecture, communication protocols and data processing algorithms. In this paper we present the design and implementation of a new type of re-configurable WSN platform. It can be used as a router, a multi-link node, a gateway, or high- performance backbone network nodes for simpler WSNs. The implemented platform utilizes up to four parallel radio transceivers. The use of multiple radios increases significantly network performance by allowing simultaneous data receptions and transmissions with several neighbors. We also present reference application architectures targeting to ultra low delay and high data rate implementations. II. DESIGN REQUIREMENTS

The platform is used for various WSN applications such as surveillance, area monitoring and environment sensing. The platform is used in large mesh networks which are used to achieve high throughput, low latency high security and interference tolerance. Data protection against routing errors caused by node malfunction, message corruption and possible denial of service attacks are needed for a secured data transfer in large WSN, thereby increasing the reliability. The protection against these threats is achieved by transmitting data frames strongly encrypted using multiple parallel routes. The use of multiple parallel transceivers provides several benefits. WSN nodes may perform simultaneous data exchanges with multiple neighbors, or multiply network performance on critical routing paths. Also, hop delays can be minimized by receiving and transmitting a forwarded data frame simultaneously. For the highest performance in large and dense networks, narrow band transceivers with a large number of selectable frequency channels are crucial. At best, each transceiver utilizes a unique frequency channel. The control of multiple transceivers requires time- accurate parallel data processing capability. The FPGA is used to implement this design as it provides accurate parallel processing, reconfigurability and high performance. HARDWARE IMPLEMENTATION A. System Architecture The hardware architecture of the platform is presented in Fig. 1. All the processing takes place on Altera Cyclone EP1C20 [1] FPGA. The FPGA is large enough for implementing several embedded processor cores, system memory, and custom hardware accelerators. These features are used for implementing versatile multi-processor architectures. Wireless communication use four Nordic Semiconductor nRF2401A [2] radio transceivers. The radios have 1 Mbps data rate and 83 selectable frequency channels in the 2.4000 2.4835 GHz license-free frequency band. Thus, a locally unique frequency channel may be assigned for each radio link. This may be utilized for developing very high performance link layer protocols. Radios are developed on separate radio boards and arranged orthogonally in order to avoid the radio interferences from each other to the maximum possible extent. The measured range of the radio board at the maximum of 0 dBm transmission power and good conditions is over 100 m. With four

simultaneous transmissions and receptions, an applicable radio range reduces to a half of that. A User Interface (UI) consists of two pushbuttons and LEDs, and a 7-segment display. In addition, digital general purpose I/O interfaces are provided for sensors, actuators and other network interfaces that can be freely utilized for custom extensions.

Fig. 1. Platform Hardware Architecture.

The platform can operate as stand-alone node in the WSN, but it can also be connected to a PC computer for debugging and monitoring of internal operation. This is enabled by RS-232 serial port. B. Physical Implementation The multi-radio WSN platform is implemented with three different types of printed circuit boards named as a mother board, a radio board and an I/O board. The mother board consists of FPGA, the user interface and a set of connectors, as presented in Fig. 2 and Fig. 3. Connectors are provided for radio and I/O boards, DC power input, FPGA programming and 16-pin general purpose I/O. The I/O board is presented in Fig. 4. The board enables battery-operation by providing battery holders for four AA-type batteries. In addition, 30 general purpose I/O- pins enable custom extensions. The complete WSN platform is presented in Fig. 5. The platform size is 125 mm x 112 mm x 30 mm. III. DESIGN CASES

The multi-radio WSN platform enables radically new WSN applications that have not been possible in the past. The applicability of the platform is demonstrated by three design cases. In the first design case, a multi-processor architecture composed of multiple Nios II processor is implemented. Then, two reference applications are presented targeting to minimize routing latency, and to maximize routing throughput.

A.

Design Case 1: A Multi-Processor Architecture

A multi-processor architecture composed of multiple Nios II processor subsystems is presented in

Fig. 6. Nios II is a 32-bit RISC softcore processor, which is specifically targeted at Altera FPGAs. There are three core variants differing on the pipelines, caches, and arithmetic logic units. A Nios II processor subsystem includes a Nios II core connected to a timer module, UART module, and local data memory. The system peripherals are connected together by Avalon switch fabric. In Avalon, each connected master-slave pair has dedicated wires with each other, leading to a point-topoint connected network.
Fig. 4. I/O Board.

Fig. 2. Top side of a Motherboard.

Fig. 3. Bottom side of a Motherboard.

The Inter-Processor Communication (IPC) is performed via a shared memory, thus reducing memory requirements as the same program code can be used for all the processors. Due to sharing of memory by all the processors, each processor is given a unique processor ID(PID) in volatile memory space which is fetched by the processor at the system bootup. In this architecture, the PIDs are implemented in logic. Clearly, data memory spaces are local for each processor.

The UART module of each subsystem is connected to UART multiplexer in order to share the single physical RS-232 port on the platform board. This solution is beneficial for debugging and software downloading purposes. Further, the architecture includes four custom logic radio interface modules for accessing radio front-ends on the platform board. When operated in shock burst mode, the payload lengths of individual transfers are limited to 256 bits. This shortcoming could be addressed by using the other mode of operation provided by the radio, called DirectMode. In this mode, the data framing as well as the frame integrity checking of transmitted bit streams are left for users concern. As a consequence, using the DirectMode would increase the flexibility in radio usage, but would also require additional functionality to be implemented by utilizing FPGA resources. The processors connect to the interface modules via a centralized radio access controller, which forwards data and interrupts between radio interfaces and processors By using a centralized accessing mechanism of this kind, the number of parallel lines as well as PIO interfaces required is reduced in comparison to the mechanism in which radio interfaces are directly connected to the processors.

processors gets too low. Hence, architecture instances up to four processors are preferred and the unutilized LEs are allocated for implementing parts of communication protocols.
TABLE I

Fig. 5. Implemented Platform

Currently, the CPUs negotiate the access times to radios using IPC. However, this functionality could be implemented on the radio access controller using mutex-based reservation mechanism. Furthermore, support for direct data forwarding between radio interfaces can be implemented in radio access controller, which would be beneficial in very low latency WSN applications.

TABLE II

Fig. 6. Implemented multi-processor architecture

The architecture described was implemented on the FPGA using Nios II fast cores with 512 bytes of instruction cache. Table I lists the total number of LEs and on-chip memory bits used (excluding memories allocated for program codes), maximum operating frequency (Fmax) and measured current consumption of the FPGA with instances of the architecture comprising 1-4 processors. The LE consumption measurements show that more than four processors could be synthesized on the FPGA. However, adding a new Nios II core to the system requires 2 KB of on-chip memory at minimum (excluding the data memory demand), and as a consequence, the available program memory for the

The current consumption of the FPGA board was measured with different number of processors synthesized on the FPGA. During the measurements, the processors executed a simple ROM-monitor program at 50 MHz. The radio interfaces were present as well, operating at 25 MHz. The radio boards were not connected to the FPGA board during the measurements. The operating voltage fed to the FPGA was 1.5 V. According to the measurements, the current consumed by the FPGA is practically linearly dependent on the number of the processors used. However, the margin in current consumption between the single-processor and dual-processor configurations is distinguishably large. This is due to the fact that single-processor configuration does not include UART multiplexer nor IPC memory used solely for multiprocessing purposes. The memory footprints of the object codes required by the software API functions on a single processor are listed in Table II. According to the results, four Nios II CPUs together with the presented software API functions allocate 22.8 kB of the total 32 kB on-chip memory leaving 9.2 kB for application code. In comparison, with two CPUs the free memory for application code increases to 18.4 kB. This should be sufficient assuming that large parts of communication protocols are implemented in hardware logic. B. Design Case 2: Ultra Low latency WSN Router

The aim of an ultra low latency WSN router realization is to minimize the routing delays over established multi- hop paths. In current WSN implementations, a hop delay may be very significant due to data buffering and channel access delays. The use of multiple hops makes thing worse, since the delay is repeated on each hop. Hence, the realization of multi-hop WSNs with high real-time performance has been very difficult. Implemented WSN router operates in a mesh network, presented in Fig. 7. To achieve highest throughput, a FDMA MAC protocol is used. A dedicated frequency channel for each radio link allows purely simultaneous data exchanges with four neighboring nodes.

Fig. 8. Link layer operation

Data are transmitted in frames consisting of a protocol header and data payload. After a successful reception of data, a recipient responds with an acknowledgement (ACK). Node B can identify a data frame forwarded to Node C within a time duration tdelay, which consists of a radio wave propagation time (tprop), a header reception time (tH), and a short header decoding delay (tdec). Since parallel computing and communication architecture is used, data frame forwarding may begin right after tdelay, as presented in the figure. Thus, the hop delay equals to tdelay and is (1) Assuming averagely 30 m hop distances, radio wave propagation delay is around 100 ns. With 96-bit protocol header and 1 Mbps radio data rate, header reception time is 96 s. Header decoding delay using the FPGA is approximately ten microseconds. Hence, a theoretical hop delay is as low as 106 s. C. Design Case 3: High Data Rate File Transfer

Fig. 7. Analyzed mesh network topology

Nodes may establish multi-hop routing paths over the network, as from a source node to a destination node presented in the Fig. 7. We present a method for delay minimization for established routing paths by the use of multiple radios. An auto-forwarding architecture that is implemented on a link layer identifies the packets that need to be forwarded, and redirects them to an appropriate parallel radio. An overview of the proposed link layer operation is presented in Fig. 8, where Node B forwards data from Node A to Node C by using two parallel radio links (links 1 and 2).

The ultra low latency WSN router design can be extended for higher data rate applications, such as File Transfer Protocol (FTP) by the use of multiple parallel routes. In this distributes data to four neighbors by the use of four parallel transceivers. These neighbors route application example, a source node frames towards a destination node through four different routes, as presented in Fig. 7. The intermediate nodes utilize the same low delay link layer operation as presented in the design case 2. While the source and destination node utilize their all radio capacity, intermediate nodes need only two transceivers for routing. Assuming FDMA-type MAC protocol with unique frequency channels for each radio link, and acknowledged data exchanges, the network throughput (T) can be estimated as

(2) where Lf , LH and LA are the lengths of a data frame, a frame header and an ACK frame, respectively. tsw is the switch time between transmission and reception mode, n is the number of parallel routes, and R is radio data rate. The resulted theoretical throughput over the network as a function of data frame length and with 1 to 4 parallel routes is presented in Fig. 9. In the estimation, frame header and ACK frame lengths are fixed to 96-bit, and radio mode switch time is 200 s. The achieved throughput increases rapidly with 200-bit frame lengths. With 3000 bits frames and four routes around 3.3 Mbps theoretical throughput retransmissions is achieved.

and test new kind of WSN protocols, algorithms and applications.

VI. [1]

REFERENCES

[2]

[3]

[4]

Fig. 9. Network throughput as a function of frame length.

High-Performance Multi-Radio WSN Platform, Mikko Kohvakka, Tero Arpinen, Marko Hnnikinen, and Timo D. Hmlinen, Tampere University of Technology Institute of Digital and Computer Systems. Nordic Semiconductors, ASA home page Datasheet nRF2401A_rev1_1, Mar 2006, v1.1, Available: http://www.nordicsemi.no/files/Product/data_s heet/Product_Specification_nRF2401A_1_1.p df, May 2006. M. Kohvakka, T. Arpinen, M. Hnnikinen, T. D. Hmlinen, High-Performance MultiRadio WSN Platform, in Proc. 2nd Int. Workshop on Multi-hop Ad Hoc Networks: from theory to reality, REALMAN06, May 2006, Florence Collaborating radios have a great potential for systemwide improvement Altera Corp. home page, Section 1, Cyclone FPGA Family Data Sheet, August 2005, v1.3, Available: http://www.altera.com/literature/hb/cyc/cyc_c 5v1_01.pdf, Feb 2006.

As the both application examples require only two radios in the intermediate nodes, the remaining the remaining two radios can be used for another parallel route to improve routing in the meshnetwork, or for the transmission of FEC data to improve tolerance against bit errors. V. CONCLUSIONS

A new unique multi-radio WSN platform has been presented. FPGA-based hardware allows reconfigurability and performance optimization for various applications. High flexibility is achieved by the use of four independent and simultaneously accessible radio transceivers. Simultaneous data exchange with multiple neighbors can be used for minimizing hop delays, and for multiplying network throughput. The selected FPGA chip is powerful allowing the implementation of even four Nios II processor cores operating at 60 MHz clock speed. The platform gives excellent opportunities to design