A Low Voltage CMOS Current Conveyor for Active Filter Design

by Brent Maundy1, Ivars Finvers1, and Peter Aronhime2 1Dept. of Electrical and Computer Engineering University of Calgary, Calgary, AB, Canada T2N 1N4 email: maundy@enel.ucalgary.ca finvers@enel.ucalgary.ca 2Electrical Engineering Dept., University of Louisville, Louisville, KY 40292, USA email: pbaron01@homer.louisville.edu
ABSTRACT A simple CMOS second generation negative current conveyor (CCII-) is presented which is suitable for low supply voltage operation. By restricting the CCII- to applications where the Y input is effectively referenced to signal ground a greatly simplified circuit topology is realized. With only two devices stacked between the supply rails, low voltage operation is achieved. Internal negative feedback is used to reduce the input resistance of the X input. Simulation results demonstrate the use of the CCII- in lowpass and bandpass filter applications. also be avoided in low voltage circuit design. Alternative approaches such as current mode techniques are needed to ensure satisfactory performance of future CC designs. In this paper we report on a low voltage CMOS implementation of a second generation negative current conveyor (CCII-) which is suitable for use in filter designs where the Y terminal is referenced to mid-supply. The latter restriction on the circuit configuration does not unduly restrict the circuits usefulness but allows it considerable simplification of the circuit topology. With only two devices stacked between the supply rails this circuit is capable of operating from a low supply voltage and at high frequencies of operation. In addition the low voltage operation offers the added advantage that it can be easily implemented in most aggressive submicron CMOS IC technologies.

Introduction
From its inception in 1970 by Sedra and Smith [1] and the work of others [2-5], the current conveyor has been shown to be a versatile building block capable of realizing a variety of circuits especially in the active filter design area. Historically, current conveyors have been designed in several forms beginning with simple current mirrors extending to translinear cells, and to complementary input buffer stages with current sensing. Inevitably each implementation suffers from drawbacks in one form or another that are also technology dependent. In general, bipolar implementations tend to suffer from the Y input impedance not being sufficiently high. On the other hand, direct CMOS implementations can suffer from the X-node impedance not being sufficiently low. By far the most effective method of implementation has been the use of use of op-amps with current sensing. The use of an opamp yields high performance at the expense of additional high performance current mirrors for current conveyoring. A variation of the op-amp theme was recently proposed that reduces the input impedance at the X-node through negative feedback [6]. As power supplies are reduced to stay abreast with technology scaling and power hungry digital circuits, the op-amp solution seems less attractive as sophisticated op-amps capable of working at low voltages are needed. The use of cascode mirrors must be

Circuit Description
To understand the circuits operation consider the schematic diagram shown in Fig. 1. It consists of a ring of three (two transistor) inverters with a feedback resistor Rf around one inverter. Diode connected transistors M4 and M5 serve to hold the input X-node at mid-supply. Inverters 2 and 3 serve as gain stages with inverter 3 providing the majority of the gain, and in the process help lower the input resistance seen at the output of inverter 1 by virtue of the large negative feedback. An input current ix injected into inverter 1 output is sampled and copied to transistors M 6, M 7, M 8 and M 9 which mirror and invert the signal current ix. The drains of M10 and M11 form a high output impedance Z-node that provides an output current iz equal in magnitude to the signal current ix. To keep the analysis straightforward we assume that inverters 1 through 3 have the same aspect ratio, but the channel lengths of inverter 3 are greater than those of inverters 1 and 2.

can be found by equating the unity loop gain frequency to the pole frequency of inverter 2 and solving for Rf. Secondly, Rf determines via the loop gain the input DC resistance seen at the X-node. This resistance is given by,

1 rin = rin // rin gm 4 + gm 5

where

(4a)

rin =
Figure 1. Proposed low voltage current conveyor The presence of Rf has a two fold effect. First, it reduces the loop gain in the inverter chain and shifts the parasitic poles of inverters 1 and 2 to a much higher frequency than that created by the parasitic pole of inverter 3. Inverter 3 parasitic pole therefore assumes the dominant pole role occurring at a frequency given by,

(1 g

m1 m 3 d 3

1 r 1 g r Rf gm 2 d 2 + rd 2 + R f R f Rf

(4b) dominates the term in (4a). Note the presence of the second minus sign in (4b) implies that rin can be negative which is indeed the case if Rf < 1/gm2. In Fig. 2 a plot of r vs. Rf for typical values of g = g = 6.8x10-4 1, g
in
m1 m2

1 3 = rd 3 cg1 + cd 3

(1)

where cg1 and cd3 are the parasitic gate to source and drain to source capacitances of inverters 1 and 3 respectively, and rd3 = (rds3a//rds3b) is the combined output resistance of inverter 31. The remaining poles are given by

2 =

(R

// rd 2 Rf

)(

1 cgd 2 + cg 3

(2)

= 2.26x10-4 1 , gm4 + gm5 = 7.143x10-4 1 , m3 rd2 = 78.5 k and rd3 = 4 M confirms (4a). From Fig. 2 it can also be seen that rin can be made very small with a suitable choice of Rf which is a desirable feature for accurate filter design. Unfortunately, the low input impedance is lost at higher frequencies as the loop gain decreases with increasing frequency.

and

+ (1 Av 2 ) rd1 + rd 7 + rd 8 1 = R f cg 2 + cgd 2 (1 Av 2 )

(3)

where Av2 = (1/Rf - gm2)/(Rf //rd2) is the dc gain of inverter 2. A zero is also created due to R f but its presence generally comes into effect only for frequencies greater than 1 and 2. Implicit in (2) are restrictions on the size of R f. If R f is too large, 2 can become less than the unity gain frequency which will force the circuit to oscillate. Too small a value for Rf will reduce the gain of inverter 2 to the point where the second stage gain is lost and the overall loop gain of the circuit becomes positive. The circuit will behave as a latch and both the X and Z nodes will latch to each rail. The low bound on R f can be determined by straightforward analysis to be R f > 1/gm2. An upper bound on the value of Rf to prevent oscillation

Rf in ohms

Figure 2 Plot of rin versus Rf for typical values of gm and rd with Rf swept over a limited range to illustrate the changes in rin . The upper limit for stability of the circuit is Rf < 4 k.

In this section and onwards we use the following notation for inverter i, i = 1, 2, 3; rdi = rds ia//rds ib, gmi = gm ia + gm ib, cgi = cgs ia + cgs ib, cdi = cds ia + cds ib, cgdi = cgd ia + cgd ib

Low-Voltage Operation Considerations

In employing this circuit in an active filter configuration care must be exercised because of its single input that is

Loop Gain Magnitude Response (dB)

referenced to the power supply rails. Indeed because of the manner in which the voltage at the X-terminal is derived it is sensitive to both Vdd and Vss. The sensitivity to Vdd(or Vss) is well known and is given by

60 50 40 30 20 10 0 -10 -20 10 100 1000 104 105 106 Frequency (Hz) 107 108 109

Vx Vdd

= Vdd VTHP

where N and P have their usual meaning, and Vx is the voltage at the X node which should ideally be at midsupply. Having a fixed aspect ratio that sets Vx at midsupply means that Vx will be sensitive to changes in Vx power supply voltages. In addition, SVdd increases as Vdd (or Vss) decreases and therefore the aspect ratio of transistors M4 and M5 should be optimized for the desired range of operation.

Vdd N + (Vss + VTHN ) P

Figure 4 Loop gain response of the three inverter ring As expected the dc open loop gain comes from inverters 1 and 3 and the dominant pole in Fig. 4 agrees with that found using (1). The current transfer ratio was found to be 0.966 which represented a 3.4% error in current conveyoring. The nonzero error can be attributed to the errors in the simple current mirroring scheme used, and possibly cannot be avoided altogether. The input resistance found was 1.7 at DC rising to 1.4 k at 50 MHz. The output resistance of the CCII- was limited to 1.1 M . If the current conveyor is used in a bandpass filter such as the SallenKey single amplifier biquad as shown in Fig. 5, the response obtained is shown in Fig. 6.

Simulation Results
To confirm the circuits operation HSPICE simulations were performed on the expanded circuit of Fig. 3 using Mitel 1.5 m CMOS Level-3 model parameters. Inverters 1, 2 and 3 are represented by transistors M1a/M1b, M2a/M2b, and M3a/M3b respectively. Note the addition of transistors M12 and M13 to compensate for the small fraction of the input current that would otherwise be lost through diode connected transistors M 4 and M 5. Transistors M 12 and M13 also assist in minimizing the offset output current.

Figure 3. Expanded view of the proposed CCIIThe supply voltage was set at 1.5 volts. The value of Rf found to produce a phase margin of 72o at a loop gain of 52 dB was 2.8 k. Note that since a fairly wide range of resistor values will make the circuit stable, resistor Rf can be replaced by an appropriately sized transmission gate comprising of complementary transistors. The loop gain frequency response of the inverter ring in the current conveyor was also examined and is shown in Fig. 4.

Figure 5 A Unity gain Sallen-Key bandpass filter The result is in close agreement with the theoretical result. That is the desired center frequency of 1 MHz with a pole Q = 1 are realized. The slight deviation in the center frequency gain can be accounted for by the non unity current transfer ratio. A 4th-order Chebychev low pass filter was also simulated to evaluate the CCIIperformance in a cascaded mode. The components of the 4th-order Chebychev filter were chosen such that it had a cut off frequency of 100 kHz and a 0.5 dB ripple. The plot of the frequency response of the 4th order filter is shown in Figure 7(a) along with and an expanded view of the passband region as depicted in Figure 7(b).

0 -10 -20
Gain(dB)

1 Ideal
Ideal Response

0 -1

-30 -40 Simulated Response -50

Gain(dB)

-2 -3

HSPICE Simulation

-4
-60 10
5

10

Frequency(Hz)

10

10

Figure 6 Frequency response of the Unity gain Sallen-Key filter

-5 1000

10 4 Frequency(Hz)

10 5

Figure 7(b). Magnitude response of the 4th-order Chebyshev Sallen-Key current-mode filter over the passband. The filters show good agreement with theory and first order deviations can be attributed to non-unity current transfer ratios. The input resistance of the CCII- can be made low which is a desirable feature for accurate filter design.

Ideal 0 -10 HSPICE Simulation -20

Gain (dB)

-30 -40 -50 -60 1000

Acknowledgements
The authors would like to acknowledge the support of the Natural Sciences and Engineering Research Council (NSERC) of Canada and the Canadian Network of Centres of Excellence in Microelectronics (Micronet).
10
4

10 Frequency(Hz)

10

References
[1] Sedra A., and Smith K., A second generation current conveyor and its applications, IEEE Trans., 1970, CT17, pp. 132-134. [2] C. Toumazou, F. J. Lidgey, and D. G. Haigh, "Analogue IC Design: the current-mode approach," Peter Peregrinus Ltd., London, United Kingdom, 1990. [3] M. Taher Abuelma'atti and M. Ali al-Qahtani, "Currentmode universal filters using unity gain cells," IEE Electronic Letters, Vol. 32, No. 12, June 6th, 1996, pp. 1077-1079. [4] S. Celma, J. Sabadell, and Martinez P., "Universal filter using unity-gain cells," IEE Electronic Letters, Vol. 31, No. 11, 1995, pp. 1817-1818. [5] B. Wilson, Recent developments in current conveyors and current mode circuits, IEE Proceedings Vol. 137, Pt. G, No. 2, April 1990, pp. 63-77. [6] H. Elwan and A. Soliman.,A Novel CMOS Current Conveyor Realization with an Electronically Tunable Current Mode Filter for VLSI, IEEE Transactions o n Circuits and Systems II: Analog and Digital Signal Processing, Vol. 43, No. 9., Sept. 1996, pp. 663-670.

Figure 7(a) Magnitude response of the 4th-order Chebyshev Sallen-Key current-mode filter over: (a) the entire frequency range The results show that the filter achieves the desired results reasonably given the simplicity of its structure and the modest Q demands placed on each unity gain Sallen-Key section. The ripple can be seen in the pass band. The deviation observed can be explained by the both the non unity current transfer ratio and the loading effect of the next stage.

Conclusions
A novel approach to realizing a current conveyor has been presented. The technique provides for simple structures that are capable of working at low voltages. A fourthorder low-pass Chebychev filter as well as a second-order bandpass filter was used to illustrated the operation of the CCII-.