USC-ISI

The MOSIS Service

BSIM3v3.1 Model
Parameters Extraction and Optimization
October2000
Henok Abebe
Vance C.Tyree
Table of Contents
1. Introduction and Motivation: -----------------------------------------------1
2. Model Equations: -------------------------------------------------------------3
2.1 Threshold and Subthreshold Regions: --------------------------------3
2.2 The Effective Channel Length and Width: ---------------------------6
2.3 Source/Drain Parasitic Resistance: ------------------------------------7
3. Junction Capacitance Model: -----------------------------------------------8
4. Parameter Extraction and Optimization Strategies: ---------------------9
5. References: -------------------------------------------------------------------16
-1-
1. Introduction and Motivation: -
BSIM3 was developed in an effort to solve the problems of semi-
empirical models and as a complement to BSIM 1-2. It has extensive built-in
dependencies of important dimensional and process parameters such as
channel length, width, gate oxide thickness, junction depth, doping
concentration, and so on.
The model has evolved through three different versions. The first
version forms the original basis for the model but had some severe
mathematical problems. The second version was largely a correction of these
mathematical difficulties, and several new parameters were introduced. The
third version that we are going to discuss here has become an industry
standard for modeling deep-submicron MOS technologies. The model is
suitable for both digital and analog applications because of better modeling of
the output conductance. It also offers binning parameters for improving the
model fits for smaller devices.
-2-
The main motivation to prepare this report is to provide MOSIS
customers with information that help to understand the MOSIS parameter
extraction and optimization procedure. MOSIS SPICE parameters are
obtained from electrical measurements on a selected wafer and using a
commercial extraction and optimization tool (Silvaco UTMOST III).
We measure I-V data on a large array of test transistors included in the
MOSIS process Monitor. Model parameters are extracted using this I-V data
such that the simulated I-V results compare closely with the measured I-V
data. A parameter extraction phase pays close attention to physical
significance of the primary model parameters while the optimization phases
focus on the correction parameters that make the model fit the full range of
device sizes in a particular process. The resulting parameter accuracy is tested
by simulating benchmark test circuits (inverter and ring oscillator) contained
on the MOSIS Process Monitor and comparing simulation results with
measurements.
-3-
One must keep in mind that the BSIM3V3.1 model is only partly
physical. Its physical foundation is more than overpowered by the very large
number non-physical correction parameters that are used to get the model to
work over a large range of channel dimensions in a deep sub-micrometer
process. Each parameter value can vary not only from one fabrication process
to another (even at the same feature size) but also from run to run by reflecting
the actual measured transistor characteristics.
2. Model Equations: -
2.1. Threshold and Subthreshold Regions:
-4-
A) In the strong inversion region, the current along the channel of the
transistor is given by: [1,2]
[ ]
}
) 3 . 1 . 2 ( ] * * 4 ) ( [ 5 . 0
, )
4k
k
- 0.9( Vbs [1,2] limit. upper with bias Substrate is V
bias. substrate volt zero at device channel long a of voltage threshold ideal the is
) (
: to in reduced be can expression above the sizes device large For
(2.1.3) - - - - - - - ) )]( exp( 2 )
2
[exp(
) )]( exp( 2
)
2
[exp( ) )](
*
exp( 2 )
2
*
[exp(
) ( ) 1 1 ( ) | | | | ( k V V
: Voltage Threshold is
(2.1.2) - - - - - - - - -
* 1
1
)
)
2
( 1
2 2
1 ( A ,
(2.1.1) - - - - - - - - -
) 2 / (
2
1
2
2
2
2
1
bseff
0
2 1 0
0 0
1
1 0 1 1 0
0
3 3 1 2 1 th0 th
1
0
2 0
1
bulk
b V DELTA DELTA V V DELTA V V V V
V Where
V
V k V k V V
V Etab Etao
l
L
D
l
L
D
V
l
L
D
l
L
D D V
l
L W
D
l
L W
D D
W W
T
V k k
L
NLX
k V k V
the V
V KETA B W
B
X X L
L
V A
X X L
L A
V
K
Where
V V A V V
V L
W
C Ids
bc bc bs bc bs bc bseff
bc
th
bseff bseff th th
ds
t
eff
sub
t
eff
sub
bi
t
eff
vt
t
eff
vt vt bi
tw
eff eff
w vt
tw
eff eff
w vt w vt
eff
ox
bseff b
eff
bseff bseff
th
bseff eff
dep j eff
eff
gst gs
dep j eff
eff
bseff
ds ds bulk th gs
sat
eff ds
ox eff
+ +

+
+ +
+
+ +

+
+ + + + +
+ +
+
+
+

'

+
+

+

-5-
If we examine equation (2.1.1) for a very small drain/source voltage
)] exp( [ to al proportion be will V , V than less Vgs for
and V - V V value, V large for show that to possible is it equation above the From
voltage, thermal the is
(2.1.5) - - - - - - - - -
)
* 2
2
exp(
2
* 2 1
)]
* 2
exp( 1 ln[ * 2
gst th
th gs gst gs
th gs
b
t t
t
off th gs
ch si
t
th gs
t
gst
V V
q
T K
v v
v n
V V V
N q
Cox n
v n
V V
v n
V

+ +
+

B) The drain current equation in the subthreshold region is given by the

following:
I I
V
v
V V V
n v
ds so
ds
t
gs th eff
t


( exp( )) exp(
*
) 1 - - - - - - - (2.1.6)
field. vertical by the
mobility channel the of reduction the represent that parameters are U and U , U s coefficent The
device). large a of mobility ideal ( mobility field low the represents which parameter the is Here
(2.1.4) - - - - - - - - -
)
2
( )
2
)( * ( 1
by given and mobility the is
region.) linear the in device for MOS current channel of equation classic the is (This

) (
become, to (2.1.1) equation lead That will
. one than less much is )
2
( also
) 2 ( than less much is ) ( that see will we ), 05 . 0 value (V
c b a
0
2
0
eff
2
ds

ox
th gst
b
ox
th gst
bseff c a
eff
ds
th gs
ox eff
ds
bulk
sat eff ds
T
V V
U
T
V V
V U U
Where
V
L
V V W
C Ids
V
A
and V V
+
+
+
+ +

-6-
Where
- - - - - - - (2.1.7)
&
I
W
L
q N
v
n N
C
C
C C V C V D
L
l
D
L
l
C
C
C
l
T X
D V l
T X
D V l
so o
si ch
s
t
factor
d
ox
dsc dscd ds dscb bseff vt
eff
t
vt
eff
t
ox
it
ox
t
si ox dep
ox
vt bs tw
si ox dep
ox
vt w bs t

+ +
+ + +
+
+
+ +

2
1
2
2
1 1
1 1
2 2 0
( )[exp( ) exp( )]
( ), ( )

si ox dep
ox
T X
C) The drain current equation in the saturated region:
I W C V A V v
V V
V
V V
V
V
b b ac
a
a A R C Wv A b V A E L A R C Wv V
c E LV R C Wv V AV A
E
v
ds ox gst bulk dsat sat
ds dsat
A
ds dsat
ASCBE
dsat
bulk ds ox sat bulk gst bulk sat bulk ds ox sat gst
sat gst ds ox sat gst gst
sat
sat

+ + +
+ +

* ( )
( ) , [ ( ) ]
,
(1+ )(1+ ) - - - - - -(2.1.8)
Where


2
2
2
1 2
4
2
1
1
2
1 3
2
2

eff
sat
A
ASCBE
A ASCBE
v
V f
V f
V V
, is the carrier saturated velocity.
= (PCLM, PDIBLC1, PDIBLC2, PDIBLCB, P , DROUT) is called the early voltage.
= (PSCBE1, PSCBE2) is the early voltage due to the substrate current induced body effect.
Detail expression for can be found in [1,2], here it is given as a function of the parameters.
vag
&
2.2. The Effective Channel Length and Width: -
-7-
The effective channel length and width model in BSIM3v3.1 is:
L L XL L
LL
L
LW
W
LWL
L W
LL LLN LW LWL LWN
XL
W W XW W
WL
L
WW
W
WWL
L W
DWG V DWB V
WL WLN WW WWN WWL DWG DWB
XW
eff drawn LLN LWN LLN LWN
eff drawn WLN WWN WLN WWN gst s bseff s
+
+ +
2
2 2 2
2
2 2 2
2
int
int
, , , &
* ( )
, , , , , &
are the length parameter that represent the short channel effect.- - (2.2.1)
is the difference between the drawn channel length on the layout and the printed length on the wafer.
are the width parameters that represent narrow channel effect.
is the difference between the

drawn channel width on the layout and the printed width on the wafer.
Usually it is enough to extract for long channel device.
and are parameters that represent reduction of the channel length and width of the device
due to Source / Drain diffuse.
L W
L L XL L
W W XW W
L W
eff drawn
eff drawn
int int
int
int
int int
&
+
+
2
2
2.3. Source/Drain Parasitic Resistance: -
Model for the parasitic resistance is a simple expression using the channel
current equation in the linear region:
-8-
3. Junction Capacitance Model: -
The Source and Drain capacitance is divided into two components,
namely the area junction capacitance per unit area and the perimeter junction
capacitance per unit length.
. parameters resistance parasitic the are & , , Where
(2.3.1) - - - - - - -
) 10 (
)] ( 1 [
: by given and resistance parasitic the is
) 2 / (
2
1
(2.1.1) equation from calculated resistance channel the is
6
dsw
1
1
r rwb rwg dsw
W
eff
s bseff s rwb gst rwg
ds
ds
ds bulk th gs
sat
eff ds
ox eff
ds
ds
ch
ch
ds ch
ds
tot
ds
ds
W P P R
W
V P V P R
R
R
V A V V
V L
W
C
V
I
R
R
R R
V
R
V
I
r

+ +

1
1
1
1
]
1

1
]
1

-9-
The total junction capacitance is found from:
- - - - - (3.1)
Where A is the total junction area.
P is the total junction perimeter.
The area junction capacitance if
if - - - -(3.2)
The perimeter junction capacitance if

C
C C A C P
C C M
V
P
V
and C C
V
P
V
C C M
V
P
V
and C C
V
P
Jcap
Jcap JA JP
JA J J
bs
b
bs
JA J
bs
b
M
bs
JP Jsw Jsw
bs
bsw
bs
JP JSW
bs
bSW
J
+
+ >
<
+ >

* *
( )
( )
( )
( )
1 0
1 0
1 0
1

<
M
bs
JSW
V if - - - -(3.3) 0
4. Parameter Extraction and Optimization Strategies: -
MOSIS is using the following data measurement procedures for parameter
extraction and optimization on a large array of test transistors included in the
MOSIS Process Monitor.
-10-

I Vs V V V
I Vs V V V
I Vs V V V
I Vs V V V
C Vs V
ds gs ds bs
ds gs ds bs
ds ds bs gs
ds ds bs gs
data @ = Low Voltage with different values.
data @ = High Voltage with different values.
data @ = Low Voltage with different values.
data @ = High Voltage with different values.
data (Junction capacitance Vs Voltage)
Additional electrical measurements on the MOSIS Process Monitor also
determine values of the following parameters:

T
CGDO
CGSO
R
ox
sh
- - - (Gate oxide thickness.)
- - - (Gate to Drain overlap capacitance. )
- - - (Gate to Source overlap capacitance. )
- - - (Sheet Resistance. )
Parameter extraction for each process technology start with an initial set
of parameters that comes from, 1) Vendor supplied models. 2) Previous MOSIS
models. 3) Extracted models from physical fundamentals. Using these setup
parameters with the above four extracted parameters from the MOSIS Process
Monitor the following nine optimization strategies are implemented.[3] (Note:
Interaction between parameters that are optimized in a given strategy is
controlled by the maximum and minimum limit of each parameter. The strategy
presented here is a standard optimization strategy and it may vary from one
technology to the other.)
-11-
Strategy 1: (Parameters in Threshold and Subthreshold Regions)
This local strategy is applied for the wide W and long L device only and
the parameters are those in equation (2.1.3), (2.1.4) & (2.1.7).
Target parameters are V U U U K K N V
th a b c factor off 0 0 1 2
, , , , , , , &
Strategy 2: (Threshold Shift effect parameters)
This local strategy is applied for the narrow W and long L device only
and the parameters are those in equation (2.1.3)& (2.2.1)

Target parameters are
data @ Low voltage with different V values required.
bs
W K DWG DWB WL WLN WW WWN W K
I Vs V V
b
ds gs ds
int
, , , , , , , , &
3 0 3
Strategy 3: (Threshold Shift and Channel Resistance effects
parameters)
It requires data @ = Low Voltage with different values. I Vs V V V
ds gs ds bs
-12-
This local strategy is applied for the wide W and short L device only and
the parameters are those in equation (2.1.3), (2.1.7), (2.2.1)& (2.3.1)

T L LL LLN LW LWN R D D D NLX P P
I Vs V V
dsw vt vt vt rwg rwb
ds gs ds
arget parameters are
data @ Low voltage with different V values required.
bs
int
, , , , , , , , , , &
0 1 2
Strategy 4: (Threshold Shift and Channel Resistance effects
Binning parameters)
A good model result can be obtained for carefully chosen target device
sizes, but the simulation characteristics vary widely from the actual device
characteristics when the channel length and width are varied from large to very
small device size. This problem is handled in approach known as Model
Binning.
BSIM3v3.1 follow the following implementation for all those parameters
listed in [1] that can be binned. As an example for parameter P,
-13-
P P
LP
L
WP
W
PP
L W
P
LP
WP
PP
eff eff eff eff
+ + +
0
0
*
- - - - - - - - - - - -(4.1)
is parameter for the large device size.
is Binning parameter for the length variation.
is Binning parameter for the width variation.
is Binning parameter for the length times width variation.
This local optimization strategy is applied for the small device size
only (short channel and narrow width.)

Target Binning parameters are and
data @ Low voltage with different values required.
PV PR PK
I Vs V V V
th dsw
ds gs ds bs
0 2
,
Strategy 5: (Low Bias Drain Saturated Current parameters.)
This local optimization strategy uses different geometry and the
parameters are those in equation (2.1.2), (2.1.8), & (4.1).

Target parameters are &

data @ Low Voltage with different values required.
For parameters & use wide W & long L device.
For parameter use wide W & short L devices.
For parameters & use narrow W & long L devices.
For the Binning parameter use small size devices.
A v B Pv B A
I Vs V V V
A A
v
B B
Pv
sat sat gs
ds ds bs gs
gs
sat
sat
0 1 0
0
0 1
, , , , ,
-14-
Strategy 6: (Low Bias Output Resistance Parameters)
The output resistance local optimization is the most difficult one and the
user should careful in including or excluding certain device sizes. This strategy
is usually applied for the short channel devices together with the long channel.
If the wide W and long L device become the dominant factor for the
optimization, this device can be excluded. This strategy and strategy #5 should
be executed one after another several times to get a good result. The parameters
that are going to be optimized in this strategy are those in equation (2.1.3),
(2.1.3b) & (2.1.8).

Target parameters are
data @ Low Voltage with different values required.
PCLM PDIBLC PDIBLC P DROUT
DELTA PSCBE PSCBE ETA DSUB
RDS Vs V V V
VAG
ds bs gs
, , , , ,
, , , , & .
1 2
1 2 0
Strategy 7: (High Bias Drain Saturated Current parameters)
This local optimization strategy uses different geometry and the
parameters are those in equation (2.1.2) & (4.1).
-15-

Target parameters are KETA, WKETA, LKETA, and PKETA.

data @ High Voltage with different values required.
For parameter KETA use wide W & long L device only.
For binning parameter WKETA use narrow W & long L devices only.
For binning parameter LKETA use wide W & short L devices only.
For Binning parameter PKETA use small devices only.
I Vs V V V
ds ds bs gs
Strategy 8: (High Bias Output Resistance Parameters)
This local optimization strategy is usually applied for the short
channel devices together with the long channel and the parameters that are
going to be optimized in this strategy are those in equation (2.1.3) & (2.1.8).

Target parameters are ETAB and PDIBLCB.
RDS Vs data @ High voltage with different values required. V V V
ds bs gs
Strategy 9: (Junction Capacitance Parameters)
-16-
This global optimization strategy uses the junction capacitance data
to optimize the parameters listed in equation (3.2) & (3.3). Junction capacitance
verses voltage measurements are taken on two junction capacitors: One with an
area dominated structure and the other with a perimeter-dominated structure.
Target parameters are and C M P C M P
J J b JSW Jsw bSW
, , , , ,
5. References: -
1998. January 1, No 9, VOL III." UTMOST in
s Parameter BSIM3v3.1 ting for Extrac Templates on Optimizati Local " Standard, Simulation Silvaco [3]
1997. Inc. Hall, - Prentice " Spice, with eling Mosfet Mod " Foty, Daniel [2]
1996. " Version), (Final Manual Users' BSIM3v3 "
Burkeley. , California of y Universit Sciences Computer and ng Engineeri l Electrica of ent Departm [1]