Self-Repairing SRAM Using On-Chip Detection and Compensation

Self-Repairing SRAM Using On-Chip Detection and Compensation

Author: Creation Date: Version: V.Revathi 3/05/2012 1.0

CONTENTS
Self-Repairing SRAM Using On-Chip Detection and Compensation...................................................................1

SELF-REPAIRING SRAM USING ON-CHIP ....................................................................................................1 DETECTION AND COMPENSATION.................................................................................................................1

Joint Impact of Inter-Die and Intra-Die Vt Shift on SRAM Stability ..................................6 Relationship between Systematic Inter-Die and Random Within-Die Vt Variation.............................................9 Overall System Characteristics of the Self-Repairing SRAM Array...................................................................11 Design Principles and Analysis of Individual System Components....................................................................14 (I)Design of the Read Stability Detector...............................................................................................................14 (II)Design of Writablility Detector......................................................................................................................16 (III)Read and Write Failure Compensation in Self-Repairing Sram Array (Adaptation Signals):....................18

ABSTRACT

In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die variations on SRAM read and write failures. To improve the robustness of the SRAM cell, we propose a closed-loop compensation scheme using on-chip monitors that directly sense the global read stability and writ-ability of the cell. Simulations based on 45-nm partially depleted silicon-on-insulator technology demonstrate the viability and the effectiveness of the scheme in SRAM yield enhancement. Index TermsDesign, failure, static RAM (SRAM), variation, yield.

INTRODUCTION

Random variations in the device characteristics can result in read and write failures in static-RAM (SRAM) cells, causing substantial yield degradation [9], [10]. Both systematic global variations (that affects all the nMOS and pMOS devices in an SRAM die identically. e.g., channel length variation) and random local variations (which results in mismatches between the devices in a particular cell, e.g., random dopant fluctuations, line edge roughness) contribute to yield degradation [7], [8]. The conflicting requirements for read stability and writ-ability in SRAM cell limit the opportunity of cell transistor sizing and/or static assignment of cell terminal voltages in improving cell robustness. Hence, the majority of prior efforts [1], [2] in improving the cell robustness against local random variation focused on dynamic control of cell terminal voltages depending on read and write operations. The dynamic approaches suffer from the limitations that, they may require two separate supply voltages, additional circuits, and complex timing to switch between two supply voltages depending on the read or the write operation. Finally, none of these methods exploit the dependence of cell failures on the global variability. While random within-die variation has been receiving attention as the major source of failures in the SRAM memory array, the combined effect of the random within-die variations and the systematic inter-die variations on the cell stability and margin has not been extensively studied.

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The effect of global threshold voltage variations on the cell failure characteristics has been first studied and exploited in [3] and [5]. In [3] authors proposed a scheme to sense the global inter-die corner of a chip by monitoring leakage of an entire SRAM array or delay of a long inverter chain. Depending on the global inter-die corner, reverse or forward body bias is applied to reduce the total number of faulty cells in a die. However, this approach suffers from the limitation that, monitoring array leakage or inverter chain delay cannot distinguish between global variation in pMOS and nMOS devices [5]. As explained in Section III, the SRAM dies, which have different global corners of pMOS and nMOS devices are more vulnerable to parametric failures compared to the ones having same global corners for pMOS and nMOS. Further, it relies on the mathematical modeling of the dependence of cell failure on global process variation. Moreover, repairing using body bias is only applicable to bulk-CMOS devices and cannot be applied for partially depleted silicon-on-insulator (PD/SOI) technologies. The effectiveness of body bias also expected to reduce with scaling [13].In this paper, we proposed a scheme for post-silicon adaptive repair of SRAM array considering the strong relationship that exists between systematic inter-die variations and random within-die variations. The novelty of the proposed scheme is to directly sense the global read stability and writability of an SRAM die and apply proper cell correction/compensation mechanism using cell and peripheral supply voltages to mitigate the dominant type of failure. Since the direct sensing of the global read stability and writability helps to successfully distinguish global corners of nMOS and pMOS devices, the proposed scheme becomes more effective in reducing the parametric failures. Once a read or write correc tion is made, we adopt a second level of stability detection to avoid any cell overcorrection.

brief, the salient features of the proposed compensation technique are as folloInws. 1)Direct detection of the global Read and Write corners. 2) Consideration of the pMOS and nMOS s as separate process parameters. 3) Cell corrections can be applied through the proper choice of voltage signalssuitable for PD/SOI as well. 4) No dynamic change in signalssimple design and timing. 5) Iterative closed loop compensation scheme improves the parametric process yield significantly.
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In the context of our proposed self-repair approach, the phrase closed loop basically means that the compensation method is iterative in nature. As read and write failure mechanisms are disjoint, it is imperative to ensure that a read compensation does not actually degrade the cell writ-ability and vice versa. The proposed scheme can effectively be used in the current/future microprocessor products with large on-chip SRAM caches with minimal change in the cell and array for parametric yield enhancement.

REFERENCES BACKGROUND
Joint Impact of Inter-Die and Intra-Die Vt Shift on SRAM Stability The systematic (or global) variation equally modifies the characteristics of all the nMOS and pMOS devices in an SRAM die. However, the global variation in nMOS and pMOS devices can be different from each other. On the other hand, local random variation results in mismatch between neighboring devices in a die. This is illustrated in Fig. 1 for threshold voltage (Vt) variation in a process.

First, the of all nMOS (and pMOS) devices in a die is shifted from its designed value by a certain amount due to global systematic variation. Next, if a single die is considered the different devices in an SRAM cell in that die can vary from its global value due to local random variation.

The local random variation results in mismatch between different devices in the cell and is the primary cause of parametric (read and write) failures in SRAM. The global variation modifies all the nMOS devices in the cell by same amount and all the pMOS devices by same amount.
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However, the global shift in nMOS and pMOS devices can be different. To illustrate the interaction of the global inter-die and local random variations on SRAM stability, we consider SRAM write failure. The write failure occurs if the node storing 1 in an SRAM cell cannot be discharged to 0 during the word line ON time. The write failure becomes more probable if the discharge current through the access transistor in an SRAM cell (Fig. 1) reduces. Consider two SRAM dies from two different global corners and assume that the local variations in both dies are the same. Further, consider die A from a low and die B from a high nMOS global corner. Assume that the time required discharging the node L from logic 1 to logic 0 for two different dies A and B be TA and TB and , respectively. The global variation shifts the nominal value of the right time and due to higher Vt of nMOS, TB>TA. The local variation results in a variation in the right time for different cells in the array. Hence, for the same amount of local variation, SRAM array which has a higher nominal write time is expected to have a larger number of cells with faulty write operation as illustrated in Fig. 2. Thus, the total number of faulty cells in an SRAM array is not only a function of the local within-die variation, but, also a strong function of the global inter-die variations.

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REFERENCES Relationship
Relationship between Systematic Inter-Die and Random Within-Die Vt Variation

In our simulation framework, we first apply a certain amount of global shift to all the six transistors of a given SRAM cell (represents systematic inter-die shift). Then, on top of the global variations, we impose a certain amount of local random Vt shifts to the individual transistors of the cell.

The standard deviation of the local shift Vt for a transistor is given by

where Wi and Li are, respectively, the width and length of the ith transistor of the SRAM cell for i=1,2,,6. In our simulation framework, the threshold voltage for individual nMOS and pMOS devices being influenced by both local and global variations can be expressed as:

In (2a) and (2b), we assume the sign of both and the slower and negative for the faster process corners.

to be positive for

The simulation model, described above, allows us to measure both the read and the write failure probabilities of the cell designed in 45-nm PD/SOI technology (say) for every possible process points over the global threshold voltage plane. In our simulation framework, we have defined the read and the write stabilities as a logarithmic function of the corresponding cell failure probabilities obtained from statistical simulation based on importance sampling [4]. Throughout this paper, the read and write stability (writ-ability) as defined in (3a) and (3b) will be our 9 primary metric for SRAM stability analysis.

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The plot in Fig. 3 directly shows that, the stability of a cell due to local random variation depends on the global process corner. Cell read stability worsens at low-Vt nMOS and high-Vt pMOS corners, whereas writability degrades at low-Vt pMOS and high-Vt nMOS corners. Fig. 3 also illustrates the facts that read and write failures in an SRAM cell are disjoint for most of the global process corners.

Our essential goal in designing the self-repairing SRAM array is to properly exploit this failure amplifying property of the systematic inter-die Vt variations by sensing the global read and write corner the cell is in.

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SYSTEM CHARACTERSTICS
Overall System Characteristics of the Self-Repairing SRAM Array

Fig. 4 illustrates the overall system architecture of the proposed SRAM array with adaptive repair mechanism. It includes the conventional SRAM array with on-chip circuits for failure characterization, a global read stability and writability detector, a very simple digital logic circuit for making decision on whether read or write correction is required, and a circuit for generating the adaptation signals for the required cell corrections.

The read stability and writability detectors detect the global read and write stabilities. They detect whether a read or a write correction is required, and accordingly generate proper digital signals (0 or 1) to actuate the Decision making and Adaptation signal generation block that applies a proper to the word line and cell supply terminal . The proposed adaptive repair algorithm is illustrated in Fig. 5.First, the adaptive repair circuit detects whether an SRAM array requires a read or a write correction. If it does not require any correction (i.e., both the read stability and writability are above some threshold level or correction boundary), it is placed in the bin marked as CORRECT ARRAY. If it does require a read OR write correction, the terminal voltages are properly modified to apply that correction. In the unlikely case the system indicates the requirement for both types of corrections; the decision logic can be configured to give priority to any of the events. After the proper type of correction has been done, the read and write stabilities of the array with modified cell terminal voltages are redetected to avoid any over corrections that might degrade the process yield.

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This second level of stability detection ensures the fact that an array corrected for read stability does not fail in terms of writability and vice versa. If the second level of stability detection shows that both the read stability and writability are above the correction boundaries, the array is placed in the CORRECT ARRAY bin, otherwise it is placed in the bin tagged as Array Suffering from Stability. A regular functional test of the memory array is performed for all the dies in CORRECT and Suffering from Stability bins before shipping. Interestingly, it is possible to apply the proposed scheme by applying full functional test to memory array multiple times. First to detect whether the number of read or write failures, next, to ensure that the adaptive repair scheme did not introduce any new failures and taking appropriate decisions, and finally, before shipping the products. It should be noted that the proposed read stability and writability detection scheme does not replace the regular functional tests; it only helps in correction of parametric read/write failures.

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Design Principles and Analysis of Individual System Components

In this section, we focus on the design issues associated with three major components of the self-repairing SRAM array and evaluate their effectiveness to the overall system yield improvement. As depicted in Fig. 4, the read stability detector, writability detector and the correction scheme using proper word line and cell supply voltages constitute the heart of the system and accordingly, the overall system performance highly depends upon the efficient design of these individual building blocks.

(I) Design of the Read Stability Detector

The major challenges in designing the read stability detector is the identification of a metric that accurately capture the global read corner of the memory array. To capture the cell read stability, we propose a monitor to sense the difference between trip voltage of the half-cell composed of PL, AL, NL and read disturb voltage of the half-cell composed of PR, NR, and AR (Fig. 6).

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To measure the trip voltage, the input and output of the inverter PL-NL are connected, the AL device has gate at Vwl and drain at Vcs, the feedback path connecting nodes L and R is eliminated, and the voltage at node L is measured. To measure the read disturb voltage, gates of PR and NR are connected to Vcs , gate of AR is at Vwl , drain of AR is at Vcs, the feedback connection for nodes R and L is removed, and the voltage at node R is measured. As illustrated in Fig. 7, SRAM cells with higher has larger read stability as defined in (3a)]. If the falls below a certain level ( in Fig. 6) which corresponds to a minimum tolerable value of normalized read stability, then current through the reference pMOS (P1) becomes larger than that through the sensing pMOS (P0), and the output of the current comparator indicates that read correction is required. The SRAM cell used for sensing read/trip voltages needs to be designed with large devices to minimize the effect of local variations on those voltages. This can also be achieved by properly configuring and connecting a large number of actual SRAM cells in parallel.

Fig. 7. Performance of the read stability sensing metric.

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(II) Design of Writablility Detector For writability sensor, the SRAM cell designed with large devices (or by connecting cells in parallel), is used to capture the feedback effect which plays an important role in write operation (Fig. 8). First, when the word line signal is low, node L is pre-charged to 1 and node R is pre-discharged to 0. When the WL signal goes high for write operation, node L discharges to 0 whereas node R is charged to 1. Voltages at both nodes are sampled at the negative edge of the word line signal and compared. If node L voltage is less than node R voltage at that time, the comparator indicates that the write operation is correct. If a correct write operation can be performed at a higher value of Vwrite-ref , it indicates that the writability (write margin) of the cell is high. Hence, for global corners with good writability (i.e., less prone to write failures), the cell will be able to perform a correct write operation even with a high value of Vwrite-ref .

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Fig. 9. Performance of the writability sensing metric.

Note that, since the sensor operates using transient WL signal, it also captures the frequency dependence of write failures. As in case of global read stability detector, in this case the devices in the sensor cell either need to be large or need to be designed by connecting a large number of actual cells in parallel to minimize the impact of local random variability. In order to sense the cell writability, we store a 0 at node R and 1 at node L. This time we have connected to the bit-line R and a variable voltage on the bit-line L. As soon as the word line turns on, node R tries to get charged to 1 and node L tend to discharge to 0. The tendency of node L to discharge to zero is a strong function of the variable voltage Vwrite. Lower the value of Vwrite (it can vary only between 0 and Vdd), worse is the cell writability. The variable voltage Vwrite is defined as weak write test output in Fig. 9. The methodology is explained in detail in [6]. In our proposed on-chip detection scheme, we sense the SRAM cell writability as described as follows. 1) First, we determine the voltage Vwrite required to flip the cell under nominal Vt conditions.
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2) Apply the voltage as predicted above to the port Vwrite,ref in Fig. 8.

3) If the cell flips, we conclude that no write correction is required (i.e., the cell is already in a good write corner), but if it does not, write correction is applied.

(III)

Read and Write Failure Compensation in Self-Repairing Sram Array (Adaptation Signals):

In the proposed self-repairing SRAM array, we chose to use variable cell terminal voltages as adaptation signals, due to significantly less process and design overhead. Application of proper cell terminal voltages suitable for read operation at the worse read corners helps correcting the faulty dies. On the other hand, application of appropriate cell terminal voltages suitable for write operation at the worse write corners help correcting the faulty dies from that corner. Fig. 10 illustrates that lower word line voltage (0.9 V instead of nominal 1.0 V) and nominal cell supply voltage improve read stability at the worst global read corner by 13%. On the other hand, writability gets improved by 37% with a lower cell supply voltage (0.9 V instead of nominal 1.0 V) with nominal word line voltage at the worst global write corner.

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We have already observed that the cell read stability and the writability depend on the global inter-die process corner. Thus, the proposed adaptation signals have been chosen as the low-cell supply voltage for arrays with bad writability and low word line voltage for arrays with bad read stability.

STATISTICAL YIELD ANALYSIS

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The effectiveness of the proposed self-repairing SRAM array design is verified using statistical simulations based on 45-nm PD/SOI SRAM cell. The adaptation technique using the variable terminal voltages is used for the simulation. The simulation framework for yield analysis has been constructed in accordance with the adaptive compensation algorithm illustrated in Fig. 5. In Fig. 11, we have plotted parametric process yield as a function of global nMOS and pMOS variability as defined in(2b)]. It is evident from Fig. 11 that the proposed SRAM array with adaptive repair algorithm has an improved parametric yield compared to the SRAM array with no adaptive repair mechanism. Using the adaptive self-repair scheme, the parametric yield can be improved by up to 12% for a global variability of 60 mV. So far, we have seen that using variable cell terminal voltages (low-word line voltage for read stability improvement and low-cell supply voltage for writability correction) as adaptation signals, we can significantly reduce the number of functional failures within a given SRAM array. But, in an SRAM, the reduction of the functional failures using a lower supply voltage can potentially increase the number of access-delay failures.

Fig. 11. Parametric yield improvement using adaptive self-repair scheme with 3% column redundancies.
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As illustrated in Fig. 12, after read or write corrections using a reduced supply voltage, the SRAM access-delay increases slightly, if the cell is already in the slow nMOS corner. However, statistical analysis for the access-delay failures with and without selfrepair scheme (Fig. 13) reveals that events where a cell is compensated for read or write failure, yet fails due to the access-delay are extremely rare. The proposed self-repair algorithm cannot recover these rare cases, unless, we slightly relax access-delay constraint.

Fig. 12. SRAM access delay distribution over the global process plane.

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Fig. 13. Delay distribution for the compensated and uncompensated cells under variations.

In the proposed self-repairing compensation technique, one of the major design issues is to properly choose a reference for the SRAM read and write stabilities (the design parameters that essentially determine the borderline between a correct cell and a faulty cell). In accordance with (3a) and (3b), we define the overall cell stability as the sum of individual read and write stabilities with the assumption that the probability of joint occurrence of read and write failures in an SRAM cell is negligibly small and can easily be ignored. In our proposed design, read and write reference stabilities explicitly depend on the target process yield specification (or the memory array failure probability) and the redundancies available in the memory array architecture [3], [5]. This can be illustrated by considering an SRAM array having a certain number of rows and columns (512 512 array for our analysis). Given a target array failure probability and percentage column redundancies available in the architecture, we can predict the tolerable overall cell failure probability (Fig. 14) [5]. In Fig. 14, we have plotted the array failure probability as22

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a function of the overall cell stability defined as the sum of SRAM read and write stabilities. As expected, we observe that the overall array failure probability decreases for a fixed cell stability as we increase the column redundancies (CR) from 0.2% to 10%.

Fig. 14. Variation of array failure probability on overall cell stability for different column redundancies for a 512 SRAM array. 512

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Fig. 15. Absolute improvement in process yield (%) for different column redundancies (CR)

Fig. 15 shows the comparison of yield between the array with the proposed selfrepair scheme and the conventional array. It can be seen that the overall yield increases with the proposed scheme regardless of the array column redundancy. It is worthwhile to note that the amount of yield improvement in the proposed array compared to the conventional one is not a monotonic function of the number of redundant columns. Yield improvement decreases as the number of column redundancies increases from 3% to 10% since the number of cells which should be corrected decrease as redundancy increases. On the other hand, yield improvement increases with the increase of column redundancy from 1% to 3%. This is due to the fact that the possibility of cell overcorrection with our proposed self-repair scheme goes higher for a smaller number of redundant columns. In such cases, we eventually end up degrading the cell writability while trying to improve the read stability of the cell and vice versa. As mentioned in Section V, the read and write stability sensors in our proposed self-repairing SRAM array can either be realized using larger lumped devices or by connecting a large number of actual cells in parallel to eliminate the effect of random local variations. However, our study reveals that the latter approach is more accurate in terms of sensing errors and capturing layout effects on global variations. As depicted in Fig. 16, value for an SRAM cell using larger lumped devices is almost 5% higher than that of an actual cell. On the other hand, connecting 2000 actual SRAM cells in parallel gives us the same value as that of a single cell. Similarly, connecting a substantial number of cells in parallel provides more accurate information about cell writability at a particular global corner than using single SRAM cell composed of large devices.

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Fig. 16. Connecting 2000 cells in parallel gives more accurate information about the global read corner than using a single SRAM cell designed with lumped devices. The self-repairing SRAM array, proposed in this paper, suffers slightly from internal sensor output variations. Although, in our design, we have kept the sensor devices reasonably large and hence less prone to process parameter variations, still there exist some internal sensing errors when we shift from one global corner to the other. We have analyzed the sensing error handling capability of the proposed system and the results are shown in Fig. 17. We have plotted absolute process yield improvement as a function of the sensor output variability ( of the Gaussian random distribution). As shown in Fig. 17, the self-repair technique is capable of offering a reasonably good process yield (7%) even with a large parametric variability of the sensing devices ( as close as 50 mV).

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Fig. 17. Variation of SRAM yield improvement profile with sensor output variability using self-repair technique.

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Fig. 18. (a) 95% confidence band at CR>10%,{3.4% 4.8%} (b) 95% confidence band at CR=3% {11.51% 13.11%} (c) 95% confidence band at CR>10% {5.83% 6.81%} Finally, Fig. 18 explicitly emphasizes the fact that the yield estimations have been carried with a reasonably high degree of confidence. For a given memory array, we have considered the absolute yield improvement results for three different column redundancies (viz. 1%, 3%, and more than 10% as depicted in Fig. 14) and a global variability of 100 mV. Fig. 18(a)(c) essentially predicts the error bands required to achieve a confidence level of 95% for three different column redundancies. It is quite apparent from Figs. 15 and 18 that with 95% confidence, the maximum possible error in our absolute yield estimation stays within+_1% .

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REFERENCES ADVANTAGES

SRAM is just one way to construct memory cells. SRAM uses six transistors per bit of storage, and is really fast. The six transistors per bit make large amounts of SRAM storage large and expensive though, so it is only applied in areas where the speed is critical, such as caches or local stores. Most processor caches are built from SRAM.It's entirely normal.

DIS-ADVANTAGES
A SRM is used in cache memory because it is so fast to access and can be accessed in a dual ported manner. The main reason for doing this is that the main non-deterministic process in computation is no longer the 'cost to compute' but the cost to access memory. In the target areas for Cell such latencies are intolerable and generally avoidable; it is easier to re-define what the cache is. When you consider the multi-processor case, this access time is even more likely to vary because it depends on other processors work-loads. For performance (and simplicity), it then makes more sense to just ditch the entire concept of a shared cache and switch to a local SRAM store.

CONCLUSION
In this paper, we investigated the interaction between the inter-die and intra-die variations on SRAM read and write failures and proposed an efficient and reliable self-repairing closed-loop compensation scheme using on-chip monitors that sense the global readability and writability of the cell directly, without sensing the process corner itself.

The proposed MOJUMDER et al.: SELF-REPAIRING SRAM USING ON-CHIP DETECTION AND COMPENSATION 83 self-repairing SRAM arrays with the exclusive facility for fast detection of the global read and write corners and subsequent compensation with minimal design overhead can be effective in achieving high-parametric yield in nanometer technologies.

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