A Linear Programming Based Static Power Optimization Scheme for Digital CMOS Circuits AMSC 662 - Project Proposal

Vishal Khandelwal Department of Electrical and Computer Engineering, University of Maryland, College Park. {vishalk@glue.umd.edu}

Introduction

This project is based on static power optimization of CMOS digital circuits. We will discuss the electrical engineering aspects of the static power optimization problem in the next section and present the mathematical equations that are involved in the formulation of this optimization problem. We briey explain why our approach is dierent from the existent work. The main aspect of this amsc-662 project proposal is to show how an electrical engineering optimization problem is modelled as a linear formulation. The high complexity of the optimization problem is expressed mathematically as a linear formulation and solved using a polynomial time LP-Solver like CPLEX. This is a good application of being able to solve complex mathematical problems eciently by using good scientic optimization paradigms like linear programming. This work is a part of my research in low power optimization.

Background and Related Concepts

In recent years, technology scaling has increased the role of leakage power in the overall power consumption of circuits. Supply voltage reduction is a widely accepted methodology for reducing dynamic power, but it has an adverse eect on circuit performance. To maintain high performance, the threshold voltage Vt must also be scaled down which causes an exponential increase in the sub-threshold leakage currents. This is a more potent problem in deep-sub micron technologies. In applications which involve large standby times, this high sub-threshold leakage can be detrimental to the overall power consumption of the circuit. Multi-threshold CMOS (MTCMOS) [3] has emerged as an eective technique for reducing sub-threshold currents in the standby mode while maintaining circuit performance. MTCMOS technology essentially places a sleep transistor on gates and puts them in sleep mode when the circuit is non-operational. State of the art techniques in leakage optimization using MTCMOS essentially assign a sleep transistor to each gate and size them such that all gates have a xed slowdown. This is followed by a clustering approach that clusters gates with mutually exclusive switching patterns. This reduces the overall area penalty of the MTCMOS transistor. There are several problems in this approach that we address in our work. Firstly, the traditional approach sizes the sleep transistors such that all gates have the same slowdown. It does not investigate the possibility of slowing down non-critical gates more than critical gates for better improvements in leakage. Secondly, it has been shown that clustering MTCMOS gates has adverse eects on signal integrity due to ground bounce issues. In this work we address these issues by developing a ne grained methodology for MTCMOS based leakage optimization. Firstly, we assign sleep transistors selectively to gates such that the overall slack could be eectively utilized. Moreover, we do not perform clustering, hence the signal integrity issues are not critical in our approach. As shown in gure 1(a), low Vt logic modules or gates are connected to the virtual supply rails through high Vt sleep transistors [5] which behave similar to a linear resistor in active mode as shown in gure 1(b). The high threshold sleep transistor is controlled using the Sleep signal and limits the leakage current to a low value in the standby mode. The load dependent delay di of a gate i in the absence of a sleep transistor can be expressed as

di

CL Vdd (Vdd VtL )

(1)

where CL is the load capacitance at the gate output, VtL is the low voltage threshold = 350 mV, Vdd = 1.8 V and is the velocity saturation index ( 1.3 in 0.18-m CMOS technology). In the presence of a sleep transistor, the propagation delay of a gate can be expressed as KCL Vdd di (2) sleep = (Vdd 2Vx VtL ) where Vx is the potential of the virtual rails as shown in gure 1 and K is the proportionality constant. Let us suppose IsleepON is the current owing in the gate during active mode of operation. During this mode, the sleep transistor is in the linear region of operation. Using the basic device equations for a transistor in linear region, the drain to source current in the sleep transistor (which is the same as IsleepON ) is given by IsleepON = n Cox (W/L)sleep ((Vdd VtH )Vx n Cox (W/L)sleep (Vdd VtH )Vx
2 Vx ) 2

(3) (4)

The sub-threshold leakage current Ileak in the sleep mode will be determined by the sleep transistor and is expressed as given by [4]
2 Ileak = n Cox (W/L)sleep e1.8 VT e
Vgs Vth nVT

(1 e

Vds VT

(5)

where n is the N -mobility , Cox is the oxide capacitance, VtH is the high threshold voltage (= 500 mV), VT is the thermal voltage = 26mV and n is the sub-threshold swing parameter. Equation 2 establishes a relation between delay of a gate di sleep and Vx . By replacing Vx in equation 4 in terms of i dsleep (using equation 2), we get a dependence between (W/L)sleep and di sleep (assuming the ON current is constant for each gate). Thus, a range of (W/L)sleep for the sleep transistor would correspond to a range of gate delays. Finally, (W/L)sleep in equation 5 can be replaced in terms of di sleep , hence establishing a relationship between gate delay and gate leakage. The nal relation between leakage and delay can be expressed as
2 Ileak = n Cox e1.8 VT e
Vgs Vth nVT

(1 e

Vds VT

dsleep 1/ IsleepON n Cox (Vdd VtH ) (Vdd VtL )dsleep 1/ (KCL Vdd )1/

(6)

This relationship exists for only those gates that have a sleep transistor assigned to them. Note that the moment a sleep transistor is assigned, some delay penalty is incurred. The range of delay that a gate can have is decided by the range of the acceptable (W/L)sleep . The objective of sleep transistor sizing is to decide the best values of (W/L)sleep for all sleep transistors such that the global delay constraint is satised and the total leakage is minimized.
Vdd Sleep high Vt sleep transistor Vdd Vx Low Vt logic Module Vx Sleep high Vt sleep transistor Gnd (a) R Gnd (b) Low Vt logic Module Vx Vdd R Vdd Vx

Figure 1: Sleep Transistor in MTCMOS Circuits

Problem Proposal

We look at a ne-grained sleep transistor placement and sizing methodology in this work. Our approach controls the placement and sizing of sleep transistors in gate level circuits using a ne grained methodology. Formally we will address the following problems: 1. Given a gate level circuit with sleep transistors at some gates, size the sleep transistors such that the global delay constraint is satised and leakage power is minimized. 2. Given a gate level circuit with a global delay constraint, identify the gates where sleep transistors can be placed and size them such that the delay constraint is satised and the overall leakage power is minimized. 3. Given a gate level circuit with its standard cell placement information and placement of sleep transistors, size the sleep transistors under an area penalty constraint such that the global delay constraint is satised and leakage power is minimized. In this work we intend to propose an optimal polynomial time LINEAR PROGRAMMING formulation for the ne-grained sleep transistor sizing problem. The key idea is to identify gates that are non-critical and increase their delay more than that of the critical gates such that the overall leakage is minimized and the delay constraint is satised. The relationship between di sleep , (W/L)sleep and Ileak is used heavily in this formulation. We also address the sleep transistor placement and sizing problem and prove it to be NP-Complete. A dynamic programming based heuristic is proposed to solve the same. Since the ne-grained scheme has potential for a very high area penalty, we present a standard cell placement driven sizing methodology. We show that the area penalty incurred by our proposed scheme is comparable to the existent body of work [3, 1]. The entire framework will be implemented in C using a VLSI-CAD framework called SIS [2]. We will present detailed experimental results showing how our linear programming formulation is eective in optimizing leakage power. We will also submit a research paper based on this entire project as a part of the nal report.

References
[1] C. Long and L. He. Distributed Sleep Transistor Network for Power Reduction. In Procs of Design Automation Conference, June 2003. [2] E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992. [3] Mohab Anis et al. Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits. In IEEE Transactions on CAD of Integrated Circuits and Systems, October 2003. [4] S. Mukhopadhyay and K. Roy. Modeling and Estimation of Total Leakage Current in Nano-scaled CMOS Devices Considering the Eect of Parameter Variation. In Procs of ISLPED 2003, Aug. 2003. [5] S. Mutoh et al. 1-V Power Supply High Speed Digital Circuit Technology with Multithreshold-Voltage CMOS. In IEEE JSSC, vol. 30, no. 8, August 1995.