BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI, HYDERABAD CAMPUS INSTRUCTION DIVISION, FIRST SEMESTER 2011-12 COURSE HANDOUT

(PART-II)

Date: 02/08/2010 In addition to Part I (General Handout for all the courses appended to the time table), this portion gives further specific details regarding the course. Course No. Course Title Instructor-in-charge Team of Instructors (i) For Lecture (ii) For Tutorial (ii) For Practical Course Description CS C391/EEE C391/ECE C391 Digital Electronics and Computer Organization P.S.SAIKRISHNA PS SaiKrishna, Prof. Moorthy Muthukrishnan Madhuri Bayya,T Haripriya, V.Srihari, Subha Madha, Saikrishna PS M.Subha, P.S.Saikrishna, V.Srihari, Anantha saradhi This course covers the topics on logic circuits and minimization, Combinational and sequential logic circuits, Programmable Logic devices, State table and state diagrams, Digital ICs, Arithmetic operations and algorithms, Introduction to Computer organization, Algorithmic State Machines The objective of the course is to impart knowledge of the basic tools for the design of digital circuits and to provide methods and procedures suitable for a variety of digital design applications. The course also introduces fundamental concepts of computer organization. The course also provides laboratory practice using MSI devices.

Scope and Objective

Text Books. : T1: M.Moris Mano and Michael D. Ciletti Digital Design, PHI, 4th Edition, 2007 T2: G Raghurama, , TSB Sudharshan Introduction to Computer Organization. EDD notes 2007 T3: G Raghurama, S & Others Experiments in Digital Electronics, EDD notes 2007.

Reference Books: R1: Donald D. Givonne ., Digital Principles and Design TMH, 2003 Course Plan. Lect. Learning Objectives No. 1 Introduction to Digital Systems and Characteristics of Digital ICs.

Topics to be covered Digital Systems, Digital ICs

Reference to Text Book 1.1; 1.9; 2.3, 10.1,2

2.

3-5 6

Boolean algebra and logic gates, Codes number systems Simplification of Boolean functions Simulation and synthesis basics Combinational Logic, Arithmetic circuits Sequential Logic Digital Integrated Circuits MSI Components Simulation of Combinational Logic Functions. Memory and PLDs Clocked Sequential Circuits Simulation of Sequential Logic Functions. Registers & Counters Analysis of arithmetic units Modular approach for CPU Design Design of Digital Systems Design of Asynchronous Circuits. Memory Organization

Boolean functions Canonical forms, number systems and codes K-Maps (4,5 variables), QM Method Hardware Description Language Adders, Subtracters Multipliers Flip-Flops & Characteristic tables, Latches. TTL, MOS Logic families and their characteristics Comparators, Decoders, Encoders, MUXs, DEMUXs HDL for Combinational Logic RAM, ROM, PLA, PAL Analysis of clocked sequential circuits, state diagram and reduction HDL for Sequential Logic

1.2-7, 2.4-2.9

3.1 to 3.8 3.11

7-9

4.1 - 4-7

10-11 12-14 15-16 17

5.1 to 5.4 10.3, 10.5, 10.7 to 10.10 4.8 to 4.11 4.12

18-20 21-22

7.2, 7.5 to 7.7 5.5, 5.7

23

5.6

24-25 26-27 28-31 32-34 35-37 38-40

Shift registers, Synchronous & Asynchronous counters Multiplication & Division algorithms RTL, HDL description Algorithmic State Machines Asynchronous Sequential Logic Memory Hierarchy & different types of memories

6.1 to 6.5 T2: Appendix A 8.1,8.2, 8.4 to 8.8 R1. Chapter 8 9.1 9.4 T2: Ch 6

Evaluation Scheme: Component Test 1

Duration Maximum Marks 50 mins 40

Date & Time 05/09 11.00 11.50 AM 3/10 11.00 11.50 AM

Remarks CB

Test 2

50 mins

40

OB

Quiz

50 mins

40

Comprehensive Examination Practicals: Regularity, Lab reports Lab test & Viva

3 Hrs

100 40

7/11 11.00 11.50 AM 07/12 AN To be announced

CB

CB To be announced

40

To be announced

(b) Practicals (From T3.) S.No.

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

Name of experiment
FAMILIARIZATION OF BENCH EQUIPMENTS IMPLEMENTATION OF BOOLEAN FUNCTIONS USING LOGIC GATES OPERATION OF 4-BIT COUNTER ADDERS AND SUBTRACTORS BCD ADDER DECODERS, MULTIPLEXERS AND DEMULTIPLEXERS LATCHES & FLIP-FLOPS COMPARATORS & ARITHMETIC LOGIC UNIT COUNTERS SHIFT REGISTERS SEQUENTIAL CIRCUITS MEMORIES AND FPGAS

Surprise Quiz: The Surprise quizzes will be conducted in the tutorial class. There will be no make-up for the same. Make-up Policy: There will no make-ups unless for genuine reasons. Prior permission is to be taken. Chamber Consultation Hour: To be announced in class Notices: All notices will be displayed on the LTC and EEE/ECE notice boards.

Instructor-in-charge,
CS C391/EEE C391/ECE C391