PLUSE AMPLITUDE MODULATION

AIM:-To study the PAM process and its waveforms. To study the demodulation of PAM. APPARATUS:1. Experimental board on study of PAM. 2. Dual trace CRO. 3. Function Generator(1MHz) CRICUIT DIAGRAM:

PAM MODULATOR

PAM DEMODULATOR

THEORY : Pulse modulation is a system in which information regarding signal is not transmitted continuously but only at certain instants of time, called the sampling that if the sampling rate in any pulse sampling theorem it says that complete information can be collected about a signal if its samples are available at a rate grater than twice the maximum frequency contained in it. The theorem is of great use in TIIME DIVISION MULTIPLEXED (TDM) systems. In TDM, the time gaps between the samples of one signal can be used to transmit the samples of some other signal. Thus more than one signal can be sent simultaneously on a time-shared basis. The above discussion shows that pulse modulation has a special application in the form of TDM systems. In continuous modulation systems such as AM, FM, phase modulation etc. TDM is not possible. The pulse modulation could be of various types depending on what characteristics (amplitude, width or position) of a pulse signal (also known as sampling signal) is varied in accordance with the amplitude of modulating signal. Pulse amplitude modulation (PAM) is the samples form of pulse modulation. In this system the signal is sampled at regular intervals and the height of each sample is made proportional to the amplitude of signal at the sampling instant. Fig (a) shows a sinusoidal modulating signal and corresponding PAM signal. The figures (b) and (c) shows two types of PAM one is double polarity and the other is single polarity. Double polarity PAM is according to the amplitudes of the signal, but if a fixed DC is a added to the signal to make it totally positive or negative then the resulting PAM is single polarity type. The effect in PAM is that of multiplying the sampling pulse train by the modulating signal.

The spectrum of PAM consists of modulating frequency fm and a pair of side frequencies around each harmonic of sampling frequency fs.Flat- topped PAM sampling is where the pulse tops are flat instead of sampling is called following the modulating signal. In this case the base band fm is slight distorted in the spectrum so that recovery of signal through low pass filtering has some distortions. GENERATION OF PAM The generation of PAM is usually quite simple. The signal is fed as one input to an AND gate. Sampling pulses are applied to the other input which opens the gate at regular intervals. The output of the gate consists of pulses whose amplitudes are equal to the signal voltages at sampling time. In this board an emitter follower with two inputs has been used. One input is the sampling clock which switches the emitter follower form active region to cut-off region. Fig.1 shows the circuit diagram of the modulator. It uses a n-p-n transistor. When the clock is negative the transistor is cut-off and the output of the emitter follower is zero. As the clock goes to zero level the transistor acts in normal emitter follower configuration and the output follows the modulating signal applied to the other input. The net result is that we get amplitude-modulated pulses at the clock frequency. DEMODULATION The extraction of signal information is quite similar to what we do in amplitude modulation. It has been explained earlier that natural PAM has single frequency fm and side frequencies around the harmonics of sampling frequency. The demodulation simply consists of envelope detection followed by a low pass filter. The low pass filter pass band is so adjusted that it rejects the side frequencies around harmonics of fs and allows only signal frequencies to pass through. In order to have good filtering second order op-amp filter can be used instead of a simple R-C filter. PROCEDURE: Study the layout of the board taking help of the panel drawing. The miniature switch above EXT terminal is used to select either internal or external modulating signal. In position it provides a sine wave with DC offset at the MODSIGNAL terminals. Amplitude knob controls the amplitude of sine wave while offset knob controls its D.C level. When amplitude knob is at zero then only a DC voltage (change able by offset) appears at MOD SIGNAL terminals. In the other position of miniature switch the internal sine wave is disconnected and the external signal appears at MOD SIGNAL terminals whose DC offset can still be adjusted by OFFSET knob. FREQ knob controls the frequency of internal singe wave modulating signal. The clock is used for sampling and it has a fixed frequency PAM appear at terminal T1 T2 is the input terminal for demodulator modulator has two inputs one for sampling clock and the other for modulating signal which can either internal or external. MODULATION 1. Observe the clock on a CRO and its waveform. Measure its amplitude and frequency fs.. 2. Connect the clock input terminals in the modulator

3. Put the control switch in A.C position and set amplitude knob fully anticlockwise. 4. Connect the modulating signal at the input to modulator 5. Connect one trace of the dual trace CRO at T1 and ground. The height will be adjustable by varying OFFSET. This is a PAM signal when input is DC. Measure the amplitude and frequency of these pulses. The frequency will be equal to fs. 6. Connect second trace of CRO at, MOD SIGNAL terminals and increase the amplitude. Observe the sinusoidal modulating signal on CRO. 7. Obtain a stationary pattern of PAM signal on the trace connected at T1.For this adjustment of amplitude, offset and frequency may be required. Trace this waveform for CRO. 8. Observe the effect of DC offset on PAM waveform. Too less offset tends to cut some portion of modulation cycle. Also observe that increasing the amplitude of modulating signal too much produces over-modulation. DEMODULATION 1. Generate the undistorted PAM waveform at T1 for sine wave modulation input. 2. Connect T1 to T2 . This connects PAM to demodulator input. 3. At this stage one trace of CRO is connected to T1 connect the other trace to DEMOD OUTPUT terminals 4. Observe the detected output and trace its waveform. Measure its frequency. It must be same as that of the modulating signal. 5. Observe the effect of changing the sine wave amplitude, offset and frequency on the detected output. EXPECTED WAVEFORMS

RESULT:

QUESTIONS 1. TDM is possible for sampled signals. What kind of multiplexing can be used in continuous modulation systems? 2. What is the minimum rate at which a speech signal can be sampled for the purpose of PAM? 3. What is cross talk in the context of time division multiplexing? 4. Which is better, natural sampling or flat topped sampling and why? 5. Why a dc offset has been added to the modulating signal in this board? Was it essential? for the working of the modulator? Explain. 6. If the emitter follower in the modulator section saturates for some level of input signal, then what effect it will have on the output? 7. Study about the frequency spectrum of PAM signal and derive mathematical expression for it? 8. Explain the modulation circuit operation? 9. Explain the demodulation circuit operation? 10.Is PAM & Demodulation is sensitive to Noise ?

PULSE WIDTH MODULATION

AIM: To study the Pulse Width Modulation (PWM) and Demodulation process and record the corresponding waveforms APPARATUS: 1. PWM trainer kit 2. C.R.O(20MHz) 3. Function generator(1MHz) CIRCUIT DIAGRAM:

MODULATOR CIRCUIT

DEMODULATION CIRCUIT

THEORY: One of the methods of generating PWM is to apply triggers at the sampling rate to control the starting time of pulses from a monostable multivibrator and then use the modulating signal to control the duration of these pulses. The time IC 555 has been used for monostable configuration. It has a voltage divider network and two comparators. The outputs of the two comparators are used to change the state of a flip-flop. Reference voltage to comparator-1 is 2Vcc/3 and that to comparator-2 is Vcc/3. Whenever the voltage on the threshold input exceeds 2Vcc/3, comparator-1 forces the flipflop to go high. A high output of flip-flop saturates the discharge transistor. These conditions persist until comparator-2 triggers the flip-flop. Even if the voltage at threshold input falls below 2Vcc/3 comparator-1 cannot cause the flip-flop to change state. The voltage at trigger input must fall below Vcc/3 to cause flip-flop output to go low through the action of comparator-2. The final output is through a buffer power amplifier at pin no.3. The power amplifier also acts as an inverter so that the output is high when the flip-flop output is low and vice-versa. The diode and RC combination at clock input acts as differentiator and it converts the clock into proper polarity triggers. The trigger goes to pin no.2 and it controls comparator-2. The modulating signal is applied to control input (pin no.5). This fixes the reference level on this input. Initially let us assume, that flip-flop output is high. This makes discharge transistor ON so that timing capacitor CT discharge through it. This is stable state. The system continues to be in this state till a trigger comes. A trigger at pin-2 triggers the flip-flop to go low. The discharge transistor becomes OFF and CT starts charging towards Vcc

through RT. This charging continues till the voltage level across CT exceeds the reference level (modulating amplitude at pin-5). At this moment comparator-1 triggers the flip-flop to go high. The capacitor CT discharges through discharge transistor and the system goes to stable state to wait for next trigger from clock input. Another constraint is that time gap between triggers should be enough to accommodate the largest deviation in pulse width. The width modulation will be distortion free if the charging of capacitor CT is linear every time. To ensure this, the time constant RTCT should be greater than the time interval between triggers and the modulating signal amplitudes should be small compared to Vcc the voltage which charges the capacitor CT. In the above scheme of generation for PWM the capacitor CT always starts charging from zero and charges till its voltage becomes equal to that of modulating signal at that time. It can easily be seen that if the signal amplitude is negative the capacitor is not to be allowed to charge at all. To avoid this, signal can be given a DC offset so that the signal amplitudes are always positive. The DC so introduced can easily be removed at the demodulation process. Information regarding the signal amplitudes is contained in varying widths of the pulses. At the demodulator the pulse widths have to be converted into corresponding amplitudes. If the transistor switch is OFF, it will allow the capacitor C to charge through resistor R. If the switch is put ON, the capacitor will discharge through the transistor. Now if the OFF time is made to correspond to various pulse widths in PWM then capacitor voltage in each charging will be proportional to the pulse width. This generates saw-tooth waveforms whose envelope is the modulating signal as shown in figure. The modulating signal can be extracted from this saw-tooth waveform by low-pass filtering (LPF). The inverter in this scheme has been added so that OFF time of transistor switch corresponds to the pulse width in PWM signal. PROCEDURE: Modulation: 1. Observe the clock on CRO and measure its frequency Ts. 2. Observe the sine wave modulating signal on CRO and see the DC shift produced in this by varying the OFFSET knob. 3. Apply clock at the clock input terminals. 4. Connect one trace of dual trace CRO to T1. As a result of clock. Certain pulse train will be obtained on CRO. These are un-modulated pulses. 5. Apply modulating signal at Em keeping control switch in DC position. 6. Connect the second trace of CRO to Em for observing the modulating signal which is DC at present.

7. The modulated output shows the proportionality between a modulating voltage and pulse width produced. 8. Put the control switch to sine wave position. 9. Adjust the modulating signal amplitude, frequency and DC offset to get a stationary waveform at the PWM output terminal T1. There will be about 10 pulses in one cycle of modulating signal. 10. Trace the PWM waveform from CRO screen. Demodulation: 1. Connect T1 to T2. This connects PWM signal to demodulator. 2. Connect CRO to T3 and obtain a stable waveform. The waveform obtained will be similar to the modulating signal. 3. Connect the CRO to DEMOD OUTPUT terminals and obtain the demodulated output on the CRO screen. 4. Adjust the DC offset and sine wave amplitude so that the distortion in output is small. 5. Measure the amplitude and frequency of this output sine wave. The frequency should be same as that of the modulating signal.

EXPECTED WAVEFORMS

RESULT:

QUESTIONS 1.An audio signal consists of frequencies in the range of 100Hz to 5.5KHz.What is the minimum frequency at which it should be sampled in order to transmit it through pulse modulation? 2. Draw a TDM signal which is handling three different signals using PWM? 3. What do you infer from the frequency spectrum of a PWM signal? 4. Clock frequency in a PWM system is 2.5kHz and modulating signal frequency is 500Hzhowmany pulses per cycle of signal occur in PWM output? Draw the PWM signal? 5. Why should the curve for pulse width Vs modulating voltage be linear? 6. What is the other name for PWM? 7. What is the disadvantage of PWM? 8. Will PWM work if the synchronization between Tx and Rx fails?

9. Why integrator is required in demodulation of PWM? 10. What kind of conversion is done in PWM generation?

PULSE POSITION MODULATION AIM: To study the Pulse Position Modulation (PPM) and demodulation process and record corresponding waveforms. APPARATUS: 1. PPM trainer kit ( AET -58) 2. C.R.O(20MHz) 3. Digital multimeter CIRCUIT DIAGRAM:

PWM MODULATOR

PWM PPM (MONOSTABLE)

PPM PWM (JK-FLIP-FLOP)

PWM DEMODULATOR THEORY: PWM Modulator A basic method of producing PWM and PPM is shown in figure. PWM modulator consists of non-inverting adder and comparator. In adder circuit ramp (sawtooth) and modulating signal are added together and combined signal is applied to the comparator. One of the comparator is connected to applied to the dc source formed by preset PR1 and other input is connected to the signal from the adder. When there is no modulating signal (AF-i/p) adder output is simply sawtooth wave, so the comparator inputs are sawtooth signal and dc voltage set by preset PR1. The output of the comparator is pulse of certain width, this pulse width is depend on dc voltage set by preset and discharging edge of the sawtooth wave. When modulating signal is applied to the modulator reference level of the sawtooth wave is changing according to the input signal therefore the output pulse width is changing accordingly. PPM Modulator: PPM can be produced by applying PWM signal to the monostable multivibrator. The output of the monostable is a pulse of the selected width using external R and C components. Monostable is designed in such a way that falling edge of the PWM wave triggers the multivibrator and output

remains high for certain time depend on RC time constant. As we know the output of the pulse width modulator is changing according to the input signal amplitude, which in turn triggers the monostable and output position changes PWM Demodulator: One method of demodulating PWM signal shown in figure. Because the length of the pulse in PWM is proportional to the amplitude of the analog input waveform and it is a rectangular pulse, the are under the PWM wave form is also proportional to the amplitude of the input. Thus a simple integrator circuit will provide a waveform that resembles the original analog input. Of course smoothing must be done. Series of integrator will serve this purpose. PPM Demodulation: Demodulation of PPM can also be accomplished using several methods. One of the simplest is to convert the PPM waveform into PWM waveform and then demodulate the PWM using the method just discussed. PROCEDURE: Observe the PWM & PPM with DC input voltages: 1. Study the circuit operation thoroughly. 2. Switch on the trainer and measure the output voltages of the regulated power supply i.e +5V and -5V. 3. Observe the output of the AF generator using CRO, note that the output is 5Vpp @ 400Hz frequency. 4. Observe the output of the control signal generator i.e ramp and reference pulse using CRO. 5. Connect ramp signal to the ramp input of the PWM modulator and dc source output to the AF input. 6. Connect DMM to the dc source output and CH 1 input of the scope to the PWM modulator output. 7. Measure the output pulse width at different input voltages starting from zero and note down the readings. ( By this we can observe the output pulse width is varying in accordance with the input voltage as per theory of PWM, the amplitude and position are fixed only width is varying).

8. Now connect output of the PWM modulator to monostable multivibrator input and CH 2 input of the oscilloscope to the monostable output i.e PPM output ( set scope in dual mode and trigger source in CH 1) 9. Observe PWM and PPM waveforms for different values of input voltage starting from zero (By this we can notice the output of monostabel is PPM i.e the pulse width is fixed and amplitude is constant only position is varying). Observe of PWM and PPM with AC input signal: 10. Now connect AF signal instead of dc voltage to the modulator and observe output waveform (Condition : scope is in dual mode, CH1 is connected to AF signal and CH2 is connected to PWM output, trigger source in CH1, if you are using storage oscilloscope after setting AF input voltage observe output in stop mode). Similarly observe PPM waveform. PWM Demodualtion: 11. Remove connection from monostable input and connect it to PWM demodulator input. 12. Connect CH 1 to input AF signal and CH 2 to demodulator output and observe the output, compare it with original AF signal. PPM Demodulation 13. Connect PPM and Reference pulse signal to respective inputs of PPM PWM converter circuit and output of the same circuit to PWM demodulator. (Scope should be set in dual mode, CH 1 is connected to input AF signal, CH 2 to demodulator output and trigger source to CH 1). Observe the output signal and compare it with input AF signal.

EXPECTED WAVEFORMS:

RESULT:

QUESTIONS: 1. What is the advantage of PPM over PWM? 2. Is the synchronization is must between Tx and Rx 3. Shift in the position of each pulse of PPM depends on what? 4. Can we generate PWM from PPM? 5. Why do we need 555 timer? 6. Does PPM contain derivative of modulating signal compared to PWM? 7. For above scheme, do we have to use LPF and integrator in that order. 8. If we convert PPM to PWM & then detect the message signal, will the o/p has less distortion? 9. Is synchronization critical in PPM? 10. How robust is the PPM to noise?

SAMPLING THEOREM
AIM: To verify sampling theorem. APPARATUS: 1. Sampling theorem verification trainer (AET-47). 2. C.R.O (20MHz) 3. Patch cords. CRICUIT DIAGRAM:

THEORY:
Pulse Modulation is used to Transmit analog information. In this system continuous wave forms are sampled at regular intervals. Information regarding the signal is transmitted only at the sampling times together with synchronizing signals. At the receiving end, the original waveforms may be reconstituted from the information regarding the samples. Sampling Theorem Statement: A band limited signal of finite energy which has no frequency components higher than fm Hz, is completely described by specifying the values of the signal at instants of time separated by fm seconds.

The sampling theorem states that, if the sampling rate in any pulse modulation system exceeds twice the maximum signal frequency, the original signal can be reconstructed in the receiver with minimum distortion. Fs > 2fm is called Nyquist rate. Where fs sampling frequency Fm Modulation signal frequency. If we reduce the sampling frequency fs less than fm, the side bands and the information signal will overlap and we cannot recover the information signal simply by low pass filter. This phenomenon is called fold over distortion or aliasing.There are two methods of sampling. (1) Natural sampling (2) Flat top sampling. Sample & Hold circuit holds the sample value until the next sample is taken. Sample & Hold technique is used to maintain reasonable pulse energy.The duty cycle of a signal is defined as the ratio of Pulse duration to the Pulse repetition period. The duty cycle of 50% is desirous taking the efficiency into account. PROCEDURE:1. Connect trainer to mains and switch on the power. 2. Observe the output of AF generator and pulse generator using CRO and note that AF signal is approximately 3Vp-p of 100HZ frequency and pulse generator output is pulse train of 10VP-P with frequency between 200 HZ and 4KHz. 3. Connect pulse output and AF output to the respective inputs of sampling circuit. 4. Connect one of the input of oscilloscope to the sampling circuit output and another to AF signal. 5. Initially set the amplitude of the AF generator to minimum level and sampling frequency to 200Hz(by adjusting the potentiometer). Observe the output of sampling circuit by varying the amplitude of modulating signal. You can notice the amplitude of sampling pulse is varying in accordance with the amplitude of the modulating signal. 6. Connect sampling circuit output to reconstructing circuit. 7. Observe the output of reconstructing circuit (AF signal) at 200Hz sampling frequency until you get the original signal. Statement: The Nyquist Theorem states that in order to recover the original signal from the samples of the signal, the signal must be sampled at a minimum of twice the maximum frequency of the signal. Note: The sampling output is uni-polar sampled i.e, only positive side

EXPECTED WAVEFORMS: Below Wavforms for fs > 2fm

DEMODULATED OUTPUT

RESULT:

QUESTIONS 1.What are the types of sampling? 2.State sampling theorem? 3.What happens when fs < 2 fm ? 4.How will be the reconstructed signal when fs >= 2fm? 5.Explain the operation of sampling circuit? 6. Explain the operation of re-construction circuit?

TDM PULSE AMPLITUDE MODULATION AND DEMODULATION AIM: Study of TDM Pulse Amplitude Modulation/Demodulation. APPARATUS: 1.Time division multiplexing kit 2.C.R.O (20 MHz) 3.Patch chords. BLOCK DIAGRAM:

THEORY: TIME DIVISION MULTIPLEXING (TDM): Sampled signals (Pulse Trains) for message f1(t) and f2(t) are shown in 2-a, 2-b. The Pulse Train of 2-b is delayed slightly from the Train of 2-a to prevent overlap. Other messages are treated similarly. When such N total Pulse Trains are combined, i.e multiplexed, the waveform of 2-c is obtained the time allocated to one sample of one message is called a Time Slot. The time interval over which all message are sampled at least once is called a frame. The portion of the Time Slot not used by any of the Sample Pulse is called the Guard Time. In a practical system, some Time Slots may be allocated to other function like Signaling, monitoring, synchronization etc., SYNCHRONISATION: To maintain proper positions of Sample Pulses in the multiplexer, it is necessary to synchronize the sampling process. A clock is used for sampling. This serves as a reference for all samples. At the Receiving Station, there is a similar Clock synchronization can be derived from the received waveforms by observing the Pulse Sequence over many pulses and averaging the pulses and averaging the pulses (in a closed loop with the Clock derived on the Voltage Controlled Oscillator). This module basically consists of the following sections: a. The Onboard Function Generator, b. The Transmitter, c. The Receiver with the associated synchronization circuitry.

Onboard Function generator: This basically provides four Amplitude Variable (0-5V PP) synchronized sine waves, each 250Hz, 500Hz, 1KHz, and 2KHz. and an amplitude variable DC level (0-5V) The 6.4 MHz crystal oscillator generates a 6.4 MHz clock. It is divided by 2decade counters and 2 ripple counters to get the 32 KHz 16KHz, 8KHz, 4KHz frequencies. This signal is fed to serial to parallel register which generates the sine wave by serial shift operations. The serial to shift register (IC 74LS164) have resistive ladder network at the output. For 16 shifts of the register, one sine wave is produced. So if a 16KHz clock is fed to the shift register, 1KHz sine wave of 2KHz, 1KHz, 500Hz and 250Hz are generated respectively. The active filter at the output suppresses the ripple and also takes care of the impedance matching. DC level is regulated by the 4.7V zener. Also 32KHz sampling clock is used as a Sampling Clock and 8KHz clock is used for Channel Identification. Transmitter: The transmitter section consists of a four analog input channels with 4 pole integrated circuit analog switch, that provides sampling and Time Division Multiplexing of each channel, using pulse amplitude modulation signals. The 32 KHz sampling clock is fed to the cascade of two counters. The two counters are configured in such a way that the outputs vary from 00 to 11. As the control input of the decoder varies from 00 to 11, the signal C1, C2, C3, C4 selects the channel the channel of the analog switch (CD4016BE) and the information of that channel is transmitted. Thus TDM is achieved effectively. The unity gain amplifiers are provided to give proper impedance matching. Receiver: The receiver section consists of a 4 pole analog switch, that de multiplexes the 4 channels and the reconstruction unit. The receiver timing logic. The de multiplexed based on the control signals C0, C1, C2, C3 assigns the information to the corresponding channels. The success of the demultiplexer operation is fully dependent on how exactly, RXCH0, RXCH1, RXCH2, RXCH3, signals match with the TXCH0, TXCH1, TXCH2, and TXCH3 signals. Thus, to ensure the proper de multiplexing, the two dividers are reset by the RXCH0 signals which corresponds with the TXCH0. The demultiplexed signals are then given to the corresponding reconstruction units. The receiver timing logic is very similar to the transmitter timing logic. The de multiplexer based on the control signals C0, C1, C2, C3 assigns the information to the corresponding channels . The success of the de multiplexer operation is fully dependent corresponding channels. The success of the de multiplexer operation is fully dependent on how exactly, RXCH0, RXCH1, RXCH2, RXCH3 signals match with the TXCH0, TXCH1, TXCH2, TXCH3 signals. Thus to ensure the proper demultiplexing, the two dividers are reset by the RXCH0 signals which corresponds with the TXCH0. The demultiplexed signals are then given to the corresponding reconstruction units. The signal reconstruction unit is a 4th order Active Low Pass filter provided for each receiver channel. They filter out the sampling frequency and their Harmonics from the demultiplexed signal

and recover the base band by an integrate action. The cut-off frequency of the 4th Order Low pass filter is 3.4 KHz. PROCEDURE: 1. Connect power supply in proper polarity to the kit & Switch on. 2. Connect the 250Hz, 500Hz, 1KHz and 2KHz sine wave signal to the multiplexer input channel CH0, CH1, CH2, CH3, by means of the patch-chords provided. 3. Connect the multiplexer output TXD of the transmitter section to the demultiplexer input RXD of the receiver section. 4. Connect the sampling clock TX CLK and Channel Identification Clock TXCHO of the transmitter section to the corresponding Rx Clk and Rx CH0 of the receiver section respectively. 5. Set the amplitude of the input sine wave as desire. 6. Take observation as mentioned below. a. Sampling Clock Tx. CLK and Rx CLK. b. Multiplexed Output TxD. c. Demultiplexer Input RxD d. Reconstructed signal CH0, CH1, CH2, CH3

EXPECTED WAVEFORMS

RESULT:

QUESTIONS 1.Draw the TDM signal with 2 signals being multiplexed over the channel? 2.Define guard time & frame time? 3.Explain block schematic of TDM? 4.How TDM differ from FDM? 5.What type of filter is used at receiver end in TDM system?

6.what are the applications of TDM? 7.If 2 signal band limited to 3 kHz, 5KHz & are to be time division multiplexed. What is the maximum permissible interval between 2 successive samples.? 8.Is the bandwidth requirement for TDM & EDM will be same? 9.Is the circuitry needed in FDM.? 10.Is TDM system is relatively immune to interference with in channels (inter channel cross talk) as compared to FDM? 11.Is the FDM susceptible to harmonic distortion compared to TDM? 12.In what aspects, TDM is superior to FDM?

PULSE CODE MODULATION AND DEMODULATION AIM: To study 2- channel Time Division Multiplexing and sampling of analog signal, and its pulse code modulation in None parity mode in the transmitter section and to study the demultiplexing and the reconstruction of the analog signal in the receiver section. APPARATUS: 1. PCM Modulator trainer- AET-68M 2. PCM Demodulator trainer- AET-68D 3. Storage Oscilloscope/ Dual Trace Oscilloscope (Note: Storage oscilloscope is desired for satisfactory observation of PCM wave forms) 4. Digital multimeter. 5. 2 No.s of co-axial cables (standard accessories with AET-68 trainer) 6. patch chords CIRCUIT DIAGRAM:

THEORY: Pulse modulation: A form of modulation in which a pulse train is used as the carrier. Information is conveyed by modulating some parameter of the pulses with a set of discrete instantaneous samples of the messages signal. The minimum sampling frequency is the minimum frequency at which the modulating waveform can be sampled to provide the set of discrete values without a significant loss of information. PCM: In pulse code modulation (PCM) only certain discrete values are allowed for the modulating signals. The modulating signal sampled, as in other forms of pulse modulation. But any sample

falling within a specified range of values is assigned a discrete value. Each value is assigned a pattern of pulses and the signal transmitted by means of this code. The electronic circuit that produces the coded pulse train from the modulating waveform is termed a coder or encoder. A suitable decoder must be used at the receiver in order to extract the original information from the transmitted pulse train. PROCEDURE: 1. Study the theory of operation thoroughly. 2. Connect the trainer (AET-68M) to the mains and switch on the power supply. 3. Observe the output of the AF generator using CRO it should be a Sine wave of 200Hz frequency with 3Vpp amplitude. 4. Verify the output of the DC source with multimeter / scope, output should vary 0 to +5v. 5. Observe the output of the Clock generator using CRO, they should be 64 KHz and 4KHz frequency of square wave with 5 Vp amplitude. Note: These clock signals are internally connected the circuit so no external connections are required. 6. Connect the trainer (AET-68D) to the mains and switch on the power supply. 7. Observe the output of the clock generator using CRO, it should be 64 KHz square wave with 5 Vp amplitude.

PCM Operation (with DC input) Modulation: 8. Set DC source to some value say 4.4 V with the help of multimeter and connect it to the A/D converter input and observe the output LEDs. 9. Note down the digital code i.e output of the A/D converter and compare with the theoretical value Theoretical value can be obtained by: A/D input voltage ________________ = X(10) = Y(2) 1 LSB value Where 1 LSB value = Vref / 2n Since Vref = 5V and n= 8 1 LSB Value = 0.01953 Example: A/D input voltage = 4.4 V

= 225.28(10) = 1110 0001(2) So digital output is 1110 0001 10. Keep CRO in dual mode. Connect one channel to 4KHz signal ( which is connected to the shift register) and another channel to the PCM out put 11. Observe the PCM output with respect to the 4KHz signal and sketch the waveforms. Compare them with the given waveforms Note: From this wave form you can observe that the LSB bit enters the output first. Demodulation: 12. Connect PCM signal to the demodulators (S-P Shift register) from the PCM modulator (AET68M) with help of coaxial cable (supplied with the trainer) 13. Connect clock signal (64 KHz) from the transmitter (AET-68M) to the receiver (AET-68) using coaxial cable. 14. Connect transmitter clock to the timing circuit 15. Observe and note down the S-P shift register output data and compare it with the transmitted data (i.e output A/D converter at transmitter). You will notice that the output of the S-P shift register is following the A/D converter output in the modulator. Observe D/A converter output (demodulated output) using multimeter /scope and compare it with the original signal and you can observe that there is no loss in information in process of conversion and transmission. 16. Similarly you can try for different values of modulating signal voltage. Sample work sheet: 1. Modulating signal 2. A/D output (theoretical) 3. A/D output (practical) 4. S-P output 5. D/A Converter output (Demodulation output) PCM Operation (with AC input) Modulation: 17. Connect AC signal of 2VPP amplitude to Sample & Hold circuit. 18. Keep the CRO in dual mode. Connect one channel to the AF signal and another channel to the sample & hold output. Observe and sketch the sample & hold output. 19. Connect the sample and hold output to the A/D converter and observe the PCM output using storage oscilloscope/ DTO 20. Observe PCM output by varying AF signal voltage. : 4.4V : 1110 0001(2) : 1110 0001(2) : 1110 0001(2) : 4.4 V

DEMODULATION 21. Connect PCM signal to the demodulator input (AET 68D) (S-P shift register) from the PCM modulator (AET -68M) with the help of coaxial cable (supplied with the trainer) 22. Connect clock signal (64KHz) from the transmitter (AET -68M) to the receiver (AET -68D) using coaxial cable 23. Connect transmitter clock to the timing circuit. 24. Keep CRO in dual mode. Connect CH 1 input to the sample and hold output (AET-68M) and CH 2 input ot the D/A converter output (AET-68D). 25. Observe and sketch the D/A output. 26. Connect D/A output to the LPF input. 27. Observe output of the LPF/Amplifier and compare it with the original modulating signal (AET-68M). 28. From above observation you can verify that there is no loss in information (modulating signal) in conversion and transmission process. 29. Disconnect clock from transmitter (AET-68M) and connect to local oscillator (i.e.clock generator output from AET-68D) with remaining setup as it is. Observe D/A output and compare it with the previous result. This signal is little bit distorted in shape. This is because lack of synchronization between clock at transmitter and clock at receiver. Note: You can take modulating signals from external sources. Maximum amplitude should not exceed 4V incase of DC and 3VPP in case of AC (AF) signals.

EXPECTED WAVEFORMS: For DC

For AC

RESULT:

QUESTIONS: 1. Differentiate PCM over Analog modulation? 2. What is bit synchronization & frame synchronization? 3. Explain block diagram of PCM? 4. What is the different error control coding technique? 5. What is resolution in ADC? 6. For arbitrary fixed reference voltage write the table of 4-bit ADC? 7. The accuracy of any digital reproduction of an analog signal depends on what? 8. If sample requires at least 12 levels of precision (+0 to +5 and 0 to 5). How many be sent for each sample? use one bit form sign. 9. What is the formula for bit rate in PCM? 10. If we want to digitize human voice (4KHz B.W), what is the bit rate assuming 8 bits/sample? 11. What is the sampling rate for PCM if the frequency ranges from 1000Hz to 4000Hz? 12. If the interval between two samples in a digital signal is 125 micro seconds. What is the sampling rate? bits should

DELTA MODULATION AND DEMODULATION

AIM:- Study of Delta Modulation and De modulation APPARATUS: 1. Delta modulation and demodulation (DCL- 007 KIT). 2. 20 MHz CRO. 3. Connecting Wires. BLOCK DIAGRAM:

DELTA - DEMODULATOR

THEORY: DELTA MODULATION Delta modulation is the differential pulse code modulation scheme in which the difference signal is encoded into just a single bit. In digital modulation system, the analog signal is sampled and digitally coded. This code represents the sampled amplitude of the analog signal. The digital signal sent to the receiver through any channel in serial form. At the receiver end digital signal is decoded and filtered to the reconstructed analog signal. The advantage of DM is that the modulator and demodulator circuits are much simpler than those used in traditional PCM. Delta modulation is an encoding process where the logic levels of the transmitted pulses indicate whether the decoded output should rise or fall at each pulse. This is true digital encoding process compared to PAM PWM and PPM . If signal amplitude has increased in DM then modulated output is a logic level 0. Thus the output from the modulator is a series of zeros and ones to indicate rise and fall of the waveform since the previous value. DELTA DEMODULATOR: The Delta De-Modulator receives the data stream from D-flip/flop of Delta Modulator. It latches this data at every rising edge of receiver clock. This data stream is then fed to unipolar to bipolar converter which changes the output from D-flip/flop to either ve voltage or +ve voltage for logic 1 and 0 respectively. PROCEDURE: DELTA MODULATION: 1. Connect the power supply with the proper polarity to the Kit and turn it on. 2. Select 250Hz sine wave input of 0V through pot P8 and fed it to input buffer section. Then give buffer output to Delta modulator input. 3. Then select clock rate of 8KHz by pressing SW1.

4. Then observe the Delta modulated output and compare it with the clock rate selected. These waveforms are as in figure. It is half the frequency of clock rate selected. 5. Observe the integrator output test point. It can be observe that as the clock rate is increased amplitude of triangle waveform decreases. This is called minimum step size. Then increase the amplitude of 250Hz sinewave up to 0.5V Signal approximating 250Hz is available at the integrator output. This output resulting from Delta modulation. 6. Then go on increasing the amplitude of selected signal through the respective pot from 0 to IV. It can be observed that the digital high makes the integrator output to go upward and digital low makes the integrator output to go downwards. Observe that the integrator output follow the input signal. Adjust P12 to get a stable waveform if required. The waveform is as shown in the figure. modulator section. 7. Increase the amplitude of 250Hz sine wave through pot P8 further high and observe that the integrator output cannot follow the input signal. State the reason. 8. Repeat the above mention procedures with different signal sources and selecting the different clock rates and observe the response of Delta Modulator. DELTA DEMODULATION: 1. Connect Delta modulated output to the input of Delta demodulator section. 2. Connect output of Delta demodulator to the input of output buffer section. And give buffer output to the 2nd order low pass filter through 4th order low pass filter. 3. Then observed various tests points in Delta demodulator section and observed the reconstructed signal through 2nd and 4th order low pass filter. Observe the waveforms as shown in figure. Observe the various test-points in the Delta signal is obtained by integrating the digital

EXPECTED WAVEFORMS:

QUESTIONS 1. Justify that at each sample only one bit of data is sent to transmission in DM? 2. Mention the advantages of ADM over DM? 3. Explain ADM? 4. What is compounding?

5. What is micro-law & A-law? 6. What will be the output of DM when the I/P is D.C signal? 7. What is slope overload? How is it overcome? 8. Is the slow varying signal, a problem for DM? 9. What is the solution for the above problem? 10. What does the integrator do in delta modulation? 11. What is the need for pulse generator in DM? 12. What does the integrator do in delta demodulation? 13. What is the need for pulse generator in DM? 14. What is the expression for step error in DM? 15. Is message (t) & approximated signal (t) should be with in a step length difference for proper o/p? 16. What is the i/p to the quantizes in delta deform scheme?

FREQUENCY SHIFTKEYING
AIM: Study the operation of FSK modulation & Demodulation and to plot the Frequency Shift Keying waveforms for binary data at different frequencies.

APPARATUS: 1. Frequency Shift Keying kit AET-48 2. Dual trace C.R.O (20MHz) 3. Digital frequency counter & DMM

CIRCUIT DIAGRAM:

THEORY : Frequency shift keying (FSK) is a modulation / Data transmitting technique in which carrier frequency is shifted between two distinct fixed frequencies to represent logic 1 and logic 0. The low carrier frequency represents a digital 0 (space) and higher carrier frequency is a 1 (mark). FSK system has a wide range of applications in low speed digital data transmission systems. Waveforms are shown in figure . FSK modulating & demodulating circuitry can be developed in number of ways, familiar VCO and PLL circuits are used in this trainer. FSK Modulator: Figure 1 shows the FSK modulator using IC XR 2206, IC XR 2206 is a VCO based monolithic function generator capable of producing Sine, Square, Triangle signals with AM and FM facility. In this trainer XR2206 is used generate FSK signal. Mark (Logic 1) and space (Logic 0) frequencies can be independently adjusted by the choice of timing potentiometers F) & F!. The output is phase continuous during transitions. The keying signal i.e data signal is applied to pin 9. FSK Demodulator: Figure 2 shows FSK Demodulator is a combination of PLL (LM565) and comparator (Opamp). The frequency changing signal at the input to the PLL drives the phase detector to result in rapid change in the error voltage, which is applied to the input of the comparator. At the space frequency, the error voltage out of the phase detector is below the comparison voltage of the comparator. The comparator is a non inverting circuit, so its output level is also low. As the phase detector input frequency shifts low ( to the mark frequency), the error voltage steps to a high level, passing through the comparison level, causing the comparator output voltage between its two output levels in manner that duplicates the data signal input to the XR2206 modulator. The free running frequency of the PLL (no input signal) is set midway between the mark and space frequencies. A space at 2025 HZ and mark at 2225 Hz will have a free running VCO frequency of 21125Hz.

PROCEDURE: 1. Study the theory of operation. 2. Connect the trainer to mains and switch on the power supply. 3. Measure the output voltage of the regulated power supply i.e +12V with the help of digital multimeter. 4. Verify the operation of the logic source using digital multimeter. Output should be zero volts in logic 0 position and 12V in logic 1 position. 5. Observe the output of the data signal using oscilloscope. It should be a square wave of 20Hz to 180Hz @ 10Vpp. ( For frequency variation potentiometer is provided. FSK Modulation: 6. Connect output of the logic source to data input of the FSK modulator. 7. Set logic source switch in 0 position. 8. Connect FSK modulator output to oscilloscope as well as frequency counter. 9. Set the output frequency of the FSK modulator as per your desire( say 2.4KHz) with the help of control F0 which represents logic 0 10. Set logic source switch in 1 position. 11. Set the output frequency of the FSK modulator as per your desire ( say 2.4 KHz) with the help of control F1 which represents logic 1. Note: we have chosen F0 as 1.2 KHz and F1 as 2.4KHz for ease of operation in fact you may set any value. 12. Now connect data input of the FSK modulator to the output of the data signal generator. 13. Keep CRO in dual mode connect CH1 input of the oscilloscope to the input of the FSK modulator and CH2 input to the output of the FSK modulator. 14. Observe the FSK signal for different data signal frequencies and plot them. By this we can observe that the carrier frequency shifting between two predetermined frequencies as per the data signal i.e 1.2 KHz when data signal is 0 and 2.4KHz when data input is 1 in this case. 15. Compare these plotted wave forms with the theoretically drawn in figure. FSK Demodulation: 16. Again connect input of the FSK modulator to the logic source and put data source switch in 0 position. 17. Connect the frequency counter to the output of the FSK modulator output. 18. Set FSK output frequency to 2025 Hz with the help of F0 control. 19. Now put data source switch in 1 position and set the FSK out put frequency to 2225 Hz with the help of F1 control without disturbing the F0. Note: As per one of the standards, for proper demodulation of FSK signal the F0 should be 2025 Hz and F1 should be 2225Hz.

20. Disconnect the FSK input of the modulator from logic source and connect data signal generator. 21. Observe the output of the modulator using CRO and compare them with given waveforms in figure. 22. Now connect the FSK modulator output to the FSK input of the demodulator. 23. Connect CH1 input of the Oscilloscope to the data signal at modulator and CH2 input to the output of the FSK demodulator (keep CRO in dual mode) 24. Observe and plot the output of the FSK demodulator for different frequencies of data signal. Compare the original data signal and demodulated signal, by this we can observe that there is no loss in process of FSK modulation and demodulation. EXPECTED WAVEFORMS:

RESULT:

QUESTIONS 1. Explain the concept of FSK? 2. Compare ASK, FSK & PSK? 3. Draw the waveforms of FSK? 4. What is M-ray signaling? What are its advantages over 2-ary signaling?

5. What are the different data coding formats & draw the waveforms what is advantages of Manchaster coding over other formats? 6. Explain the demodulation scheme of FSK? 7. What is the formula for Band Width required in FSK? 8.What is the minimum B.W for an FSK signal transmitting at 2000bps(haif duplex),if carriers are separated by 3KHz? 9.Is the FSK spectrum, a combination of two ASK spectra centered around two frequencies? 10.Is the FSK band width is more than ASK band width for a given band rate? 11.Is it more susceptible to noise than ASK? 12.What are the limiting factors of FSK? 13.Is the band rate & bit rate are same for FSK?

PHASE SHIFT KEYING

AIM: Study the operation of PSK (Binary) Modulation & Demodulation and to plot the PSK wave forms for Binary data at different frequencies. APPARATUS: 1. Phase Shift Keying trainer-- AET-71 2. Dual trace Oscilloscope 3. Digital multimeter 4. Patch chords BLOCK DIAGRAM:

THEORY : Phase Shifting Keying (PSK) is a modulating / Data transmitting technique in which phase of the carrier signal is shifted between two distinct levels. In a simple PSK (i.e Binary PSK) unshifted carrier Vcos Wo t is transmitted to indicate a 1 condition , and the carrier shifted by 180 o i.e -V cos Wo t is transmitted to indicate a 0 condition. Wave forms are shown in Figure PSK Modulating & Demodulating circuitry can be developed in number of ways one of the simple circuit is used in this trainer.

PROCEDURE: 1. Study the theory of operation. 2. Connect the trainer to mains and switch on the power supply. 3. Measure the output of the regulated power supply i.e +5V and -5V with the help of digital multimeter. 4. Observe the output of the carrier generator using CRO, it should be an 8 KHz Sine with 5 Vpp amplitude. 5. Observe the various data signals (1 KHz, 2 KHz and 4 KHz) using CRO. Modulation 6. Connect carrier signal to carrier input of the PSK Modulator. 7. Connect data signal say 4 KHz from data source to data input of the modulator. 8. Keep CRO in dual mode. 9. Connect CH1 input of the CRO to data signal and CH2 to the output of the PSK modulator 10. Observe the PSK o/p Signal with respect to data signal and plot the wave forms Compare the plotted waveforms with given wave forms. Demodulation: 11. Connect the PSK output to the PSK input of the demodulator. 12. Connect carrier to the carrier input of the PSK demodulator Note: In actual communication system reference carrier is generated at receiver. 13. Keep CRO in dual mode. 14. Connect CH1 to the data signal (at Modulator) and CH2 to the output of the demodulator. 15. Compare the demodulated signal with original data signal, By this we can notice that there is no loss in modulation and demodulation process. 16. Repeat the steps 7 to 15 with different data signals i.e 2 KHz and 1 KHz.

EXPECTEDWAVEFORMS:

RESULT:

QUESTIONS 1. Explain the concept of PSK? 2. Compare ASK, FSK, PSK? 3. Draw the waveforms of PSK? 4. What is M-ary signaling? What are its advantages over 2-ary signaling? 5. Explain the demodulation scheme of PSK?. 6. What is the advantage of PSK over ASK, FSK? 7. Will the smaller variations in the signal can be detected reliably by PSK? 8. Can we transmit data twice as for using 4-PSK as we can using 2-PSK? 9. What is the minimum B.W required in PSK? 10. Is the B.W in PSK is same as in ASK? 11. Is the maximum bit rate in PSK is greater than ASK? 12. Is the maximum baud ate in PSK & ASK are same?

DIFFERENTIAL PHASE SHIFT KEYING

AIM: Study the characteristics of differential phase shift keying. APPARATUS: 1. Differential Phase Shift Keying Kit 1 2. C.R.O (20MHz) 3. Digital multimeter. 4. Nos of coaxial cables (standard accessories with AET-72 trainer) BLOCK DIAGRAM:

fig (1.1)

fig(1.2) THEORY: DPSK: Phase Shift Keying requires a local oscillator at the receiver which is accurately synchronized in phase with the un-modulated transmitted carrier, and in practice this can be difficult to achieve. Differential Phase Shift Keying (DPSK) over comes the difficult by combining two basic operations at the transmitter (1) differential encoding of the input binary wave and (2) phase shift keying hence the name differential phase shift keying. In other words DPSK is a noncoherent version of the PSK. The differential encoding operation performed by the modulator is explained below Let b (t) be the binary message to be transmitted . An encoded message stream b(t) is generated from b(t) by using a logic circuit The first bit in b(t) is arbitary which may be chosen as 1 or 0 . The subsequent bits in b(t) are determined on the basis of the rule that when b(t) is 1 b(t)does not change its value fig 1.4 shows two possible bit streams b(t) and the respective phases. In the first bit stream, the initial bit (arbitary) is 1 and in the second bit stream, the intial bit is 0 EX-NOR gate can be used to perform this operation as its output is a 1 when both the input are same, and a 0 when the inputs are different.

Figure 1.4: b(t) b(t) Phase 1 00 0 0 1800 1 0 1800 1 0 1800 0 1 00 0 0 1800

B(t)

Phase

1800

00

00

00

1800

00

Figure 1.5 Example for Complete DPSK operation (with arbitary bit as 0):

Message signal(to be transmitted) 0

Encoded data(differential data)

0 1800 1800

1 00 00

1 00 00

1 00 00

0 1800 1800

1 00 00

Trasnmitted signal phase:

Received signal phase :

Encoded data(differential data)

Message signal (Demodulation)

DPSK Demodulator: Fig 1.1 showa the DPSK modulator . This consists of PSK modulator and differntial encoder. PSK Modulator :IC CD 4052 is a 4 channel analog multiplexer and is used as an active component in this circuit. One of the control signals of 4052 is grounded so that 4052 will act as a two channel multiplexer and other control is being connected to the binary signal i.e, encoded data . Un shifted carrier signal is connected directly to CH1 and carrier shifted by 1800is connected to CH2. Phase shift network is a unity gain inverting amplifier using OpAmp (TL084). When control signal is at high voltage, output of the 4052 is connected to CH1 and un shifted (or 0 phase) carrier is passed on to output. Similarly when control signal is at zero voltage output of 4052 is connected to CH2 and carrier shifted by 1800 is passed on to output. Differential encoder: This consists of 1 bit delay circuit and an X-NOR Gate. 1 bit delay circuit is formed by a D-Latch. Data signal i.e, signal to be transmitted is connected to one of the input of the X-NOR gate and other one being connected to out of the delay circuit. Output of the X-NOR gate and is connected to control input of the multiplexer (IC 4052) and as well as to input of the D-Latch. Output of the X-NOR gate is 1 when both the inputs are same and it is 0 when both the inputs are different. DPSK Demodulator: Fign 1.2 shows the DPSK Demodulator. This consists of 1 bit delay circuit, X-NOR Gate and a signal shaping circuit. Signal shaping circuit consists of a Op-amp based zero crossing detector followed by a D-latch. Receiver DPSK signal is converted to square wave

with the help of zero crossing and this square wave will pass through the D-Latch. So output of the D-latch is an encoded data. This encoded data is applied to 1 bit delay circuit as well as to one of the inputs of X-NOR gate. And output of the delay circuit is connected to another input of the X-NOR gate. Output of the X-NOR gate is 1 when both the inputs are same and it is 0 when both the inputs are different. PROCEDURE: Modulation: 1. Connect carrier signal to carrier input of the PSK Modulator. 2. Connect data signal from data input of the X-NOR gate. 3. Keep CRO in dual mode. 4. Connect CH1 input of the CRO to data signal and CH2 input to the encoded data (which is nothing but the output of the X-NOR gate) 5. Observe the encoded data with respect to data input. The encoded data will be in a given sequence.

Actual data signal

10101101001010110100 01100011011001110010

Encoded data signal :

6. Now connect CH2 input of the CRO to the DPSK output and CH1 input to the encoded data. Observe the input and output waveforms and plot the same. 7. Compare the plotted waveforms with the given waveforms in fig: 1.3 Note: Observe and plot the waveforms after perfect triggering. Better to keep the encoded data more than 4 cycles for perfect triggering. Demodulation: 1. Connect DPSK signal to the input of the signal shaping circuit from DPSK transmitter ( i.e., AET 72M) with the help of coaxial cable (supplied with trainer). 2. Connect clock from the transmitter ( i.e. AET 72M) to clock input of the 1 bit delay circuit using coaxial cable. 3. Keep CRO in dual mode. Connect CH1 input to the encoded data (at modulator ) and CH2 input to the encoded data ( at demodulator). 4. Observe and plot both the waveforms and compare it with the given waveforms. You will notice that both the signals are same with one bit delay. 5. Keep CRO in dual mode. Connect CH1 input to the data signal (at modulator) and CH2 input to the output of the demodulator. 6. Observe and plot both the waveforms and compare it with the given waveforms. You will notice that both the signals are same with one bit delay.

7. Disconnect clock from transmitter (AET 72M) and connect to local oscillator clock (i.e., clock generator output from AET 72D) with remaining setup as it is. Observe demodulator output and compare it with the previous output. This signal is little bit distorted. This is because lack of synchronization between clock at modulator and clock at demodulator. You can get further perfection in output waveform by

adjusting the locally generated clock frequency by varying potentiometer. EXPECTEDWAVEFORMS

RESULT:

QUESTIONS 1. How does DPSK differ from PSK? 2. Explain theoretical modulation & demodulation of DPSK using arbitrary bit sequence and assuming initial bit 0 and 1? 3. What is the advantage of DPSK over PSK? 4. Why do we need 1 bit delay in DPSK modulator & demodulator? 5. What does a synchronous detector (multiplier) do in DPSK demodulator? 6. What is the relation between carrier frequency & the bit interval T? 7. What are the disadvantages of DPSK? 8. Is the error rate of DPSK is greater than PSK? 9. What is the expression for DPSK error? 10. What are the applications of DPSK?

AMPLITUDE SHIFT KEYING

AIM: 1. To study the operation of ASK modulator and demodulator 2. Observation and plotting of ASK signal for different frequencies of data (Modulating) signal 3. Demodulation of ASK signal and compare the demodulated signal with the original data signal APPRATUS: 1. Amplitude Shift Keying trainer AET-119 2. Dual trace Oscilloscope. 3. Patch Chords. CIRCUIT DIAGRAM:

THEORY: In a digital system of communications the modulating wave form will be of the form of a square wave, or a train of impulses ASK is a form of amplitude modulation where the carrier is modulated by the train of impulses. This modulation can be between two levels of amplitude or more usually, interchanging the carrier on and off. This is known like ASK on-off, or key on-off (OOK). Below figure shows the modulating signal (data), carrier signal and ASK signal of ASK system. Experimental procedure: 1. Go through the theory of operation thoroughly 2. Switch on the trainer and measure the regulated power supply output i.e +5V and -5V with respect to the ground.

3. Observe and note down the frequency and amplitude of the carrier generator with the help of oscilloscope. Note: Frequency will be 10 KHz and the amplitude will be 4.5Vpp. 4. Observe and measure the output of date signal with the help of the oscilloscope this will be a square wave of 5VPP with frequency varying between 20 Hz and 200 Hz. Note: Some times starting frequency may be below 20 Hz and the maximum frequency may exceed 200 Hz depends on the tolerance of the circuit components 5. Connect carrier input of the ASK modulator to the carrier signal and data input of the ASK modulator to the logic switch output 6. Observe and draw the output of the ASK modulator when data is 1 and 0. Compare the output with waveform shown in figure Modulation: 8. Now disconnect data input of the ASK modulator from the logic switch output and connect it to modulating (data) signal. 9. Set modulating signal frequency at 100 Hz. 10 Observe the modulating signal and ASK signal simultaneously and plot both the signals Demodulation: 11. Connect ASK signal to the input of the ASK demodulator. 12. Observe the demodulated signal (out of the ASK demodulator) and compare with the original signal (i.e modulating signal). With this, we can conclude

that the original data signal (modulating Signal) has been recovered with out loosing any information (voltage, frequency and the Phase). 13. Repeat steps 9 to 12 for different frequencies of data signal.

EXPECTED WAVEFORMS:

RESULT:

QUESTIONS 1. If the bit rate of an ASK signal is 1200bps, what is the baud rate? 2. Is ASK highly susceptible? 3. What are the characteristics of transmission medium which effect speed of transmission in ASK? 4. Find the minimum band width for an ASK signal transmitting at 2000bps.The transmission made is half duplex?

5. If B.W is 5000Hz for an ASK signal, what are the baud rate? 6. What is the advantage of ON-OFF keying in ASK? 7. Given the bandwidth of 10KHz ( 1Hz to 1KHz), Find the band width for upper side & lower side band of carrier in full duplex ASK? 8. For the above problem, what are the carrier frequencies in upper & lower side bands?

DIFFERENTIAL PULSE CODE MODULATION AND DEMODULATION AIM: To Study & understand the operation of the DPCM APPARATUS: 7. DPCM Modulator trainerAET-69M 8. DPCM Demodulator trainerAET-69D 9. Storage Oscilloscope 10. Digital Multimeter. 11. 2 Nos of co- axial cables (standard accessories with AET-69 trainer) 12. Patch chords BLOCK DIAGRAM:

THEORY: Differential PCM is quite similar to ordinary PCM. However, each word in this system indicates the difference in amplitude, positive or negative, between this sample and the previous sample. Thus the relative value of each sample is indicated rather than, the absolute value as in normal PCM. This unique system consists of I. DPCM Modulator (AET -69M) 1. Regulated power supply 2. Audio Frequency signal generator 3. Prediction Filter 4. Sample & Hold circuit 5. A/D Converter 6. Parallel Serial Shift register 7. Clock generator / Timing circuit 8. DC source II. DPCM Demodulator (AET-69D): 1. Regulated Power Supply 2. Serial-Parallel Shift register.

3. D/A converter. 4. Clock generator 5. Timing circuit 6. Prediction filter 7. Passive low pass filter PROCEDURE: 6. Study the theory of operation thoroughly. 7. Connect the trainer (AET-69M) to the mains and switch on the power supply. 8. Observe the output of the AF generator using CRO, it should be Sine wave of 400 Hz frequency with 3V pp amplitude. 9. Verify the output of the DC source with multimeter/scope; output should vary 0 to +290mV. 10. Observe the output of the Clock generator using CRO, they should be 64 KHz and 8 KHz frequency of square with 5 Vp-p amplitude. 11. Connect the trainer (AET-69D) to the mains and switch on the power supply. 12. Observe the output of the Clock generator using CRO, it should be 64KHz square wave with amplitude of 5 pp.

DPCM Operation (with DC input):

Modulation: 13. Keep CRO in dual mode. Connect one channel to 8 KHz signal (one which is connected to the Shift register) and another channel to the DPCM output. 14. Observe the DPCM output with respect to the 8 KHz signal and sketch the waveforms. Note: Form this waveform you can observe that the LSB bit enters the output first.

Demodulation 15. Connect DPCM signal to the demodulator (S-P register) from the DPCM modulator (AET 69M) with the help of coaxial cable (supplied with the trainer). 16. Connect clock signal (64 KHz) from the transmitter (AET-69M) to the receiver (AET -69D) using coaxial cable. 17. Connect transmitter clock to the timing circuit. 18. Observe and note down the S-P shift register output data and compare it with the transmitted data (i.e output A/D converter at transmitter) notice that the output of the S-P shift register is following the A/D converter output in the modulator. 19. Observe D/A converter output (demodulated output) using multimeter/scope and compare it with the original signal and can observe that there is no loss in information in process of conversion and transmission.

DPCM Operation (with AC input):

Modulation: 20. Connect AC signal of 3VPP amplitude to positive terminal of the summer circuit. Note: The output of the prediction filter is connected to the negative terminal of the summer circuit and can observe the waveforms at the test points provided on the board. 21. The output of the summer is internally connected to the sample and hold circuit 22. Keep CRO in dual mode. Connect one channel to the AF signal and another channel to the Sample and Hold output. Observe and sketch the sample & hold output 23. Connect the Sample and Hold output to the A/D converter and observe the DPCM output using oscilloscope. 24. Observe DPCM output by varying AF signal voltage.

Demodulation: 25. Connect DPCM signal to the demodulator input (AET -69D) (S-P shift register) from the DPCM modulator (AET -60M) with the help of coaxial cable (supplied with trainer). 26. Connect clock signal (64KHz) from the transmitter (AET -69M) to the receiver (AET-69D) using coaxial cable. 27. Connect transmitter clock to the timing circuit. 28. Keep CRO in dual mode. Connect one channel to the sample & hold output (AET-69D) and another channel to the D/A converter output (AET-69D). 29. Observe and sketch the D/A output 30. Connect D/A output to the LPF input and observe the output of the LPF. 31. Observe the wave form at the output of the summer circuit. 32. Disconnect clock from transmitter (AET -69M) and connect to the local oscillator(i.e., clock generator output from AET-69D) with remaining setup as it is. Observe D/A output and compare it with the previous result. This signal is little bit distorted in shape. This is because lack of synchronization between clock at transmitter and clock at receiver.

EXPECTED WAVEFORMS: For DC

For AC

RESULT:

QUESTIONS: