Lecture25 MOSTransQuantitativeId VD VG

ECE 3040 - Dr.
Alan Doolittle Georgia Tech

Lecture 25
MOSFET Basics (Understanding with Math)
Reading: Pierret 17.1-17.2 and Jaeger 4.1-4.10 and
Notes
ECE 3040 - Dr. Alan Doolittle Georgia Tech
MOS Transistor I-V Derivation
With our expression relating the Gate voltage to the surface potential and
the fact that |
S
=2|
F
we can determine the value of the threshold voltage
( )
( )
area unit per e capacitanc oxide the is
where,
devices) channel - p (for 2
2
2
devices) channel - n (for 2
2
2
ox
ox
ox
F
S
D
ox
S
F T
F
S
A
ox
S
F T
x
C
qN
C
V
qN
C
V
c
|
c
c
|
|
c
c
|
=
=
+ =
Where we have made use of the use of the expression,
o S S
K c c =
Coordinate Definitions for our NMOS Transistor
x=depth into the semiconductor
from the oxide interface.
y=length along the channel from
the source contact
z=width of the channel
x
c
(y) = channel depth (varies
along the length of the channel).
n(x,y)= electron concentration
at point (x,y)
n
(x,y)=the mobility of the
carriers at point (x,y)
Device width is Z
Channel Length is L
Assume a Long Channel device (for
now do not worry about the channel
length modulation effect)
Concept of Effective mobility
The mobility of carriers near the interface is
significantly lower than carriers in the
semiconductor bulk due to interface
scattering.
Since the electron concentration also varies
with position, the average mobility of
electrons in the channel, known as the
effective mobility, can be calculated by a
weighted average,
| |
}
}
}
}
=
=
=
=
=
=
=
=
=
=
=
) (
0
2
) (
0
) (
0
) (
0
) , ( ) , (
) (
/ arg ) , ( ) (
,
) , (
) , ( ) , (
y x x
x
n
N
n
y x x
x
N
y x x
x
y x x
x
n
n
c
c
c
c
dx y x n y x
y Q
q
cm e ch dx y x n q y Q
defining or
dx y x n
dx y x n y x

Empirically
( )
constants are ,
1
u
u

and where
V V
o
T GS
o
n
+
=
Drain Current-Voltage Relationship
In the Linear Region, V
GS
>V
T
and 0<V
DS
<V
dsat
dy
d
n q nE q J J
n qD nE q J
n y n Ny N
N n N
|

~ ~ ~
V + =
Neglecting the diffusion current, and recognizing the current is
only in the y-direction,
Drain Current-Voltage Relationship
In the Linear Region, V
GS
>V
T
and 0<V
DS
<V
dsat
}
}
} }
}
} } }
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
|
.
|
\
|
|
|
.
|
\
|
=
= =
DS
DS
DS
c
c
V
N
n
D
V
N n D
V
N n
L y
y
D
N n
y x x
x
n
y x x
x
Ny Ny D
d Q
L
Z
I
d Q Z L I
d Q Z dy I
dy
d
Q Z
dx y x n y x q
dy
d
Z
dx J Z dxdz J I
|
|
|
|
|
|
|
|
|
|
|
0
0
0 0
) (
0
) (
0
) , ( ) , (
To find I
D
, we need an expression relating the
electrostatic potential, |, and Q
N
Capacitor-Like Model for Q
N
Assumptions:
Neglect all but the mobile inversion charge (valid for deep inversion)
For the MOSFET, the charge in the semiconductor is a linear function of
position along the semiconductor side of the plate. Thus, | varies from 0 to V
DS
MOS Capacitor MOS Transistor
( )
T GS
V V for > ~
T GS ox N
V V C Q
( )
T GS
V V for >
~ |
T GS ox N
V V C Q
Source
Drain
,
dV
dQ
C Since
ox
=
Neglect the depletion region charge
Note: Assuming a linear variation of potential along the channel
leads to an underestimation of current but is a good estimate for
hand calculations.
Only voltages above threshold create inversion charge
Using Capacitor-Like Model for Q
N
we can estimate I
D
as:
( )
( )
T GS Dsat DS
DS
DS T GS
ox n
D
V
T G ox
n
D
V
N
n
D
V V and V V
V
V V V
L
C Z
I
d V V C
L
Z
I
d Q
L
Z
I
DS
DS
> s s
(
=
}
}
=
=
=
=
0
2
2
0
0
| |
|
|
|
|
This is known as the square law describing the
Current-Voltage characteristics in the Linear or
Triode region.
Note the linear behavior for small V
DS
(can neglect V
DS
2
term). Note
the negative parabolic dependence for larger V
DS
but still V
DS
<V
Dsat
(can NOT neglect V
DS
2
term).
Capacitor-Like Model for Q
N
For V
DS
>V
dsat
the voltage drop across our channel is V
Dsat
with the remaining voltage
(V
DS
-V
Dsat
) dropped across the pinch-off region
( )
DS Dsat
Dsat
Dsat T GS
ox n
Dsat D
V V
V
V V V
L
C Z
I I s
(
= =
2
2
But the charge at the end of the channel is zero due to the pinched off channel,
( )
Dsat T GS
Dsat T GS ox N
V V V
or
V V V C L y Q
=
= ~ = 0 ) (
Thus,
( ) | |
DS Dsat T GS
ox n
Dsat D
V V V V
L
C Z
I I s = =
2
2
But what about the saturation region?

T GS Dsat
V V V =
( ) | |
DS Dsat T GS
ox n
Dsat D
V V V V
L
C Z
I I s = =
2
2
( )
T GS Dsat DS
DS
DS T GS
ox n
D
V V and V V
V
V V V
L
C Z
I
> s s
(
=
0
2
2
Summary of MOSFET IV Relationship

MOS Transistor Applications
Voltage variable Resistor
An n-channel MOSFET has a gate width to length ratio of Z/L=100, u
n
=200
cm
2
/Vsec, Cox=0.166 uF/cm
2
and V
T
=1V. We want to develop a resistor that has
a resistance that is controlled by an external voltage. Such a device would be used
in variable gain amplifiers, automatic gain control devices, compressors and
many other electronic devices. Define what range of V
DS
must be maintained to
achieve proper voltage variable resistance operation. Find the On-resistance
(V
DS
/I
D
) of the transistor from 1.5V<V
GS
<4Vfor small V
DS
.
First, to achieve voltage variable resistance operation, we must operate in the
linear region. Otherwise, the current is either a constant regardless of drain
voltage (saturation region) or is approximately zero (cutoff due to the capacitor
being in either accumulation and depletion).
Thus, V
GS
-V
T
>V
DS
. Given the values above, 0<V
DS
<0.5V
Continued...
Voltage variable Resistor
Using the linear region I
D
equation:
( ) ( ) | |
( ) | |
( ) | |
( ) ( ) | |
O s s O

=
= =
~
(
=
600 100
,
1 / 6 166 . 0 200
01 . 0
V small for
2
2
DS
2
DS
GS
DS
T GS ox n
DS T GS
ox n
DS
D
DS
DS
DS T GS
ox n DS
DS T GS
ox n
D
R
Thus
V cm F e
R
V V C
Z
L
V V V
L
C Z
V
I
V
R
V V V
L
C Z V
V V V
L
C Z
I

Current Source
The same transistor is to be used for a Current Source. Define the range of
drain-source voltage that can be used to achieve a fixed current of 50 uA.
For a constant current regardless of Drain-Source voltage, we must use the
saturation region:
( ) | |
( )
( )
V V
V
cm uF VSec cm
uA
V V V V
L
C Z
I I
GS
GS
DS Dsat T GS
ox n
Dsat D
173 . 1
1
2
/ 166 . 0 / 200 100
50
2
2
2 2
2
=
=
s = =

This source will operate over a V
DS
>V
GS
-V
T
or V
DS
>0.173 V
MOS Transistor: Deviations From Ideal
Channel Length Modulation Effect
Above pinch-off (when V
DS
>V
Dsat
=V
GS
-V
T
) the channel length reduces
by a value AL.
Thus, the expression for drain current,
Becomes,
( ) | |
DS Dsat T GS
ox n
Dsat D
V V V V
L
C Z
I I s = =
2
2
( )
( ) | |
( ) | |
DS Dsat T GS
ox n
Dsat D
DS Dsat T GS
ox n
Dsat D
V V
L
L
V V
L
C Z
I I
L
L
L L L
V V V V
L L
C Z
I I
s
|
.
|
\
|
A
+ = =
|
.
|
\
|
A
+ ~
A
( A
s
A
= =
1
2
1
1 1
L, L * since or
2
2
2
*In many modern devices, this assumption does not hold. Thus, the channel length modulation parameter we are deriving does not describe the IV
expressions well.
Channel Length Modulation Effect
DS
V
L
L
=
A
But the fraction of the channel that is pinched off
depends linearly on V
DS
because the voltage
across the pinch-off region is (V
DS
-V
Dsat
) so,
( ) | |( )
DS Dsat DS T GS
ox n
Dsat D
V V V V V
L
C Z
I I s + = =
1
2
2
where is known as the Channel-Length
Modulation parameter and is typically:
0.001 V
-1
< <0.1 V
1
Channel Length Modulation
causes the dependence of drain
current on the drain voltage in
saturation.
Body Effect (Substrate Biasing)
Until now, we have only considered
the case where the substrate (Body)
has been grounded.
but the substrate (Body) is often
intentionally biased such that the
Source-Body and Drain-Body
junctions are reversed biased.
The body bias, V
BS
, is known as the backgate bias and can be used to modify the
threshold voltage.
Note that now our channel potential has an offset equal to V
BS
, .
( )
( ) devices) channel - p (for 2
2
2
2
2
F
S
D
ox
S
F T
F
S
A
ox
S
F T
qN
C
V
qN
C
V
|
c
c
|
|
c
c
|
=
+ =
Thus, our threshold potential with the body grounded,
The Gate- Body Threshold becomes,
( )
( ) devices) channel - n (for 2
2
2
devices) channel - p (for 2
2
2
BS F
S
A
ox
S
BS F GB
BS F
S
D
ox
S
BS F GB
V
qN
C
V V
V
qN
C
V V
Threshold
Threshold
+ =
+ =
|
c
c
|
|
c
c
|
But we would like to have this in terms of V
GS
instead of V
GB
.
Since, V
GS
=V
GB
+V
BS
( )
( ) devices) channel - p (for 2
2
2
2
2
BS F
S
D
ox
S
F GS
BS F
S
A
ox
S
F GS
V
qN
C
V
V
qN
C
V
Threshold
Threshold
+ =
+ =
|
c
c
|
|
c
c
|
Surface Potential |
S
V
T
=
( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
ox
F BS F TO TP T
F BS F TO TN T
C
V V Jaeger V Pierret V
V V Jaeger V Pierret V
S A
2qN
where,
devices) channel - p (for 2 2
devices) channel - n (for 2 2
c
| |
| |
=
+ = =
+ = =
This can be rewritten in the following form (more convenient to reference the threshold
voltage to the V
BS
=0 case).
is known as the body effect parameter
MOS Transistor:
Enhancement Mode verses Depletion Mode MOSFET
We have been studying the enhancement mode MOSFET
(Metal-Oxide-Semiconductor Field Effect Transistor). It is called
enhancement because conduction occurs only after the channel
conductance is improved or enhanced. In this case,
V
TN
>0 and V
TP
<0
Transistors can be fabricated such that:
These transistors have conduction for V
GS
=0 due to a channel
already existing without the need to invert the near surface
region. To modulate currents, a field must applied to the gate that
depletes the channel. Thus, transistors of this nature are called
Depletion mode MOSFETs.
0 V and 0 V
TP TN
> s
MOS Transistor:
Enhancement Mode verses Depletion Mode MOSFET
MOS Transistor:
Summary
Jaeger uses the notation:
Pierret) in (Z Width Gate the is W where
PMOS
Pierret) in (Z Width Gate the is W where
'
'
L
W
C
L
W
K K
L
W
C
L
W
K K
NMOS
ox p p p
ox n n n
= =
= =
4-Terminal 3-Terminal
NMOS
(n-channel)
PMOS
(p-channel)
Enhancement Enhancement Depletion Depletion
MOS Transistor:
Summary
NMOS PMOS
Regardless of Mode
Cutoff
Linear
Saturation
Threshold Voltage
V
T
for Enhancement
Mode
V
T
for Depletion
Mode
Pierret) in Z W : (Note
'
= = =
L
W
C
L
W
K K
ox n n n
Pierret) in Z W : (Note
'
= = =
L
W
C
L
W
K K
ox p p p

TN GS DS
V V for I s = 0
TP GS DS
V V for I > = 0
( ) | |( )
0
1
2
2
> > >
+ =
TN GS DS TN GS
DS TN GS
ox n
DS
V V V and V V
V V V
L
C Z
I
( ) | |( )
0
1
2
2
> > s
+ =
TP GS DS TP GS
DS TP GS
ox n
DS
V V V and V V
V V V
L
C Z
I
( )
0
2
2
> > >
(
=
DS TN GS TN GS
DS
DS TN GS
ox n
DS
V V V and V V
V
V V V
L
C Z
I

( )
0
2
2
> > s
(
=
DS TP GS TP GS
DS
DS TP GS
ox n
D
V V V and V V
V
V V V
L
C Z
I

0 >
TN
V
0 s
TN
V
0 <
TP
V
0 >
TP
V
( ) ( )
F BS F TO TP
V V V | | 2 2 + = ( ) ( )
F SB F TO TN
V V V | | 2 2 + + =
MOS Transistor:
Bias Circuitry-Enhancement Mode NMOS
Due to zero DC current flow in the gate, the bias analysis of a MOSFET
is significantly easier than a BJT.
A B
C Form Thevenin
circuits looking out
the gate, drain, and
source
DS DS
GS th G
V R I V
V R I V
+ =
+ =
3 10
3
But I
G
=0 so V
GS
=3V
Assume Saturation operation (selected for
easy math because I
DS
does not depend on
V
DS
since no was given =0):
( ) | |
( ) | |
DS
DS
TN GS DS TN GS
n
DS
V Check
A
x
i
V v v for V v
K
i
50 1 3
2
10 25
0
2
2
6
2
= =
> > =
V V V V V
V k uA V
TN GS DS
DS
2 5
) 100 ( 50 10
= > =
+ =
Assumption of Saturation operation was correct! If it were not correct simply
make another assumption (I.e. linear region) and resolve.
MOS Transistor:
Bias Circuitry-Enhancement Mode NMOS
I
DS
I
G
MOS Transistor:
Bias Circuitry-Depletion Mode NMOS
Bias circuit of a depletion mode device is much simpler due to the fact
that the device conducts drain current for V
GS
=0V
What value of R1 results in 100 uA drain current?
Again Assuming saturation:
2
200
0
3
V
uA
K
V
V V
n
TO
=
=
=
( ) | |
( )
( )
V V V V V V V
V k uA V R I V
V Check
K
uA I
V
R
V
V uA
uA
V
K
I
V V
V v v for V v
K
i
TN GS DS
DS DS DS
DS
DS
GS
n
DS
TN GS
TN GS DS TN GS
n
DS
1 ) 3 ( 2 8
20 100 1 10
20
100
2
1
2
/ 200
100 2
3
2
0
2
2
2
+ = = > =
+ = + =
O =
= =
= + = + =
> > =
I
DS
Assumption of Saturation operation was correct! If it were not correct simply
make another assumption (I.e. linear region) and resolve.
PMOS Transistor:
Bias Circuitry-Enhancement Mode PMOS
2
25
0
1
V
uA
K
V
V V
p
TO
=
=
=
( ) | |( ) ( ) | |
( ) | |
( ) | |
( ) | |
0 ) 1 ( 66 . 2 08 . 6 0
08 . 6
4 . 34 1 66 . 2
2
6 25
66 . 2 71 . 2 0 21 . 7 051 . 0
1
2
6 25
000 , 39 4 6 10
2
600 5 . 1 || 1 6
1 5 . 1
5 . 1
10
0
2
1
2
2
2
2
2
2 2
> > > >
= + =
= +
=
+ = =
+
= =
=
+ + =
O = = =
+
=
> > s
= + = =
TP GS DS
DS
DS D D DS S D DD
D
GS GS GS
GS GS
GS TP GS
p
S EQ DD
EQ G G GS S S DD
EQ EQ
TP GS DS TP GS
TP GS
p
DS TP GS
ox n
S D
V V V
V Check
V V R I V R I V
A
E
I
V or V V V
V V
E
V V V
K
R V V
V R I V R I V
K M M R V
M M
M
V V
V V V and V V
V V
K
V V V
L
C Z
I I

MOS Transistor:
Bias Circuitry-Possible Combinations
( ) ( ) | | ( )
( )
Source th Drain th Source th DS DS Drain th
DS
DS TN GS n DS DS TN GS
n
DS
Source th Source th DS GS Base th
V R R I V V
optionally and
V
V V V K I or V V V
K
I
V R I V V
_ _ _ _
2
2
_ _ _
) 3
,
2
1
2
) 2
) 1
+ + + =
(
= + =
+ + =
Always: Solve 1) for V

GS
and plug into 2).
In certain cases, V
DS
will need to be eliminated by using
3) solved for V
DS
and plugged into 2).
Case A: Saturated, and =0 and no source resistor
only 1 and 2 required. Results in 1
st
order polynomial.
Case B: Saturated, and >0 and no source resistor all
3 equations needed. Results in 1
st
order polynomial.
Case C: Saturated, and =0 and a source resistor all 3
equations needed. Results in 2
nd
order polynomial.
Case D: Saturated, and >0 and a source resistor all 3
equations needed. Results in 3
rd
order polynomial.
Case E: Linear/Triode, with or without a source resistor
all 3 equations needed. Results in 2
nd
order
polynomial.
Assume either saturated or linear/triode.
Useful Formulas for DC Bias Solutions
If a 3
rd
order polynomial results, try factoring it into a linear and quadratic term 1
st
. If
this is not easy for your case, a longer but sure fire way is listed below.

Lecture25 MOSTransQuantitativeId VD VG

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Lecture25 MOSTransQuantitativeId VD VG

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ECE 3040 - Dr.

Alan Doolittle Georgia Tech

But what about the saturation region?

Summary of MOSFET IV Relationship

ECE 3040 - Dr. Alan Doolittle Georgia Tech

Always: Solve 1) for V

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