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R09

III B.Tech II Semester Examinations, APRIL 2012 VLSI DESIGN (CSE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks 1. (a) What is the principle of FPGAs? Explain about the architectures fo FPGAs. (b) What are the applications of FPGAs? Explain. 2. Draw the circuit for NMOS Inverter and explain its operation. 3. (a) Explain the processing steps in fabrication of nmos technology with neat sketches. (b) Explain any one method of encapsulation of IC. 4. (a) Explain about the effect of scaling on MOSFET parameters. i. Gate Area ii. Gate capacitance iii. Channel Resistance iv. Transistor Delay (b) Explain about Design Rules for contact cuts. 5. (a) What are the differences between a gate array chip and standard-cell chip? What benefits does each implementation style have? (b) Write the equations for a full adder in SOP form. Sketch a 3-input, 2- output PLA implementing this logic. 6.Design a stick diagram and layout for the CMOS logic shown below.

SET-1

Max Marks: 80

[8+8] [16]

[10+6]

[8+8]

[8+8] [16]

7.a)Explain RAM&ROM read& write operations with neat sketches? b)Compare RAM,ROM,SRAM,DRAM,EPROM,PROM w.r.t speed, cost,volatility&Non-volatility, applications? [7+9] 8.a)Briefly explain about need for testing &its principles? b)Explain different fault models in testing? c)Explain TAP controller using state Diagram?

[5+5+6]

R09
III B.Tech II Semester Examinations, APRIL 2012 VLSI DESIGN (CSE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks

SET-2

Max Marks: 80

1. (a) Draw the circuit and layout schematic for 2-input NOR gate giving explanation. (b) What are the various limitations of scaling? 2. Draw the circuit for CMOS inverter and explain the transfer characteristic using necessary equations, and the different regions in the characteristic. 3. (a) Explain the structure and principle of PLA. (b) Draw the schematic and explain how Full Adder can be implemented using PLA's.

[8+8]

[16]

[6+10] 4. Explain the following (a) Double metal MOS process rules. (b) Design rules for P- well CMOS process. 5. Describe the flow diagram of Berkeley N well fabrication. 6 (a) With neat sketches, explain the transfer characteristics of a CMOS inverter. (b) Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region.

[8+8] [16]

[8+8]

7. (a) Explain the differences between the Full Scan& Partial Scan? What are the different levels of testing? (b) Write about scan based testing with neat sketch? [6+6+4] 8.a)Briefly explain SRAM with neat sketches? b)What are the differences between SRAM&DRAM?

[8+8]

R09
III B.Tech II Semester Examinations, APRIL 2012 VLSI DESIGN (CSE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks 1. (a) Explain the processing steps in fabrication of PMOS technology with neat sketches. (b) What are the additional two layers in BICMOS technology compared to other. 2. (a) Explain about stick diagram. (b) Explain about scaling& its limitations?. 3. (a) Draw the circuit of CMOS Inverter and explain its operation. (b) What are the various pull up transistor used for inverters?

SET-3

Max Marks: 80

[10+6]

[8+8]

[8+8]

4. (a) Draw the structure of programmable Array logic(PAL) and explain its principle of operation. (b) Explain about different methods of implementation approaches in VLSI Design. 5.Briefly discuss the limits of scaling. Why scaling is necessary for VLSI circuits? 6. Design a layout diagram for the NMOS logic shown below

[8+8] [16]

[16] 7.a)Explain the Design strategies for test? b)Write short notes on i)Chip level test techniques ii)System level test techniques

[6+10]

8.a)Explain SRAM&DROM read& write operations with neat sketches? b)Compare RAM,ROM,SRAM,DRAM,EPROM,PROM w.r.t speed, cost,volatility&Non-volatility, applications [8+8]

R09
III B.Tech II Semester Examinations, APRIL 2012 VLSI DESIGN (CSE) Time: 3 hours Answer any FIVE Questions All Questions carry equal marks 1.Explain the principle and working of CPLDs and give their applications. 2. Draw the circuits for n-MOS, p-MOS and C-MOS Inverter and explain about their operation and compare them.

SET-4

Max Marks: 80

[16]

[16]

3.(a) Why scaling is required? (b) How does Depletion Regions around Source and Drain are affected due to scaling down of device dimensions? Explain. [6+10] 4. Draw the structure, explain the function and write the applications characteristics of the following programmable CMOS devices: (a) PLA (b) PAL (c) FPGA (d) CPLD. 5. Discuss the Gate logic with reference to the following: (a) NMOS and CMOS inverters. (b) NMOS- NAND and CMOS NAND gates (c) NMOS- NOR and CMOS- NOR gates. 6. Explain the following terms related to the fabrication of IC (a) Diffusion (b) oxidation (c) Lithography (d) Metallization. 7. Explain the following in brief: (a) Chip level test techniques (b) System level test techniques.

[16]

[4+6+6]

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[8+8]

8 a)Explain SRAM&DROM read& write operations with neat sketches? b)Compare RAM,ROM,SRAM,DRAM,EPROM,PROM w.r.t speed, cost,volatility&Non-volatility, applications [8+8]