MOS Theory, SPICE, CMOS Fabrication Lecture

Lecture 2 Basic MOS Theory, SPICE Simulation, CMOS Fabrication
Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London
URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@imperial.ac.uk

MOS Theory, SPICE, Fabrication Introduction to Digital Integrated Circuit Design Lecture 2 - 1
Based on slides/material by
P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html Digital Integrated Circuits: A Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison Wesley
MOS Theory, SPICE, Fabrication
Introduction to Digital Integrated Circuit Design
Lecture 2 - 2
Recommended Reading
J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective: Chapter 2 (2.1 2.3), Chapter 3 (3.3) Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective: Chapter 2, Chapter 3 (3.2), Chapter 5.
Lecture 2 - 3
Outline
MOS transistors SPICE simulation CMOS fabrication process Layout rules
Lecture 2 - 4
MOS Transistor
Shown here is the cross-section of an n-channel enhancement transistor: Substrate is moderately doped with p-type material. Substrate in digital circuit is usually connected to VGnd (ground). The source and drain regions are heavily doped with n-type material through diffusion. These are often referred to as the diffusion regions.
Lecture 2 - 5
Conduction Characteristics of MOS Transistors (for fixed Vds)

MOS transistors are majority-carrier devices. For n-channel transistors, the majority carriers are electrons conducted through a channel. A positive gate voltage (w.r.t. substrate) enhances the number of carriers in the channel, and increases conduction. Threshold voltage Vtn denotes the gate-to-source voltage above which conduction occurs. For enhancement mode devices, Vtn is positive; for depletion mode devices, Vtn is negative. p-channel devices are similar to n-channel devices, except that all voltages and currents are in opposite polarity.
Lecture 2 - 6
Cross-Section of CMOS Technology
Lecture 2 - 7
MOS transistors - Types and Symbols
G S
NMOS Enhancement
NMOS Depletion
S
PMOS Enhancement
S
G S
NMOS with Bulk Contact
Lecture 2 - 8
Threshold Voltage: Concept
S -
+ V GS G
n+
n+
n-channel p-substrate B
Depletion Region
Lecture 2 - 9
MOS transistor (1)

Between the diffusion regions is the gate area form from a layer of polycrystaline silicon (known as polysilicon). This is separated from the substrate by a layer of thin oxide (made of silicon dioxide). Polysilicon is reasonable conductor and form the gate electrode. Underneath the thin oxide and between the n+ regions is the channel. The channel is conducting when a suitable electric field is applied to the gate. Due to geometric symmetry, there are no distinctions between the source and drain regions. However, we usually refer the terminal with more positive voltage the drain (for n-type) and less positive voltage the source. For a zero gate bias and a positive VDS, no current flows between the drain and source because of the two reverse biased diodes shown in the diagram. The drain and source are therefore isolated from each other. Assuming that the substrate is always at the most negative supply voltage, these two diode should never become forward bias under normal operation.
Lecture 2 - 10
MOS transistor (2)

When a positive voltage is applied to the gate, an electric field is produced across the substrate which attracts electrons toward the gate. Eventually, the area under the gate changes from p-type to n-type, providing a conduction path between the source and drain. The gate-source voltage VGS when a channel starts to form under that gate is called the threshold voltage VT. The surface underneath the gate under this condition is said to be inverted. The surface is known as the inversion layer. As larger bias is applied to the gate the inversion layer becomes thicker An other p-n junction exists between the inversion layer and the substrate. This diode junction is field induced. Contrast this with the p-n junction between the source (or drain) and the substrate, which is created by a metallurgical process.
Lecture 2 - 11
The Threshold Voltage
Lecture 2 - 12
Current-Voltage Relations
V GS G
V DS D n+ L x ID
n+
V(x)
p-substrate B
MOS transistor and its bias conditions

Current-Voltage Relations
Lecture 2 - 14
Transistor in Saturation
VG S V DS > VGS - V T D
G S n+
-
VG S - VT
n+
Lecture 2 - 15
MOS transistor (3)

As a voltage is applied between the source and drain, the inversion layer becomes thinner at the drain terminal due to interaction between VG and VD. If VDS < VGS - VT, then the drain current Id is a function of both VGS and VDS. Furthermore, for a given VDS, ID increases linearly with (VGS - VT). The transistor is said to be operating in its linear or resistive region. If VDS > VGS - VT, then VGS < VT and no inversion layer can exist at the drain terminal. The channel is said to be 'pinched-off'. The transistor is operating in the saturation region, where the drain current is dependent on VGS and is almost independent of VDS.
Lecture 2 - 16
I-V Relation
Lecture 2 - 17
A model for manual analysis
Lecture 2 - 18
Dynamic Behavior of MOS Transistor

G
CGS S
CGD D
CSB
CGB
CDB
B
The Gate Capacitance
Lecture 2 - 20
Average Gate Capacitance
Different distributions of gate capacitance for varying operating conditions
Most important regions in digital design: saturation and cut-off
Lecture 2 - 21
Issues concerning Sub-Micron MOS Transistors

Threshold Variations Parasitic Resistances Velocity Saturation Mobility Degradation
Lecture 2 - 22
Threshold Variations
VT Long-channel threshold Low VDS threshold
L Threshold as a function of the length (for low VDS) Drain-induced barrier lowering (for low L)
Lecture 2 - 23
Parasitic Resistances
Lecture 2 - 24
Velocity Saturation (1)
Lecture 2 - 25
Velocity Saturation (2)
1.5 VGS = 5 1.0 I D (mA) VGS = 4 VGS = 3 0.5 VGS = 2 VGS = 1 0.0 1.0 2.0 3.0 VDS (V) 4.0 5.0
Linea r Dependence
0.5
ID (mA) 0 0.0
1.0 2.0 V G S (V)
3.0
(a) I D as a function of V DS
(b) ID as a function of V G S (for VDS = 5 V).
Linear Dependence on VGS

Sub-Threshold Conduction
102 104 ln(ID) (A) 106 108 1010 1012 0.0 Subthreshold exponential region Linear region
VT 1.0
2.0 VGS (V)
3.0
Lecture 2 - 27
Latch-up problem (1)

The p+ region of the p-transistor, the n-well and the p- substrate form a parasitic pnp transistor T1. The n- well, the p- substrate and the p+ source of the n-transistor forms another parasitic npn transistor T2. There exists two resistors Rw and Rs due to the resistive drop in the well area and the substrate area.
Lecture 2 - 28
Latch-up problem (2)

T1 and T2 form a thyristor circuit. If Rw and/or Rs are not 0, and for some reason (power-up, current spike etc), T1 or T2 are forced to conduct, Vdd will be shorted to Gnd through the small resistances and the transistors. Once the circuit is 'fired', both transistors will remain conducting due to the voltage drop across Rw and Rs. The only way to get out of this mode is to turn the power off. This condition is known as latch-up. To avoid latch-up, substrate-taps (tied to Gnd) and well-taps (tied to Vdd) are inserted as frequently as possible. This has the effect of shorting out Rw and Rs.
Outline
Lecture 2 - 30
What is SPICE Circuit Simulator?

SPICE is a widely-used circuit-level simulator, originally from Berkeley. SPICE uses numerical techniques to solve nodal analysis of circuit. It supports the following:
Textual input to specify circuit & simulation commands Text or graphical output format for simulation results
You can use SPICE to specify these circuit components:

Resistors, Capacitors, Inductors Independent sources (V, I), Dependent sources (V, I) Transmission lines Active devices (diodes, BJTs, JFETS, MOSFETS) non-linear d.c. non-linear transient linear a.c. Noise & temperature
Introduction to Digital Integrated Circuit Design Lecture 2 - 31
You can use SPICE to perform the following types circuit analysis:
SPICE MODELS
Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Em perical - Simple and Popular
Lecture 2 - 32
MAIN MOS SPICE PARAMETERS
Lecture 2 - 33
SPICE Parameters for Parasitics
Lecture 2 - 34
SPICE Transistors Parameters
Lecture 2 - 35
Fitting level-1 model for manual analysis
Region of matching ID Short-channel I-V curve
V GS = 5 V
Long-channel approximation V DS = 5 V V DS
Select k and such that best matching is obtained @ V gs = V ds = V DD
Lecture 2 - 36
Technology Evolution
VDD decreases
Save dynamic power Protect thin gate oxides and short channels No point in high value because of velocity sat.
Vt must decrease to maintain device performance But this causes exponential increase in OFF leakage Major future challenge
Lecture 2 - 37
Outline
Lecture 2 - 38
CMOS Fabrication
CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
Lecture 2 - 39
Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
Vi Qn VDD
Qp Vo
A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1
Lecture 2 - 40
Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps
A GND Y VDD
p+
n+
n+ p substrate
p+ n well
p+
n+
substrate tap
MOS Theory, SPICE, Fabrication Introduction to Digital Integrated Circuit Design
well tap
Lecture 2 - 41
Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line
GND nMOS transistor substrate tap

VDD pMOS transistor well tap

Lecture 2 - 42
Detailed Mask Views

Six masks

n-well Polysilicon n+ diffusion p+ diffusion Contact Metal
n well
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
Lecture 2 - 43
Fabrication Steps
Start with blank wafer Build inverter from the bottom up First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2
p substrate
Lecture 2 - 44
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
Lecture 2 - 45
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer Softens where exposed to light
Photoresist SiO2
p substrate
Lecture 2 - 46
Lithography
Expose photoresist through n-well mask Strip off exposed photoresist
Photoresist SiO2
p substrate
Lecture 2 - 47
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
Photoresist SiO2
p substrate
Lecture 2 - 48
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
SiO2
p substrate
Lecture 2 - 49
n-well
n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si
Ion Implantation
Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
SiO2 n well
Lecture 2 - 50
Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
n well p substrate
Lecture 2 - 51
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer

Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
Polysilicon Thin gate oxide n well p substrate
Lecture 2 - 52
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon Thin gate oxide n well p substrate
Lecture 2 - 53
Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact
n well p substrate
Lecture 2 - 54
N-diffusion
Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing
n+ Diffusion
n well p substrate
Lecture 2 - 55
N-diffusion cont.
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n+
n+ n well p substrate
n+
Lecture 2 - 56
N-diffusion cont.
Strip off oxide to complete patterning step
n+
n+ n well p substrate
n+
Lecture 2 - 57
P-diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+ p substrate
p+ n well
p+
n+
Lecture 2 - 58
Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
Contact
Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+
Lecture 2 - 59
Metalization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
M e ta l
Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+
Lecture 2 - 60
Outline
Lecture 2 - 61
Layout
Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
Lecture 2 - 62
Design Rules
Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)
Lecture 2 - 63
CMOS Process Layers
Layer
Color
Representation
Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via
Yellow Green Green Red Blue Magenta Black Black Black
Lecture 2 - 64
Intra Layer Design Rules
Same Potential 0 or 6 10 3 Active 3 2 Select
Different Potential 9 Polysilicon 2 Metal1 Contact or Via Hole 2 2

Metal2 3
Well
3
4
Lecture 2 - 65
Transistor Layout
Transistor
Lecture 2 - 66
Vias and Contacts
2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4
2 2
Lecture 2 - 67
Select Layer
2 3 2 1 3 3 Select
Substrate
Well
Lecture 2 - 68
CMOS Inverter Layout
GND
In
VD D
Out (a) Layout
A p-substrate n
+
A n p
+
Field Oxide
(b) Cross-Section along A-A

Summary
MOS transistor: majority carrier device building block of integrated circuits SPICE: popular circuit level simulator that applies nodal analysis of circuit CMOS transistors are fabricated on silicon wafer
Lithography process Different materials are deposited or etched in each step
Layout rules: contract between IC designer and process engineer

Guidelines for constructing process masks
Lecture 2 - 70

MOS Theory, SPICE, CMOS Fabrication Lecture

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Lecture 2 Basic MOS Theory, SPICE Simulation, CMOS Fabrication

URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@imperial.ac.uk

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Conduction Characteristics of MOS Transistors (for fixed Vds)

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Cross-Section of CMOS Technology

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS transistors - Types and Symbols

NMOS with Bulk Contact

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Threshold Voltage: Concept

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS transistor (1)

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS transistor (2)

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

The Threshold Voltage

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS transistor and its bias conditions

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS transistor (3)

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

A model for manual analysis

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Dynamic Behavior of MOS Transistor

The Gate Capacitance

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Average Gate Capacitance

Different distributions of gate capacitance for varying operating conditions

Most important regions in digital design: saturation and cut-off

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

Issues concerning Sub-Micron MOS Transistors

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

VT Long-channel threshold Low VDS threshold

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design

MOS Theory, SPICE, Fabrication

Introduction to Digital Integrated Circuit Design