The 15th Conference of Electric Supply Industry 2004, October 18-22, 2004, Shanghai, China

Parameter Optimization for Frequency Limit Controller of EGAT-TNB HVDC Interconnection System
NitusVoraphonpiput Electricity Generating Authority of Thailand Thailand Kittipon Chuangaroon Electricity Generating Authority of Thailand Thailand Somchai Chatratana National Science and Technology Development Agency Thailand

Abstract
The Tenaga Nasional Berhad (TNB, Malaysia) the Electricity Generating Authority of Thailand (EGAT) HVDC 300 kV, 300 MW interconnection system was commissioned in 2001 for energy exchange between Thailand and Malaysia. The HVDC system was chosen for both rapid power exchange and electric power system stability. Inside the HVDC pole control, there are four stability functions, namely: Run-up, Run-down, Frequency Limit Control (FLC) and Power Swing Damping. The Frequency Limit Control (FLC) prevents system frequency excursion when generators or loads are tripped out of the power system. The FLC increases, or decreases DC power to recover the system frequency back within the acceptable band. This paper describes the design of Proportional plus Integral (PI) controllers of the Frequency Limit Control. The first PI controller is used to reduce the system frequency and the second PI controller is used to raise the system frequency. The PI controllers were optimized by optimal control technique. The integral square error (ISE) criterion is used and the integral of the frequency deviation square plus the DC power deviation square with respect to time is defined as performance index. The computer simulation is made on simple governor-turbine models of each generation type, Thailand main grid parameters, Automatic Generation Control (AGC.) and HVDC Frequency limit control. Due to the complication of the system and the nonlinearity of the FLC, the numerical method is proposed. The numerical Powell algorithm is used for parameters optimization. The simulation results indicate that the parameters obtained from the optimization algorithm give the best performance in terms of minimum frequency deviation and necessary dc power transfer. Simulation results are in good agreement with recommended practices.

Key words:
HVDC, Frequency Limit Control (FLC), Load Frequency Control (LFC), Integral Square Error (ISE)

Contact
Nitus Voraphonpiput System Control and Operation Division, Electricity Generating Authority of Thailand 53 Charansanitwong Rd. Bangkrui Nonthaburi Thailand 11130 phone: 662-4362174 Fax. 662-4362191 Email: nitus.v@egat.co.th Kittipon Chuangaroon Control and Protection System Division, Electricity Generating Authority of Thailand 53 Charansanitwong Rd. Bangkrui Nonthaburi Thailand 11130 phone: 662-4362174 Fax. 662-4362191 Email: kittipon.c@egat.co.th Somchai Chatratana National Science and Technology Development Agency 111 Thailand Science Park, Paholyothin Rd., Klong 1, Klong Luang, Pathumthani, 12120, Thailand phone: 662-5647000 Fax. 662-5647003 Email: somchaich@nstda.or.th

1. Introduction
In 2001, The Tenaga Nasional Berhad (TNB, Malaysia) and Electricity Generating Authority of Thailand (EGAT) have installed the HVDC 300 kV, 300 MW system on the southern part of Thailand and the northern part of Malaysia. The converter station was installed at the KNE substation, Thailand and at Gurun substation, Malaysia. This HVDC is an only linked system between two countries. The previous ac system is used only for backup. The main purpose of HVDC project is to exchange the energy between two countries with additional benefit of ac system stabilization. This is the reason that stability functions were installed in the pole control of both sides. The stability functions are realized in software and implemented in the hardware of the HVDC pole control systems. The transient stability control function softwares are included in the function package WPACT (Power Order Setting Function for Transient Stability). The four functions of transient stability control are as follows: - Power Run-Up - Power Run-Back - Power Swing Damping (Dual Frequency Modulation) - Frequency Limit Control The Power Run-Up and Power Run-Back are used to prevent under frequency relay from tripping the southern part generation out of the system. The Power Swing Damping is used to reduce the oscillations in the tie-lines between the central part and the southern part of Thailand. At the moment, the Power Swing Damping studies are in progress. The Frequency

The 15th Conference of Electric Supply Industry 2004, October 18-22, 2004, Shanghai, China

Limit Control (FLC) protects frequency excursion of the system. The frequency excursion can occur when a generator or load is tripped out of the power system. The FLC provides incremental DC power compensation to bring the system frequency back within the acceptable band.

2. Frequency Limit Control

The Frequency Limit Control is a modulation function in the Power Order Setting Function for Transient Stability Control (POAC), which is realized in software. The function diagram of modulation is shown in figure 1, [1]. In the expansion box POAC, four signals are created from four functions of the transient stability control. These four signals are summed to give the output signal Pdc of the POAC block. Pdc from both stations (3FP-WPAC) are summed again to form the AC power reference signal (PrefAC). The AC power reference signal (PrefAC) is then divided by the voltage at (P/U) function unit to form an AC current command (IdrefAC). IdrefAC is then added to the output of the (P/U) function unit of P dref DC of the Power order at the Pole-Pole Power Transfer (PPT) function in 5FP-CC_T3 block. The result of the summation is I dref , which is then compared with the I margin to give the control signal I dc control.

Rectifier

Inverter
- Imargin

5FP-CC T3 Power order

PdrefDC To Idc control

P/U

Idref

PPT

3FP-WPAC Disable Activate POAC

PdrefAC

IdrefAC To PdrefAC

3FP-WPAC Disable POAC Activate

P/U

POAC Disable Run-Back Run-Up Power Swing Damping Activate Frequency Limit Control Figure 1 Power Order Setting Function for Transient Stability (POAC) Block Diagram In principle, the Frequency Limit Control function is designed to prevent frequency excursion when the generation units or loads are tripped out of the power system. This function calculates the deviation of system frequency and corrects the deviation with the incremental dc power transfer. For example, during the moment that the ac system receives dc power from HVDC, a load is tripped out. The system frequency will increase and finally exceed the upper bound. The Frequency Limit Control function will reduce the dc power transfer and the system frequency is recovered to the normal value. In case of tripping-out of a generation unit, the system frequency decreases and eventually falls below the acceptable band. The Frequency Limit Control function will increase the dc power transfer to compensate the loss of ac power and the system frequency will be recovered back to 50 Hz. Figure 2 shows the diagram of the Frequency Limit Control [1]. The input signal of the Frequency Limit Control is Actual Frequency [Hz] which is measured from the ac power system. The first order delay block with 0.02 second time constant is added to prevent rapid change of input signal. The output of first order delay block is then compared with Nominal Value: 50 Hz and the frequency error is limited to be within 5 Hz. The output signal from this limiter block is multiplied with -1, if the host station is operating in the rectifying mode and with +1, if the host station is operating in the inverting mode. The result of multiplication is added with the Lower set-point and the result of addition becomes an input of upper PI controller (PI controller with low limit). Moreover, the result of multiplication is also subtracted with the Upper set-point and the result of subtraction becomes an input of lower PI controller (PI controller with high limit).The bottom PI controller (associated with

Pdc

The 15th Conference of Electric Supply Industry 2004, October 18-22, 2004, Shanghai, China

Upper set-point) creates positive power reference signal (Pdc) and the top PI controller(associated with Lower set-point) creates negative power reference (Pdc).
50 Hz

+
Fmin = 49.75 Hz

+
Rectifier 1 -1

Kp=0.1 Lower Tn=10 sec set-point

0 -0.35 pu

T=0.02 sec Actual Frequency

+
5Hz

+ + +
Kp=0.1 Upper Tn=10 sec 0.25 pu set-point 0 Enable

Pdc

-5Hz

Fmax = 51.00 Hz

+
Pole for Stability Function enabled Stability Function enabled Power Swing Damping Function enabled

&

Figure 2 Frequency Limit Control Diagram The proportional gain and integral time constant of both controllers were initially set (by the manufacturer) at 0.1 and 10 seconds, respectively. The Lower set-point is the subtraction of nominal frequency and the low frequency limit. The low frequency limit is set at 49.75 Hz so the subtraction result is 0.25 Hz. The higher set-point is the subtraction of the high frequency limit and nominal frequency. The high frequency limit is set at 51.0 Hz. The subtraction result is -1.0 Hz. The band between high and low limit is fixed at least 1 Hz because of software condition [1]. Both controllers will not create output at the same time because of high and low limiter block inside. Therefore, the power reference signal (Pdc) comes from only one PI controller. The final output signal of Frequency Limit Control is summed with signals from other stability function in the POAC block and then fed to the division block (P/U), which finally becomes an AC current order (IrefAC).

3. Model for Frequency Control Study

The model for frequency control study is presented as block diagram in figure 3. Three control loops can be made out from the diagram. The first (inner) loop is the primary control loop (shown by dash line), which consists of three governorturbine models with speed droop feedback and system grid, [2],[3]. Three governor-turbine models are thermal plant, hydro plant and combined cycle plant (CC-GT). In this study, the normal system spinning reserve is assumed at 1,000 MW. The approximated distribution of spinning reserve among thermal plant group, hydro plant group and combined cycle plant group are 600 MW, 200 MW and 200 MW respectively. The thermal plant and hydro plant are modeled by simple governor-turbine model which is presented in [4]. The combined cycle plant model is modeled by simple CC-GT model presented in [3]. The speed droop of each type of power plant are specified as follows: 11% for thermal plant, 5% for hydro plant and 5 % for CCGT plant. The system grid is modeled as first order delay.
f
Governor and Turbine Model of Hydro Plants
*

PH

PL f

Automatic Generation Control

6 sec

S&H

Governor and Turbine Model of Thermal Plants Governor and Turbine Model of CC-GT Plants

PT

System Grid

PC

HVDC Frequency Limit Control (FLC) Model

Pdc

Figure 3. Model for Frequency Control study

The 15th Conference of Electric Supply Industry 2004, October 18-22, 2004, Shanghai, China

The second (outer) loop is an automatic generation control (AGC), which consists of the integral element, the sampling and hold element and the primary loop. The third loop consists of an independent HVDC Frequency Limit Control. When power unbalance occurs, the primary loop adjusts the generation with the setting droop. However, the reaction from the speed droop alone cannot balance the increase in power generation with the power loss. The system frequency still does not recover to the set value (50 Hz). The secondary loop detects this frequency error and adjusts the generation from all power plants by sending a new power setting (P*). The action of AGC can now recover the system frequency back to 50 Hz. The new power setting occurs every 6 seconds because SCADA scans and calculates the new setting within 6 seconds. Therefore, the 6 second-sampling and hold function is inserted in the AGC loop. The HVDC frequency limit control function is independent from the generation control and is installed in HVDC pole control. The system frequency error signal (f) is fed into the FLC to create an additional control signal (Pdc) and this signal is used to compensate the deviation of system frequency. The FLC model, which is modified from figure 2, is shown in figure 4. [5]
50 Hz

+
Fmin = 49.75 Hz

Kp=0.1 Tn=10 sec 0 Rectifier =1 Inverter = -1 K=600 T=0.8 sec

T=0.02 sec

-300 Lower limit controller

5Hz

Pdc

-1 -5Hz Kp=0.1 Tn=10 sec

+
300 0

+
Fmax = 51.00 Hz

50 Hz

+
Upper limit controller

Figure 4. HVDC Frequency Limit Control Model

4. System Simulation
In the simulation, the tripping of 700 MW generations out of the ac system is defined as disturbance. It is assumed that there were enough spinning reserves (1000 MW); therefore the system could recover back to the normal frequency. The simulation result, with only the action of primary loop and outer loop is shown in figure 5. It is evident that after the disturbance, the system frequency fell very fast and the maximum frequency deviation was 0.358 Hz.
Incremental Power [MW]

Without FLC

Frequency Deviation [Hz]

Incremental Power [MW]

Without FLC

Frequency Deviation [Hz]

400 300

Thermal Plant Hydro Plant

0.4 0.3 0.2

400 300

Thermal Plant Hydro Plant

0.4 0.3 0.2

200 100 0 -100 -200 -300 -400 0 25 50 75 Time [sec] 100 125

200 100 0 -100 -200 -300 -400 0 25 50 75 Time [sec] 100 125

CC-GT Plant

0.1 0.0 -0.1

DC Power

CC-GT Plant

0.1 0.0 -0.1

Frequency Deviation

-0.2 -0.3 -0.4 150

Frequency Deviation

-0.2 -0.3 -0.4 150

Figure 5. Incremental Power compensation and Frequency Deviation without FLC

Figure 6. Incremental Power compensation and Frequency Deviation with FLC (Kp = 0.1 and Tn = 10 sec)

After maximum falling, system frequency turned back slowly to the normal setting value. The recovery completed after 100 seconds. The simulation results in figure 5 shows that each generation type has different response to the disturbance. The thermal power plant gives slow response but it has a lot of spinning reserve. The hydro power plant gives inverse response at the first few second before providing necessary compensation. However, the response of hydro power plant is faster than thermal power plant. The CC-GT power plant has very fast response. It increases their megawatt output rapidly, but the spinning reserve is normally small. The system operators have to operate CC-GT power plant near the high limit due to economic reason. In the next case, the action of HVDC Frequency limit Control is included. The incremental DC power was calculated by PI-controller. The initial settings of proportional gain for both controllers were 0.1 and integrating time constant were 10

The 15th Conference of Electric Supply Industry 2004, October 18-22, 2004, Shanghai, China

seconds. The simulation results, with the same disturbance, are shown in figure 6. The DC power could be rapidly increased by FLC controller. However, FLC did not act at the disturbance time. It was activated when the system frequency was lower than the lower limit (Fmin = 49.75 Hz) or higher than the upper limit (Fmax = 51.0 Hz). Even though HVDC provided additional power but the system frequency response was the same as in figure 5.The maximum deviation in this case is 0.357 Hz. The system frequency was not improved because the addition DC power was not appropriate. Therefore, the new settings for controllers are necessary. The study was made only on low frequency problem because the upper limit setting is quite high and the high frequency problem has less probability.

5. Parameters Optimization
The design objective is the regulation of system frequency with necessary DC power supply from HVDC system. DC power supply to one side of the interconnection acts as disturbance on the other side of the interconnection. Therefore, it is important to ensure that only necessary amount of DC power are drawn from the other side. For this reason, the Integral Square Error Criterion, which taking into account of frequency deviation and incremental DC power transfer, is proposed as performance index as shown in (1).

J=

{(f )
0

+ (rPdc )2 dt

(1)

where

f Pdc
r

is cost function or performance index is deviation of system frequency [Hz] is incremental of DC power [pu] is positive weighting for DC power

The equation (1) is cost function that has to be minimized. The unknown parameters are proportional gain (Kp) and integrating time constant (Tn). The appropriate weighting (r) is unknown at this stage but the small weighting means more DC power transfer is allowed. The optimization process started by assigning initial values to the gain and time constant (0.1 and 10 secs) of the top PI controller associated with Lower set-point. The system in figure 3 was then simulated with the conditions of disturbance. The performance index was calculated with a specified positive weighting for DC power (r). The performance index is then minimized to obtain optimum gain and time constant of the controller. The process was repeated with the value of positive weighting for DC power (r) from 0.2 up to 0.7 with 0.1 step increase.

6. Simulation results
The optimum results of each weighting are shown in table 1. The simulation was carried out on VISSIM. The Powell search method was selected as an algorithm for finding the optimum solution. The simulation period started at 0.0 second and finished at 150 second. The results of initial setting and without FLC case are included. The dynamic response of each weighting are shown in figure 7 and figure 8. Table 1. Optimal Results of Varied Weighting r = 0.2 r = 0.3 r = 0.5 r = 0.6 r* = 0.4 11.421 0.547 1479.3 0.358 300.0 1.715 6.708 1.774 1017.3 0.352 274.3 1.753 3.918 3.331 931.4 0.345 164.6 1.786 2.477 4.305 813.5 0.346 114.9 1.806 1.720 4.976 691.2 0.347 90.1 1.825

Weighting Optimum Kp Optimum Tn [sec] Incremental Energy [MJ] Maximum Frequency Deviation [Hz] Peak DC power [MW]
150 sec

r = 0.7 1.253 5.560 575.6 0.349 68.1 1.844

Initial setting 0.1 10 60.1 0.357 6.5 1.926

Without FLC 0.358 0 1.936

J0 =

(f ) dt
2 0

Note: J0 is Frequency deviation performance index From table 1, minimum frequency deviation occurs at 0.4 weighting with the optimum gain of 3.918 and optimum time constant of 3.331 seconds. The peak DC power for this setting is 164.6 MW. Other weightings give unsatisfactory result because the maximum frequency deviations are higher. It can be seen that, high peak power did not result in lower frequency deviation. For example, in the case of r equals to 0.2, the peak DC power is 300 MW with incremental energy 1479.3 MJ, the maximum frequency deviation is 0.358. This value of the maximum frequency deviation is the same as in the case of no HVDC compensation (without FLC). The incremental of DC power is limited at 300 MW because of the other AC side constraint. Figure 7 presents the frequency deviation of each weighting. The simulation of incremental DC power is shown in figure 8. According to the set up, the FLC should operate when system frequency deviation reached 0.25 Hz at 2.5 second. However, due to the first order delay function and the incremental DC power signal is calculated by PI-controller, delay in incremental DC power compensation naturally occurs.

The 15th Conference of Electric Supply Industry 2004, October 18-22, 2004, Shanghai, China
Frequency Deviation [Hz] 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 0.0 5.0 10.0 15.0 20.0 25.0 Time [sec] 30.0 35.0 40.0 45.0 50.0

Frequency Deviation
DC Power [MW] 325 300 275

Incremental DC power

r* = 0.4 r = 0.2

250 225 200 175 150 125 100 75 50 25 0 -25 0.0 5.0 10.0 15.0 20.0 25.0 Time [sec] 30.0 35.0 40.0 45.0 50.0

r* = 0.4 r = 0.2

r = 0.7

r = 0.7

Figure 7. Frequency deviation of varied weighting (r)

Figure 8. Incremental DC power of varied weighting (r)

Figure 9 presents the response of each power plant group and HVDC for optimum case. Each generation increases their generation after disturbance but DC power responds at 4 second. Figure 10 shows the improvement of system frequency regulation. The maximum frequency deviation with optimum setting is less than without FLC. The system frequency recovers back to the acceptable band approximately 4 seconds faster than without FLC.
Incremental Power [MW] 400 300 200 100 0 -100 -200 -300 -400 0 5 10 15 20 25 Time [sec] 30 35 40 45 50 Dynamic Response Frequency Deviation [Hz] 0.4
Frequency Deviation [Hz] 0.00 -0.05

Thermal DC Power CC-GT

0.3
-0.10

0.2 0.1 0
-0.15 -0.20 -0.25 -0.30 -0.35 -0.40 0 5 10 15 20 25 Time [sec] 30 35 40 45 50

Optimum setting

Hydro Frequency

-0.1 -0.2 -0.3 -0.4

Without FLC

Figure 9. Incremental power and frequency deviation of optimal solution

Figure 10. Comparison of frequency deviation

7. Conclusions
This paper explained the model for power system frequency control study, which included HVDC frequency limit control model. Simulation result showed that initial setting of controller gain and time constant were not appropriate and system frequency regulation was not improved even with DC power compensation form HVDC system. To improve FLC performance, the optimal control technique with the integral square error (ISE) as a performance index was suggested. The DC power transfer by FLC to one side of the interconnection was a disturbance of the other side. Therefore, the performance index was defined as an integral of the sum of square of incremental DC power with weighting factor (r) and the square of frequency deviation with respect to time. The optimum gain and time constant were then calculated for each weighting. The satisfactory result occurred at the weighting 0.4. The optimal parameters of PI-controller for this weighting were Kp = 3.918 and Tn = 3.331 second. The results indicated that system frequency could be improved with only necessary incremental DC power transfer.
References 1. Siemens, 2001, Pole Control Design Specification 2. Gran Andersson, 2003, Dynamic and Control of Electric Power Systems Lecture 35-528, ETH Zrich March 3. Siemens, 1995, Feasibility Study on Measures for Rapid Power Increase in Steam Power Plant (EGAT Power Reserve Study) 4. Atif S. Debs, 1996, Modern Power System Control and Operation: A Study of Real-Time Operation of Power Utility Control Centers 5. Siemens, 1998, HVDC Modulation Design Study Report