IRF9630, RF1S9630SM

Data Sheet January 2002

6.5A, 200V, 0.800 Ohm, P-Channel Power MOSFETs

These are P-Channel enhancement mode silicon gate power eld effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specied level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for other high-power switching devices. The high input impedance allows these types to be operated directly from integrated circuits. Formerly developmental type TA17512.

Features
6.5A, 200V rDS(ON) = 0.800 Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards

Ordering Information
PART NUMBER IRF9630 RF1S9630SM PACKAGE TO-220AB TO-263AB BRAND IRF9630 RF1S9630

Symbol
D

NOTE: When ordering, use the entire part number. Add the sufx 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S9630SM9A.

Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE

JEDEC TO-263AB

DRAIN (FLANGE)

2002 Fairchild Semiconductor Corporation

IRF9630, RF1S9630SM Rev. B

IRF9630, RF1S9630SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specied IRF9630, RF1S9630SM -200 -200 -6.5 -4 -26 20 75 0.6 500 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC
oC oC

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. TJ = 25oC to 125oC

Electrical Specications
PARAMETER

TC = 25oC, Unless Otherwise Specied SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(off) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured From the Contact Screw On Tab To the Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to the Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances
D LD G LS S

TEST CONDITIONS ID = -250A, VGS = 0V(Figure 10) VGS = VDS, ID = -250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC= 125oC VDS > ID(ON) x rDS(ON)MAX, VGS = -10V VGS = 20V ID = -3.5A, VGS = -10V (Figures 8, 9) VDS ID(ON) x rDS(ON)MAX, ID = -3.5A (Figure 12) VDD = -100V, ID -6.5A, RG = 50 RL = 15.4 (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = -10V, ID = -6.5A, VDS = 0.8 x Rated BVDSS Ig(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VDS = -25V, VGS = 0V, f = 1MHz (Figure 11)

MIN -200 -2 -6.5 2.2 -

TYP 0.500 3.5 30 50 50 40 31 18 13 550 170 50 3.5

MAX -4 -25 -250 100 0.800 50 100 100 80 45 -

UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH

Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain (Miller) Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance

4.5

nH

Internal Source Inductance

LS

Measured From the Source Lead, 6mm (0.25in) From Package to Source Bonding Pad Typical Socket Mount

7.5

nH

Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient

RJC RJA

1.67 80

oC/W oC/W

2002 Fairchild Semiconductor Corporation

IRF9630, RF1S9630SM Rev. B

IRF9630, RF1S9630SM
Source to Drain Diode Specications
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D

MIN -

TYP -

MAX -6.5 -26

UNITS A A

Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES:

VSD trr QRR

TJ TJ TJ

= 25oC, ISD = -6.5A, VGS = 0V (Figure 13) = 150oC, ISD = -6.5A, dISD/dt = 100A/s = 150oC, ISD = -6.5A, dISD/dt = 100A/s

400 2.6

-1.5 -

V ns C

2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 17.75mH, RG = 25, peak IAS = 6.5A. (Figures 15, 16).

Typical Performance Curves

1.2 POWER DISSIPATION MULTIPLIER 1.0

Unless Otherwise Specied

-10

0.8 0.6 0.4 0.2 0

ID, DRAIN CURRENT (A) 0 50 100 150

-8

-6

-4

-2

0 0 50 75 100 125 150 TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

1 THERMAL IMPEDENCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE PDM t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 10-1 t 1, RECTANGULAR PULSE DURATION (s) 1 10

ZqJC, NORMALIZED

0.01 10-5

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

2002 Fairchild Semiconductor Corporation

IRF9630, RF1S9630SM Rev. B

IRF9630, RF1S9630SM Typical Performance Curves

-100

Unless Otherwise Specied (Continued)

TC = 25oC TJ = MAX RATED SINGLE PULSE

-15

VGS = -10V

-9V VGS = -8V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

-12

VGS = -7V -9 VGS = -6V -6 VGS = -5V VGS = -4V

-10

10s 100s 1ms

-1

OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)

10ms 100ms DC

-3

-0.1 -1

-10 -100 VDS, DRAIN TO SOURCE VOLTAGE (V)

-1000

-10

-20

-30

-40

-50

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

FIGURE 5. OUTPUT CHARACTERISTICS

-20

ID, DRAIN CURRENT (A)

-16

VGS = -10V VGS = -9V VGS = -8V VGS = -7V

ID(ON), ON-STATE DRAIN CURRENT (A)

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

-15

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

-12 -55oC -9 25oC -125oC

-12

-8

VGS = -6V

-6

-4

VGS = -5V VGS = -4V

-3

-2

-4

-6

-8

-10

0 0 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) -10

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS

2.0 rDS(ON), DRAIN TO SOURCE ON RESISTANCE () NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5

FIGURE 7. TRANSFER CHARACTERISTICS

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

1.6

2.0

1.2 VGS = -10V 0.8 VGS = - 20V

1.5

1.0

0.4

0.5

0 0 -5 -15 -10 ID, DRAIN CURRENT (A) -20 -25

0 -40

40

80

120

160

TJ , JUNCTION TEMPERATURE (oC)

NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

2002 Fairchild Semiconductor Corporation

IRF9630, RF1S9630SM Rev. B

IRF9630, RF1S9630SM Typical Performance Curves

1.25 NORMALIZED DRAIN-TO-SOURCE BREAKDOWN VOLTAGE

Unless Otherwise Specied (Continued)

2000 VGS = 0V, f = 1MHz CISS = CGS + CGD C = CGD 1600 RSS COSS CDS + CGD 1200 CISS 800 COSS CRSS

1.05

0.95

C, CAPACITANCE (pF)

1.15

0.85

400

0.75 -40

40

80

120

160

10

20

30

40

50

TJ , JUNCTION TEMPERATURE (oC)

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

7.0

gfs, TRANSCONDUCTANCE (S)

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ISD, DRAIN CURRENT (A) TJ = -55oC

-100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TJ = 150oC -10

5.6

4.2

TJ = 25oC TJ = 125oC

2.8

-1.0

TJ = 25oC

1.4

0 0 -3 -6 -9 -12 -15 ID , DRAIN CURRENT (A)

-0.1 -0.4 -0.6 -1.0 -1.2 -1.6 -0.8 -1.4 VSD, SOURCE TO DRAIN VOLTAGE (V) -1.8

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT

FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

I D = -8A

VGS, GATE TO SOURCE (V)

-5

- 10

VDS = -160V VDS = -100V VDS = -40V

- 15 0 8 16 24 42 40

Qg(TOT) , TOTAL GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

2002 Fairchild Semiconductor Corporation

IRF9630, RF1S9630SM Rev. B

IRF9630, RF1S9630SM Test Circuits and Waveforms

VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0

VDD
+

0V

tP IAS -VGS

DUT

VDD

IAS tP VDS BVDSS

0.01

FIGURE 15. UNCLAMPED INDUCTIVE ENERGY TEST CIRCUIT

FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON td(ON) tr 0 RL 10%

tOFF td(OFF) tf 10%

DUT VGS RG

VDD
+

VDS VGS 0

90%

90%

10% 50% PULSE WIDTH 90% 50%

FIGURE 17. SWITCHING TIME TEST CIRCUIT

FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

CURRENT REGULATOR

-VDS (ISOLATED SUPPLY) 0 DUT VDS

12V BATTERY

0.2F
+

50k 0.3F Qgs D G DUT VDD Qgd Qg(TOT) VGS

0 IG(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR 0

IG(REF)

FIGURE 19. GATE CHARGE TEST CIRCUIT

FIGURE 20. GATE CHARGE WAVEFORMS

2002 Fairchild Semiconductor Corporation

IRF9630, RF1S9630SM Rev. B

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Rev. H4

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