IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO.

7, JULY 2010

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Closed-Loop Class-D Amplier With Nonlinear Loop Integrators

Benno Krabbenborg and Marco Berkhout, Member, IEEE
AbstractIn many integrated class-D audio ampliers large linear capacitors are used to create the triangular reference signals for generation of PWM signals. In this paper, an integrated class-D amplier is presented that uses a control loop with area efcient nonlinear gate oxide capacitors. A model is used to show that the nonlinearity does not degrade the THD performance. To limit the maximum voltage on the gate oxide capacitor, a method was used to prevent voltage drift of the integrator output in case the amplier is clipping. This method also improves the clipping recovery behavior. Measurements and simulations on two ampliers with linear and nonlinear capacitors conrm that nonlinear capacitors do not introduce additional distortion. Measurements on the amplier with and without the clipping recovery method conrm the improvement in clipping recovery. Index TermsClass-D ampliers, audio ampliers, power ampliers, switching ampliers, THD, distortion, nonlinear capacitors, pulse width modulation, clipping.

Fig. 1. Feed-forward PWM.

I. INTRODUCTION LASS-D ampliers have become a standard solution for many applications where good audio quality as well as high efciency are required. High efciency is realized with output transistors acting as switches with minimum power dissipation. Integrated Class-D ampliers appear in many applications varying from low-power mobile phones and hearing aids to home theatre sets and high-power ampliers. Many Class-D ampliers use pulsewidth modulation (PWM). is compared to a triangular reference signal An input signal at a much higher frequency. The output of the comparator gives the PWM signal. This signal can be amplied and with a low-pass lter the original audio signal can be reconstructed. of such a system is given by the ratio The voltage gain of the amplitudes of the PWM signal and the reference triangle . This method is called feed-forward PWM conversion and is shown in Fig. 1. Ideally, the spectrum of the PWM signal does not contain harmonics of the modulating signal, which means it can be considered ideal in terms of distortion. However, this is only true when the slopes of the triangular reference signal are perfectly linear. An analysis on distortion introduced by the carrier is given in [1]. In many integrated Class-D ampliers, integrators are used to create the triangular reference signal. An implementation of

Fig. 2. Closed-loop class-D amplier topology.

Manuscript received November 16, 2009; revised February 12, 2010; accepted March 15, 2010. Current version published June 25, 2010. This paper was approved by Guest Editor Ko Makinwa. The authors are with NXP Semiconductors, Eindhoven, The Netherlands (e-mail: benno.krabbenborg@nxp.com; marco.berkhout@nxp.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/JSSC.2010.2048084

an integrator using a capacitor and a square wave current requires a linear capacitor with a perfectly at CV characteristic. Unfortunately, integrated linear (metal) capacitors tend to be relatively large. Gate oxide capacitors have a much higher capacitance per area (up to 12 times), but suffer from nonlinearity that distorts the reference signal [2]. The goal of this paper is to show that nonlinear capacitors can still be used in a Class-D amplier without adding distortion. The outline of this paper is as follows. In Section II, the amplier topology is discussed and in Section III a low-frequency model is introduced. In Section IV the nonlinear capacitor is discussed and in Section V a model is presented to demonstrate the effect of the nonlinearity in the loop. With simulations the inuence of the nonlinear components on THD is discussed in Section VI. In Section VII, a method is presented to prevent the integrator output voltages from drifting apart during clipping. This way the clipping recovery behavior of the amplier is improved and the maximum voltage on the nonlinear capacitors is automatically limited. In Section VIII measurement data on THD and clipping behavior are presented that conrm the validity of the work. Finally, conclusions are given. II. AMPLIFIER TOPOLOGY For high-power ampliers, open-loop and closed-loop topologies are used. In open-loop ampliers, the power stage just amplies a digitally generated PWM signal to the supply

0018-9200/$26.00 2010 IEEE

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Fig. 3. Integrator signals V and V , oscillator signal osc and comparator output pwm during: (a) zero, (b) negative, and (c) positive input signal.

voltage. In such a system [3], the errors introduced by supply voltage variations or switching errors are not corrected and will appear as distortion in the output signal. To obtain proper audio performance the emphasis in such systems is put on the design of the power supply and the accuracy of the power stage. In a closed-loop topology, feedback is added to provide power supply rejection and correction of switching errors in the output stage. In this paper an analog input, xed frequency, closed-loop class-D amplier is discussed. The topology is described in detail in [4] and is shown in Fig. 2. The loop has two integrators congured around ampliers and that realize a second-order loop transfer. The output of the amplier is a square wave PWM signal. The signal is connected to the amplier by means of a low-pass load LC-lter . The output voltage is converted to by feedback resistor and injected into the a current virtual ground of the rst integrator . This yields a triangular at the output of this integrator . A reference clock wave signal osc is converted to a square wave current that is injected into the virtual ground of the second integrator . This at the output of yields a second (reference) triangular wave is proportional the second integrator. The amplitude of with the supply voltage in the same way as the amplitude of the is. Therefore, the amplitude of the trifeedback current is also proportional to the supply angular reference voltage voltage and keeps the loop gain supply voltage independent. and are fed to the inputs The triangular wave signals and intersect the comparator of a comparator . When of the amplier output pwm changes state and the output switches yielding the desired PWM signal. The peaks of signals and coincide with the edges of signal osc and pwm, reis converted to a current spectively. The input signal by V-I converter and injected into the virtual ground of the rst integrator . Fig. 3 shows the triangular wave signals and when (a) zero, (b) negative and (c) positive input signals are applied. to The input signal causes the slopes (and amplitude) of remains (almost) the same but the change. The shape of DC-level is shifted with respect to zero. In this manner a linear relation is realized between the input signal and the duty-cycle . of the output signal III. LOW-FREQUENCY MODEL For the analysis of the low-frequency (audio) behavior of the loop, all signals can be replaced with their average value over

Fig. 4. Time continuous model for the closed-loop class-D amplier.

one clock period. For the currents this means that only the net charge transfer over one clock period is relevant. Now the oscillator current disappears since the average current value is zero and the net charge per clock period is also zero. The comparator and output stage can be represented with a single gain block with a value equal to the ratio of the supply voltage (amplitude of ) and the reference triangle amplitude . (1) The resulting model can be seen in Fig. 4. In Fig. 5, a mathematical representation of the control loop can be seen for both the switched mode and time continuous model. Both the switched mode model and the time continuous model of Fig. 5 were simulated for a 20 kHz signal as can be seen in Fig. 6. can be easily derived. From Fig. 5(b) the loop transfer The loop transfer of the feedback loop is shown in Fig. 7 and is given by (2) where and . At low frequencies the loop transfer has a second order behavior. At higher frequencies bypasses the second a direct path from the rst integrator . This creates a zero in the loop transfer at the integrator unity-gain frequency of the second integrator: (3) The zero causes the loop transfer to have a rst order behavior of the loop. As is explained near the unity gain frequency is coupled to the PWM in [4] the unity gain frequency by a factor . The closed-loop switching frequency

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Fig. 5. Mathematical model for the control loop (a) switched mode, (b) time averaging approximation.

Fig. 8. CV characteristic for PMOS, NMOS, and a combination of both (schematic of combination in inset).

is proportional with output level ).

Fig. 6. Simulation results for both the switched mode and the continuous time and post lter model for a 20 kHz signal: (a) switching output voltage V output voltage V , (b) integrator output voltages V and V .

and frequency

for

IV. NONLINEAR CAPACITORS As mentioned in Section I, gate oxide capacitors are preferred over metal capacitors because of size. A simple way to create a gate oxide capacitor with a high capacitance value for both positive and negative bias is the use of a MOS transistor. The source, drain and back gate are tied together and form one of the capacitor terminals. The gate is the other terminal. Now consider a PMOS transistor. For positive voltages between the gate and the n-type back gate a mobile charge layer (electrons) below the gate oxide is formed (accumulation). Since the charge density can be much higher than the doping level, this gives a thin layer with high capacitance per unit area. For negative voltages below , an inversion layer is formed, again the threshold voltage with a dense mobile charge (holes) below the gate oxide. For low voltages a dip in the CV characteristic occurs. In this region depletion determines the capacitance and the doping level of the back gate limits the charge density. This charge is built up in a much thicker space charge layer below the gate oxide and gives a lower capacitance per unit area than inversion or accumulation. An NMOS transistor has a similar behavior. A parallel connection of a PMOS and an NMOS gives a quite symmetrical and smooth CV characteristic as shown in Fig. 8. Note that for low voltages the capacitance of the combination drops to about 40% of the maximum value that is reached at high voltages. To obtain a perfectly symmetric CV characteristic an antiparallel connection of two PMOS (or two NMOS) transistors can be used [2]. Both types have a parasitic capacitance from back gate to the substrate. For the antiparallel connection this results in a parasitic capacitance at both terminals of the capacitor.

Fig. 7. Second order loop transfer.

transfer from input current is now equal to

to amplier output voltage

(4) and can be expressed as a function of the output level and frequency: (5) (6)

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Fig. 9. Nonlinear function and 3 with an NMOS/PMOS combination.

V X as a function of V

for a capacitor

For the NMOS/PMOS combination, the parasitic capacitance of both transistors can be kept on one terminal of the capacitor, which is preferred for the use in the control loop discussed in the next section. V. CONTROL LOOP WITH NONLINEAR CAPACITORS The linearity constraint for the capacitors is essential if the triangular reference signal is directly compared to the input signal as shown in Fig. 1. Any nonlinearity in the reference directly appears in the transfer function from input voltage to duty cycle. In this section it is shown that the linearity constraint does not apply for the control loop presented in Section II. on a voltage-dependent capacitor with The charge voltage is given by the area below the CV characteristic between and . The effective capacitance can now be dened as (7) When compared to an integrator with a linear capacitor , the nonlinearity of the capacitor in the integrator can be modeled with a multiplication function in series with the integrator output: (8) can be seen in Fig. 9 for the case with the NMOS/PMOS combination. The integrator output voltage is a strictly increasing function of and is therefore bijective as can be seen in Fig. 9. The nonlinear function can be added as a gain block to the mathematical model from Fig. 5(a) as can be seen in Fig. 10(a). and are the voltages as they would be in the case of linear capacitors and . and are multiplied with the nonlinear functions and to and respectively. The block can be moved through the T-junction to the input of the comparator. For mathematical correctness an additional block must now be placed before as can be seen
Fig. 10. (a) Loop with nonlinear integrators, (b) after moving nonlinear blocks, (c) after eliminating nonlinear blocks, and (d) time averaging model.

in Fig. 10(b). As equals , both comparator inputs see the same nonlinearity. and are bijective functions of and , and the comparison of and is mathematically equivalent to the comparison of and . (At the moment the comparator decides, , and consequently ). The equal nonlinear blocks in series with the comparator inputs can therefore be eliminated as can be seen in Fig. 10(c). Note that this is not allowed when different weight factors are used for the integrator outputs before comparing as in [2]. The resulting low-frequency time averaging model for the loop with nonlinear integrators can be seen in Fig. 10(d). Since

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Fig. 11. Integrator signals V ; V and (scaled) output signal V for the loop with linear as well as with nonlinear capacitors and zero input signal.

Fig. 12. Loop after compensating the nonlinearity in series with R .

the comparator in Fig. 10(c) compares the voltages and , the value of in this model is equal to the value in case of linear capacitors. Fig. 11 shows the signals on the integrator outputs for the case with nonlinear capacitors as well as for the case with linear capacitors. Note the increased slopes for low voltages between the dashed lines (in the dip of the CV characteristic). The edges of for both cases are identical. The only nonlinear block left in Fig. 10(c) and (d) is in series with the resistor . Theoretically, for a rst order system (with ) this nonlinear block can be ignored, and the effect innite of the nonlinear capacitors on the resulting edges of the signal is fully cancelled. Note that the used topology does not is also required in the loop to allow comallow this, since pensation for offset of the second integrator or asymmetry in the oscillator current. From Fig. 10(d) we can conclude that cancelover one clock lation also occurs when the time average of period is zero. This is the case for zero input signal as can be seen in Fig. 11. In other cases however, the net amount of charge is unequal to zero, and transferred per clock period trough higher than in the case of linear capacitors. Since the nonlinear block amplies with to , the effective value of is reduced with a factor . The actual level of that determines this factor is proportional with output amplitude and frequency as can be seen in (5). Equations (2) and (3) show that and the zero frequency increase with the the loop transfer , which may lead to stability problems. For same factor low frequency and low output amplitudes, is close to zero, and the loop gain is a factor 2.5 higher than for the case with linear capacitors. The effect of the nonlinearity can be compensated with an inas can be seen in Fig. 12. For perfect verse nonlinearity compensation, is equal to . An implementation of such an inverse nonlinearity can be seen in Fig. 13. For low voltages (between and ) none of the transisdetermines the resistance. For volttors is conducting and ages below or above one of the transistors is conducting and the resistance reduces to the parallel connection of and . Fig. 14 shows in the linear case (constant), and in the inverse nonlinear case for the PMOS/NMOS combination. Also the effective value is shown for both cases. The reduction of the effective value for due to the division with is clearly visible. Using the inverse nonlinear resistance compensates this effect signicantly, though not perfectly.

Fig. 13. Implementation on the inverse nonlinear resistor for use in combination with the PMOS/NMOS capacitor (a) or with the antiparallel PMOS transistor (b).

Fig. 14. Resistance R and effective resistance of R =X for the linear case and the inverse nonlinear case for the PMOS/NMOS combination. All values are relative to the original resistance in the linear case R .

Fig. 15 shows the integrator outputs and the current through close to clipping for a loop with all linear components, with nonlinear capacitors and for the loop with both nonlinear capacitors and the inverse nonlinear resistance. Note that the increased current amplitude due to the nonlinear capacitors in Fig. 15(b) is compensated with the inverse nonlinear resistance in Fig. 15(c). VI. THD SIMULATIONS Fig. 16(a) shows a Fourier transform of the output voltage for a simulated signal with kHz for the loop with linear and nonlinear components. The modulation depth was 24% and all amplitudes are relative to the amplitude of the fundamental.

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Fig. 15. Integrator outputs V and V and current I nonlinear resistor.

for the loop with (a) all linear components, (b) nonlinear capacitors, and (c) nonlinear capacitors and inverse

Fig. 17. Simulated THD of a 1 kHz signal as a function of modulation depth M for the loop with all linear components and for the loop with nonlinear capacitors and inverse nonlinear resistors, for the NMOS/PMOS combination and for the anti-parallel PMOS connection.

loop with the symmetric nonlinear components has even slightly lower distortion than the loop with linear components. Although the simulated THD level for this model increases with modulation depth, it is unlikely to be the limiting factor in an integrated Class-D amplier as will be shown in the section on measurement results. The NMOS/PMOS combination has the advantage that all parasitic capacitors are kept to one of the terminals. This terminal was connected to the low impedance output of the opamps in the integrators. This makes the loop less sensitive to voltage spikes in the substrate.
Fig. 16. Fourier transform of a simulated 1 kHz signal for the loop with nonlinear capacitors and inverse nonlinear resistors (a) for the NMOS/PMOS combination, and (b) for anti-parallel PMOS connection.

VII. CLIPPING BEHAVIOR A. Drift of the Integrator Output Voltages A common requirement for audio ampliers is that the output can be driven rail-to-rail. It is customary to specify the output power of audio ampliers at 10% distortion, meaning that the output signal is clipping about 40% of the time. Clipping occurs when the current from the VI converter exceeds the feedback current through the feedback resistor . The does no longer change sign every input current for integrator period so that the output voltage drifts away from the normal will drift away (in the opoperating region. As a result, also posite direction) because the current through will follow . In Fig. 18(a) the drift of the integrators outputs can be seen for a clipping 10 kHz signal. When the input current is reduced to normal levels again, the integrator outputs need some time to return to their normal operating levels where they intersect every

Note that even the loop with linear components is not free of distortion and shows a third harmonic at 120 dB. This is because the use of a negative feedback loop itself adds some distortion [6]. As can be seen in Fig. 16(b) the loop with symmetric nonlinear components based on just PMOS transistors shows no signicant difference with the linear case. The loop with the NMOS/PMOS combination shows some additional peaks (offset) and at the second and fourth harmonic beat cause the CV characteristic is not perfectly symmetrical. In Fig. 17 the simulated THD can be seen as a function of modulation depth , again for three cases. Note that the even harmonics for the loop with the nonlinear NMOS/PMOS combination give a higher THD level than the other two cases. The

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Fig. 18. Clipping recovery: (a) Integrator outputs V and V for a 10 kHz signal, (b) post lter output V

for a 1 kHz signal.

Fig. 19. Improved clipping recovery: (a) Integrator outputs V and V for a 10 kHz signal, (b) post lter output V for a 1 kHz signal.

cycle. During this recovery the output sticks to the supply voltage. After the loop has resumed control, the error on the output voltage is corrected. This is visible as a second order response in the output voltage as can be seen Fig. 18(b) for a 1 kHz signal. This clipping recovery behavior is audible and is perceived as a ticking noise that is clearly different from the normal distortion that results from clipping. Since the amplier uses gate oxide capacitors, the voltage drift of the integrator outputs must be limited to avoid damage. In [5] a method is presented to improve the clipping recovery behavior and limit the maximum voltage on the gate oxide capacitors. B. Clip Detection As can be seen in Fig. 3, during normal operation, the edge of the oscillator signal osc is always followed by an edge of the comparator output pwm. During clipping the integrator outputs do not intersect, and pwm no longer changes sign. The sequence of osc and pwm is now disturbed: for clipping to the negative supply, osc is followed by without an edge of pwm. This can be easily detected with an asynchronous logic circuit and agged with a signal cliplow (or cliphigh for clipping to the positive supply). As soon the input current has returned to normal levels and the loop has resumed control, pwm changes sign again, and cliplow or cliphigh can be reset.

C. Drift Prevention After detecting clipping, the integrators are prevented from drifting apart by resetting the integrator outputs each clock this is done by temporarily interperiod. For integrator until the integrator output voltage rupting the input current is achieved by delaying is zero again. The reset of integrator the edge of the oscillator signal osc (signal oscdel) until the integrator output voltage has crossed zero. Since both integrator output voltages remain close to zero during clipping, the maximum voltage on the integration capacitors is also limited. When the input signal is back to a value below clipping level, no voltage drift needs to be corrected before returning to normal operation. As a result, the clipping recovery is very fast and without the sticking behavior as can be seen in Fig. 19. D. Implementation The amplier presented in this paper uses a slightly modied version of the clipping recovery method in [5]. Although this method shows a perfect clipping behavior, implementation introduces some non ideal effects that may cause sub harmonic oscillations during clipping. These oscillations occur when the reset of the integrators during clipping leads to an intersection of and . This intersection results in an unintended pwm edge that resets the clip mode and causes the amplier to toggle between clipping mode and normal mode every other cycle. Such

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Fig. 20. Total control loop with nonlinear capacitors C and C , inverse nonlinear resistor R and s .

and R

, sign comparators A

and A

and the switches s

can be seen for the modied method. Note that the integrator outputs are not reset to zero. Therefore, a small amount of drift is allowed and a few clock periods are required to recover after clipping. The resulting clipping recovery is however still very close to the ideal case in Fig. 19. VIII. MEASUREMENT RESULTS
Fig. 21. Relation between V and V

and cliplow and cliphigh.

an intersection can be caused when the required edge delay is too high, or by a large comparator delay. Therefore, two modications were introduced. The rst modication utilizes the division of in two and as can be seen in Fig. 13. During branches clipping, the control loop does no longer control the output voltage, and the resistance that is used to increase the loop gain no longer has a function. The current through this resistance is however responsible for the drift of the second integrator during clipping. To reduce the required edge delay is added in series with for the second integrator, a switch as can be seen in Fig. 20. In clip mode, switch is opened is left. The second and only the high-impedance branch modication deals with the reset voltage for the integrators. When the comparators for zero detection have some delay, the reset actions do not stop exactly when and equal and zero. Instead, there will be some overshoot for both that can cause an unintended intersection of and . A separation of the reference levels for the sign comparators and with a window is used to prevent this. When is reset to and is reset to . clipping occurs, , cliplow and In Fig. 21 the relation between cliphigh can be seen. In Fig. 22 the simulated clipping behavior

Both the loop with nonlinear capacitors and inverse nonlinear resistor based on the NMOS/PMOS combination as well as the method for improved clipping recovery were implemented in a Class-D amplier. The amplier was realized in a SOI-based BCD process [7]. This amplier was compared to an amplier with similar control loop using linear capacitors [4] made in an of older process node. Fig. 23 shows the measured SE application with a these two ampliers for a 100 W in symmetric supply voltage of 60 V ( 30 V, 30 V). Below 1 W level is dominated by thermal of output power, the noise that is equal for both ampliers. Above 1 W the level is dominated by harmonic distortion. In this region the results show that the amplier with nonlinear components does not show additional distortion and is even somewhat better. Note that the amplier with nonlinear capacitors was made in a more advanced process generation. So, although the topology was equal, also other implementation aspects besides the capacitors were different. One important difference is that the size of the power transistors was reduced signicantly while keeping equal on-resistance. This lowers the capacitive coupling from outputs to the substrate that is responsible for part of the distortion. Fig. 24 shows chip photographs of both ampliers. With linear capacitors, the die size of the amplier in Fig. 24(b) would have been 16% larger. Fig. 25 shows post-lter output signals measured on the class-D amplier of Fig. 24(b) with and without the clipping recovery system. As can be seen the measured signals are in good agreement with the simulations from Fig. 22.

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Fig. 22. Simulated clipping recovery for the loop in Fig. 20: (a) Integrator outputs V and V for a 10 kHz signal, (b) post lter output V for a 1 kHz signal. TABLE I CHARACTERISTICS OF THE AMPLIFIERS PRESENTED IN THIS PAPER AND THE AMPLIFIER USED FOR COMPARISON [4]

Fig. 24. Chip photographs (same scale) of the amplier with linear capacitors from [4] (a) and the amplier presented in this paper (b). The capacitors of one channel are indicated. Fig. 23. Measured THD versus output power for a 1 kHz signal for an amplier with linear capacitors [4] and the amplier presented in this paper with nonlinear capacitors and inverse nonlinear resistor.

IX. CONCLUSION Area-efcient, nonlinear gate oxide capacitors can be used in a Class-D amplier to save 16% in die area without introducing additional distortion. A model was described that allows

analysis of effects of the nonlinear components. The only effect of the nonlinearity is visible in the effective value of the resistance used to create the zero in the loop transfer. This can be compensated with an inverse nonlinear resistor. THD simulations and measurements on the amplier and a comparison with an amplier with linear capacitors conrm this. The improved clipping recovery method prevents the integrator outputs from

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Fig. 25. Measured clipping behavior for a 1 kHz signal for the amplier with nonlinear loop integrators (a) without and (b) with the improved clipping recovery.

drifting apart. This prevents the output from sticking to the supply voltage during clip recovery and it automatically limits the voltage across the nonlinear gate oxide capacitors in the integrators. Measurements on an amplier with and without the clipping recovery system conrm the improvement.

[7] P. Wessels, M. Swanenberg, H. van Zwol, B. Krabbenborg, H. Boezen, M. Berkhout, and A. Grakist, Advanced BCD technology for automotive, audio and power applications, IEEE J. Solid-State Circuits, vol. 51, no. 7, pp. 195211, Jul. 2007. Benno Krabbenborg received the M.Sc. degree in electrical engineering in 1990 and the Ph.D. degree in 1994, both from the University of Twente, Enschede, The Netherlands. His research dealt with electrothermal device modeling and simulation. In 1995, he joined Philips Semiconductors where he worked on reliability of power ICs. Currently, he is a Principal Design Engineer with NXP Semiconductors Nijmegen, The Netherlands. His main interests are class-D ampliers and integrated power electronics.

REFERENCES
[1] M.-T. Tan, H.-C. Chua, B.-H. Gwee, and J. S. Chang, An investigation on the parameters affecting total harmonic distortion in class D ampliers, in Proc. IEEE Int. Symp. Circuits and Systems, May 2000, pp. IV-193IV-196. [2] W. H. Groeneweg, Analog signal processing for a class D audio amplier in 65 nm CMOS technology, in Proc. ESSCIRC, 2008, pp. 322325. [3] F. Nyboe, C. Kaya, L. Risbo, and P. Andreani, A 240 W monolithic class D audio amplier output stage, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 13461355. [4] M. Berkhout, An integrated 200 W class-D audio amplier, IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 11981206, Jul. 2003. [5] M. Berkhout, Design of high power class-D audio ampliers, in Analog Circuit Design. Dordrecht: Springer Science & Business Media B.V., 2009, pp. 209229, ISBN: 987-1-4020-8943-5. [6] W. Shu and J. S. Chang, THD of closed-loop analog PWM class-D ampliers, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 17691777, Jul. 2008.

Marco Berkhout (M09) received the M.Sc. degree in electrical engineering in 1992 and the Ph.D. degree in 1996, both from the University of Twente, Enschede, The Netherlands. Currently, he is a Senior Principal Design Engineer with NXP Semiconductors Nijmegen, The Netherlands. His main interests are class-D ampliers and integrated power electronics. Dr. Berkhout received the 2002 ESSCIRC Best Paper Award, and was plenary invited speaker on audio at low and high power at the 2008 ESSCIRC.